7 System Verification Jobs

Key responsibilities and tasks for a Systems Engineer: Requirements Engineering : Gathering and analyzing user needs and system requirements. Collaborating with stakeholders to define and document system requirements. Considering factors like functionality, performance, security, and usability. System Design : Designing the architecture and components of the system. Developing system models and allocating requirements to subsystems. Ensuring integration of hardware, software, and other components. Focusing on scalability, reliability, and maintainability. System Integration : Integrating various components and subsystems into a cohesive system. Coordinating with different teams for effective integration. Performing integration testing and resolving compatibility issues. System Verification and Validation : Conducting verification and validation to ensure the system meets functionality and performance criteria. Developing test plans, performing tests, and analyzing results. Identifying and resolving discrepancies or issues. Risk Assessment and Management : Identifying and analyzing potential risks and uncertainties. Assessing the impact of risks on performance, safety, and reliability. Developing risk mitigation strategies and contingency plans.

The Product V&V (Verification and Validation) will be a part of the Engineering group that is responsible for implementing technical strategies, evaluate and develop products, and provide a superior level of technical support that benefits the organization. The Systems Engineer will lead the V&V effort / with a Product V&V focus collaborates closely with Engineers, Architects, and Test in the Ventilation business to develop and commercialize Class 2 medical devices. Responsibilities: Works together to support product verification and validation planning, resolution of technical integration issues, safety agency interface, system testing and coordination and interfaces with Philips design center. Provides engineering expertise in software and system verification and establishes system V&V plans, assists in developments of protocols and reviews reports. Implements design for testability by collaborating with R&D (Research and Development) teams to evaluate requirements for testability. Collaborates with external agencies for compliance and safety certification Incorporates essential operating mechanisms of systems engineering of medical device design and engineering principles and adheres to medical device regulations. Defines system requirements, architecture, and interfaces to meet product requirements, risk analysis and industry standards; conducts system design analysis to select key components and defines control methods; and coordinates build and design integration. Conducts design reviews as part of the product development process to ensure customer requirements are met and the designs are manufacture-able, serviceable, and reliable. In addition, it does the same for subsystem requirements and product integration. Behaviors: The successful candidate will demonstrate the following: Leadership: The ability to make things happen by encouraging and channeling the contributions of others; recognizing and addressing critical issues in a timely manner and acting as an agent for change and continual improvement when required to achieve results. Accountability/Ownership : Work closely with team members and take ownership be a mentor to junior engineers Influence : The demonstrated ability to gain acceptance and commitment from others to one's own beliefs and ideas. Negotiating: The ability to construct and maintain a strong bargaining position to ensure positive response and agreement: striving for win-win situations. Adaptability: Must possess the ability to understand new concepts quickly and apply them accurately throughout an evolving environment and organize work assignments to meet established timetables. Data-driven decision-making : ability to move teams through vague and complex situations. Present complex ideas in a simple manner to resolve issues. Relentless focus on Quality and Transparency as an organizational value. The systems team drives the systems elements of R&D development projects including systems requirement definition and management, architectural definition, control/software/interface product specification and simulation, build integration, system testing and qualification to meet product level requirements. Skills Required Building Architecture,Design Integration,System Verification,Medical Devices,Leadership,Medical Devices Design,Validation Plans,Verification and Validation (V&V),Process Development (PD),System Designs,Product Specifications,Results-Oriented,Product Development,FDA Medical Device Regulations,Design,Design Analysis,Medical Device Regulations,System Requirements,Research and Development Operations,Identifying Customer Needs,People Management,Product Requirements,Development Projects Location Pune, India Desirable Skills Building Architecture,Design Integration,System Verification,Medical Devices,Leadership,Medical Devices Design,Validation Plans,Verification and Validation (V&V),Process Development (PD),System Designs,Product Specifications,Results-Oriented,Product Development,FDA Medical Device Regulations,Design,Design Analysis,Medical Device Regulations,System Requirements,Research and Development Operations,Identifying Customer Needs,People Management,Product Requirements,Development Projects Designation Associate

System Verification : System and Unit Level Verification Defect Management Documentation of Test Plan, Case, Record, Report System Integration Automation experience appreciated typically 5+ Years of experience Skills Required Verification and Validation (V&V),Test Planning, Automation Systems, System Verification, Defects Management, Test Case Planning, Documentations, Systems Integration Location Pune, India Desirable Skills Verification and Validation (V&V),Test Planning, Automation Systems, System Verification, Defects Management, Test Case Planning, Documentations, Systems Integration Designation Associate

THE ROLE: Be a member of the team that plays a significant role in ensuring the quality of next generation microprocessors through structured DFT, Automatic Test Pattern Generation (ATPG) and Logic Built-In Self-Test (LBIST) techniques. Key responsibilities: Collaborating with the design teams to ensure DFT design rules and guidelines are met The person should have experience in timing concepts Generating high quality manufacturing test patterns for stuck-at, transition fault models and through the use of on-chip test compression techniques Exercising the LBIST circuitry and ensuring that repeatable signatures can be produced Simulating and verifying the ATPG and LBIST patterns Working with the product engineering teams on the delivery of manufacturing test patterns Developing, improving and maintaining scripts as vital Desired profile - The candidate must have detailed knowledge of DFT basics such as scan insertion, fault models, ATPG, BIST techniques, and on-chip compression techniques that reduce test time and tester memory. Experience with test tools such as FastScan and TestKompress is highly desirable.Scan/ATPG, knowledge of industry standard DFT features, simulation debug, MBIST Academic credentials: MS/M Tech/BE in Computer Engineering/Electronics/Electrical Engineering Demonstrated success in a senior ICteam role with similar skills Location: Hyderabad Telangana AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers and will consider all applicants without regard to race, marital status, sex, age, color, religion, national origin, veteran status, disability or any other characteristic protected by law. EOE/MFDV

Verification and Validation (V&V) is about providing objective evidence that the system/product, when in use, fulfills the requirements in the intended operating environment. Algorithms are cross-functional in nature, and the verification of these solutions is as critical as their design. This role requires excellent system understanding, system verification thinking, and close teamwork with hardware and software design, algorithm design, systems application, system architecture, and quality teams. Responsibilities: Drive the verification and validation effort of our key programs. Work with algorithm engineers and Embedded SW to understand requirements, specifications, and implementations to prepare and execute suitable verification and validation plans. Define a long-term verification and validation roadmap of capabilities, flows, and methodologies to continuously improve productivity. Creatively plan to test devices in corner cases where potential marginalities and issues could arise beyond the given specifications. Consult on required hardware system boards and software to automate test cases to achieve the best coverage at the highest efficiency. Qualifications Minimum BS in Electrical or Computer Engineering; MSEE or MSCE and 6+ years of experience preferred. Experience and Skills Experience in verifying complex algorithms such as battery state estimation and health algorithms (SoC, SoH, SoP) for automotive or industrial applications. Understanding the working theory of lithium-ion batteries and familiarity with new chemistries. Experience with machine learning and/or statistical analysis methods. Proficiency in C/C++ (embedded) and Python or other programming/scripting languages. Proficiency in MATLAB/Simulink Background in Systems Engineering and/or formal testing of complex systems (e.g., automotive). Excellent hardware and software troubleshooting skills. Experience with software compiler/debug tools, such as IAR, Keil, or Segger. Experience with software revision control, repositories, and regression testing (e.g., Git, Bitbucket, SVN). Ability to work in teams and collaborate effectively with people in different functions. Clear communicator with excellent verbal, written, and organizational skills. Motivated, proactive, fast learner, and hands-on. Nice to Have Background in automated software and system verification. Experience with requirements management tools (e.g., JAMA, DOORs). Experience with ARM-based microcontrollers (Cortex-Mx or Cortex-Rx series).

Role: System Verification & Validation System and Unit Level Verification Defect Management Documentation of Test Plan, Case, Record, Report System Integration Automation experience appreciated typically 5+ Years of experience

KEY EXPERTISE Seasoned ASIC Front End leader with 20 years of cross domain experience ranging from architecture, uArch, IP/Sub- systems/SOC/ chiplets design/integration, RTL coding, Synthesis, CDC, timing, power analysis, system/IP verification, Silicon Bring up. Proven track record of leading the design and development of complex IPs, sub-systems, chiplets for SOCs in the multiple domains like PCIE, USB, UCIE, ARM/x86 CPUs, RISC-V, VPU/NPU, GPU, LSIO, NOC, Fabrics, AMBA buses, DRAM, SD/SDIO/eMMC etc. Responsible for defining the technical direction of ASIC designs and collaborating with cross- functional teams to ensure successful ASIC implementation. Demonstrated strong leadership, project timelines & resources management and team management skills, and the ability to influence the technical strategy of the organization. Familiar with ASIC verification methodologies, DFT, Physical design and board design which help in influencing cross functional teams in getting desired results. Excellent execution capabilities to handle multiple domains in multiple projects simultaneously. Delivered superior results through team collaboration and diversity of thought. Always open to learn new technologies to grow in technical breadth and depth. Managed development of multiple sub-systems and IPs designed from scratch for Intel IOT (Elkhart Lake), Edge (Reefbay), dVPU/NPU (Arrow LakeR), GPU (DMR-D), Media (MTL-D), Smart NIC (Altera NIC), Palm Ridge, Mount Morgan IPU SoCs which are executed in advanced technology nodes of both Intel (18A, 3nm, 5nm) and TSMC (N3e, N5, N6). Have hands on experience in chiplets, Sub-systems and IP development (micro-architecture development, 3rd party IP integration (Synopsys, Verisilicon. SiFive RISCV, ARM cores etc.,), RTL implementation, synthesis, static timing analysis, Power analysis, system/IP level verification, FPGA emulation, Si bring-up) and SoC integration flows and methodologies. Led 30+ engineer design team and have good experience in working with cross-functional teams and cross BU teams across multiple geos, resulting in good collaboration and accelerated time to market. Led IP development (RTL design, Lint, CDC, Synthesis, timing, unit level and system level verification) of various IPs in Nvdia Tegra SoC processors (from first generation [APX] to ninth generation [Xavier]) and Cisco NIC chips. Have good working experience on low power design methodologies (clock gating, power gating, multi-vt and DVFS) used in mobile SoCs. Designed couple of modules in Tegra SoC like DMA engine, SD/SDIO/ eMMC5.2 host controller and bus-bridges for Nvidia proprietary buses. Worked on architecture, micro architecture, RTL design and timing analysis. Familiar with automotive electronics ISO26262 safety requirements. Was Executive member from Nvidia in SD card org and JEDEC (eMMC) forum. Participated in SD/SDIO4.x, SD host4.x and eMMC5.x specification development. Working experience with cross functional teams like back end, analog I/O pad and SW teams to ensure IP requirements are met at each stage. Have working experience in developing tree build and regression infrastructure. Have hands on experience in ASIC verification also - Test Planning, Develop Directed, Random and System-level (soc level) Test Cases; Design Test Bench using System Verilog; Develop Random Test environment; Execute Code Coverage & Analyse Reports, Execute Gate-level Simulations; Execute Functional & Regression Tests. Good Team Player: Participated and lead the effort of SD4.x/eMMC5.x host controller design and verification. Detail oriented go- getter with Fast Learning Curve and strong analytical, decision making, problem solving, visualizing, negotiating, communication & interpersonal skills. Mentored engineers, designed IP/SS schedules with proper staging plan with cross team dependencies, identified and solved technical issues, and ensured development of high-quality products.