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RTL ASIC Engineer (All Levels) Blueberry Semiconductors

1.0 - 15.0 years

0 Lacs

karnataka

On-site

As an ASIC designer with a minimum of 1-15 years of experience in RTL design using Verilog/System Verilog, you play a crucial role in the RTL design flow. Your responsibilities include: - Specification/Microarchitecture definition - Design and verification - Timing Analysis - DFT, and Implementation - Integration - RTL signoff tools - UPF/Low power signoff - CDC/RDC - Lint Your domain knowledge should encompass Clocking, System modes, Power management, debug, interconnect, safety, security, and other architectures. Your expertise in these areas will be invaluable in contributing to the success of the projects. As a highly motivated individual, you should be a self-starter with excellent inte...

Posted 2 weeks ago

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