3.0 - 7.0 years

0 Lacs

karnataka

On-site

As an experienced Digital Design Engineer with 3+ years of experience, you will collaborate with system architects to interpret high-level specifications and requirements for digital design. Your responsibilities will include creating RTL descriptions of digital circuits using hardware description languages such as Verilog and SystemVerilog to capture the desired functionality. You will implement digital logic functions, state machines, and control units to meet design goals for performance, power, and area (PPA). In this role, you will work with synthesis tools like Synopsys Design Compiler and Cadence Genus to optimize the RTL code for efficient gate-level implementation. You will address clock domain crossing (CDC) issues by synchronizing signals that cross different clock domains and implement low-power design techniques to reduce power consumption while maintaining functionality. Your tasks will also involve using static timing analysis (STA) tools to ensure that the design meets timing constraints and operates at the desired clock frequency. You will conduct functional simulation and RTL-level verification using tools like ModelSim to verify the correctness of the RTL code. Additionally, you will identify and address issues in the RTL code, collaborating with cross-functional teams to resolve them. Maintaining comprehensive documentation of the RTL code, design constraints, and any design-specific considerations will be essential in this role. You will also be responsible for integrating digital IP blocks from internal or external sources into the overall design, ensuring compatibility and functionality. Collaboration with physical design, verification, and DFT (Design for Test) engineers is crucial to ensure the successful integration of digital components into the complete IC design.,

Posted 2 days ago

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