2224 Synthesis Jobs - Page 9

ASIC RTL DESIGN ENGINEER (4 to 10 Years) IP/SoC Design Company: ACL Digital (Wafer space Semiconductor) Location [Bangalore/Pune/Chennai/Noida] Experience: 4 to 10 Years Openings: 6 Positions Job Description Sr RTL Design Engineer We are seeking a seasoned RTL Design Engineer with a strong background in microarchitecture and RTL coding. The ideal candidate will play a key role in designing state of the art solutions for automotive camera and display systems. Responsibilities Microarchitecture definition and RTL implementation ensuring optimal performance, power, area. Collaborate with software teams to define configuration requirements, verification collaterals etc. Work with verification teams on assertions, test plans, debug, coverage etc. Proficiency in Verilog/System Verilog Very google understanding of ASIC design methodologies Qualifications and Preferred Skills Graduate/Post Graduate/PhD in Electrical/Electronics 4-10 years hands-on experience in microarchitecture and RTL development Proficiency in developing micro-architecture from the design requirements, defining the H/W- S/W interface. In-depth understanding of MIPI CSI and DSI protocols Experience designing IP blocks for video and audio design Proficiency in Verilog, System Verilog Familiarity with industry-standard EDA tools and methodologies Experience with large high-speed, pipelined, and low power designs Excellent problem-solving skills and attention to detail Strong communication and collaboration skills Experience in designs complying to automotive functional safety will be a plus

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill collaborate closely with cross-functional teams to ensure the successful delivery of highquality designs Responsibilities: Responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs. Understand Design Architecture and timing requirements Develop timing constraints SDC and validate Work with Physical design to close SDC related timing issues. Analysis of timing from synthesis to verify constraints. Work with architects and logic designers to generate block and full chip timing constraints. Analyse scenarios and margin strategies with Synthesis & Design team. Work on SDC for block, partition, Fullchip such as define constraints, IO budgeting, merging constraints. Work with third party IP, derive timing signoff requirements. Requirements: Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. Total 4+ years of experience in STA, timing closure related work. Hands-on experience in ASIC timing constraints generation and timing closure. Tool Knowledge on Timevision, Fishtail, Genus, Prime Time, Tempus, Tweaker is MUST. Deep understanding and experience in various functional and test modes. Good fundamental on Physical design implementation. Validate timing constraints for Block and Partitions. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization.Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule. Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Ability to work cross-functionally with various teams and be productive under aggressive schedules. Proven ability to lead and mentor junior engineers, fostering their professional growth and development. Preferred Qualifications: Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Has at least worked on full chip STA closure of large size silicon. Tool Knowledge on Fishtail, Timevision and other standard tool for constraint development. Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for STA integration. Familiarity with low-power design techniques and methodologies, such as multivoltage domains and power gating using UPF

We are seeking an exceptional Senior Physical Design Engineer to take a key role in our semiconductor design team. As a Senior Physical Design Engineer, you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs Key Responsibilities Perform Synthesis, floor planning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs. Define and drive physical design strategies to meet aggressive performance, power, and area targets. Conduct detailed analysis of timing, power, and area, and drive design optimizations to improve QoR. Block/Partition signoff closure for STA, PV, LEC, IR/EM, CLP very efficiently. Provide technical leadership and guidance to the physical design team, mentoring junior engineers and fostering a culture of excellence. Work closely with RTL design and DFT teams to understand design requirements and constraints, and drive successful tapout of designs. Support and Development of advanced physical design methodologies and flows for complex semiconductor designs. Requirements Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. 4+ years of experience in physical design of ASICs Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics for Synthesis, PnR, Signoff Closure. Extensive experience with timing closure techniques, power optimization. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization. Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule. Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Proven ability to lead and mentor junior engineers, fostering their professional growth and development. Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Expertise in Synthesis that includes details understanding of RTL, Early PnR timing issues, Constraint issue, design issues. Experience in handling Partitions and blocks for size estimation, pin assignment, CTS. Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration. Detailed Knowledge on Clocking methodology and various techniques to improve skew, latency, timing, power. Familiarity with low-power design techniques and methodologies, such as multi-voltage domains and power gating using UPF. Expertise in physical verification, including DRC, Antenna, LVS, PERC, and ERC checks. Expertise in Timing Closure including setup, hold, DRV, SI, Interface issues. Experience with formal verification for RTL to Netlist and Netlist to Netlist. Knowledge of emerging technologies such as machine learning and AI for design automation and optimization.

This job might be for you if You enjoy solving problems. You love taking on difficult challenges and finding creative solutions. You dont know the answer but will dig until you find it. You communicate clearly. You write well. You are motivated and driven. You volunteer for new challenges without waiting to be asked. You will take ownership of the time you spend with us and make a difference. You can impress our customers with your enthusiasm to solve their issues (and solve them!) Job Description Required Solid RTL coding experience including Microarchitecture of design System Verilog and Verilog coding using provided coding styles. Understanding of SDC Understanding STA reports and how to adjust RTL accordingly. Designing for error cases and debug of IP Understanding of CDC logic Knowledge of lint rules and exceptions Design and use of block level simulations to bring up IP. Knowledge of AMBA buses and when to use them. Job Description Preferred Experienceleading small design team. C coding / Firmware skills Knowledge on common processor architectures(ARM, RiscV) FPGA experience includes part selection, pin assignment, timing constraints, synthesis, and debug of design in the FPGA. Lab brings up experience, scripting. Relevant tool experience such as: Socrates, Core Consultant in additionto standard simulation tools (xcellium, vcs, etc) Emulation experience(Zebu, Palladium, etc) Board knowledge, component selection, probing, debug. JTAG debugging experience (Coresight, Lauterbach, etc). Low power design techniques Qualifications E./B.Tech. degree at minimum.

We are seeking a skilled and detail-oriented Engineer specializing in Synthesis, Physical Synthesis, and pre-layout Static Timing Analysis (STA). The ideal candidate will have strong expertise in various aspects of digital design implementation, including UPF generation, synthesis optimizations, and constraint development. This role is crucial for ensuring the functional correctness, performance, and power efficiency of our semiconductor designs. Key Responsibilities: Perform Synthesis, Physical Synthesis, and pre-layout Static Timing Analysis (STA) for complex digital designs. Responsible for UPF (Unified Power Format) generation from scratch to define power intent for low-power designs. Execute synthesis of RTL code into gate-level netlists. Implement Multi-Vt (Multi-Threshold Voltage) optimizations to achieve power and performance targets. Implement and optimize Clock Gating techniques for power reduction. Perform Datapath Synthesis to ensure efficient data flow implementation. Conduct Scan Insertion for Design For Testability (DFT). Ensure designs are Multi-supply/Switching aware for robust power management. Implement and verify DVFS (Dynamic Voltage and Frequency Scaling) techniques. Perform Retiming to optimize critical paths for timing closure. Undertake Constraint Development , ensuring accurate and comprehensive timing constraints. Possess IP constraint knowledge on interfaces like DDR3/4, Multiprotocol SerDes, ARM core and Subsystem, USB3.0 , which is a significant plus. Required Skills and Qualifications: Strong expertise in digital design Synthesis and Physical Synthesis . Proficient in pre-layout Static Timing Analysis (STA) . Experience with UPF generation . Knowledge of Multi-Vt optimizations, Clock Gating, Datapath Synthesis, Scan Insertion, Multi-supply/Switching awareness, DVFS, and Retiming . Strong skills in Constraint Development . Familiarity with IP constraints on DDR3/4, Multiprotocol SerDes, ARM core and Subsystem, USB3.0 is highly desirable.

Role: AI ML Engineer Experience: 4 - 7 Years Qualification: B.Tech Location: Gurugram - Onsite • Build and deploy GenAI Models with techniques such as RAG and Fine Tuning. • Developing AI/ML algorithms to analyze huge volumes of historical data to make predictions and recommendations. • Implement and optimize deep learning models for generative tasks such as image synthesis, voice etc • Collaborate with software engineers to integrate Generative AI models into production systems • Should be able evaluate the application cases and problem-solving potential of AI/ML algorithms and rank them according to success likelihood. • Should be able to comprehend data through exploration and visualization, spot discrepancies in data distribution • Should be able to work on structured as well as unstructured data • Should be able to develop various algorithms based on statistical modelling procedures and build and maintain scalable machine learning solutions in production • Should be able to leverage cloud platforms for training and deploying large scale solutions (AWS Preferred) • Should have working knowledge on managing ModelOps framework • Should understand CI/CD processes in product deployment and used it in delivery. • Should be able to collaborate with data engineers to build data and model pipelines and maintain accuracy • Should be able to take complete ownership of the assigned project • Experience of working in Agile environments • Well versed with JIRA or equivalent project tracking tool

We are looking for talented RTL Designers to join our SoC Digital Design Team. This role involves contributing to the development of high-performance SoCs for the mobile space. The ideal candidate will have strong expertise in RTL-based digital design, excellent communication skills, and the ability to collaborate effectively with diverse global teams involved in the ASIC design lifecycle. You'll get the opportunity to work on cutting-edge SoCs that are shaping the future of mobile technology. Responsibilities: Develop micro-architecture and RTL implementation for System-on-Chips (SoCs). Take responsibility for block-level or full-chip integration and design . Be hands-on with Lint, CDC (Clock Domain Crossing), and LEC (Logic Equivalence Checking) tools, with a preference for experience in Low Power check tools . Possess a good understanding of design implementation flows and tools such as Synthesis, STA (Static Timing Analysis), and DFT (Design For Testability) . Have a good understanding and hands-on experience with database management flows , preferably ClearCase/ClearQuest . Collaborate with the functional verification team to review test plans and coverage . Experience with AXI/AHB protocols is essential. Knowledge of Networks on Chip Fabric and I/O protocols like SDCC/DDR/USB/UART/SPI would be a significant plus. Work seamlessly with global teams including ASIC design, IP, architecture, implementation, DFT, power, STA, PD, software, firmware, and validation teams. Required Skills and Qualifications: Excellent inter-personal and communication skills. Strong knowledge of digital design principles. Proficiency in RTL implementation. Familiarity with design verification processes.

Job Title: RTL Design Engineer Experience: 3–5 Years Company: eInfochips (An Arrow Electronics Company) Location: Ahmedabad/ Noida Job Type: Full-Time Job Description: eInfochips is looking for talented RTL Design Engineers with 3–5 years of experience in digital design. You will be working on IP and SoC-level RTL development for leading semiconductor clients across domains like Automotive, Consumer, Industrial, and AI. Key Responsibilities: RTL design using Verilog/SystemVerilog for IP and SoC subsystems Perform synthesis, linting, CDC/RDC analysis Interface with verification, physical design, and architecture teams Support SoC integration and debug Ensure design quality and timing closure Required Skills: 2+ years of hands-on RTL design experience Strong in digital design concepts (FSMs, pipelining, FIFOs) Proficient with tools like Synopsys Design Compiler, SpyGlass, VCS Experience with standard protocols (AXI, AHB, APB) Basic scripting skills (TCL, Perl, Python) How to Apply: 📩 Send your resume to: Nshalini.singh@einfochips.com

As a Principal Physical Design Engineer (CAD) at Ampere, you will be part of a dynamic Processor Design group pioneering the realm of high-performance implementation and physical design. Your role will involve developing and maintaining physical design flows for cutting-edge designs that push the boundaries of technology. Your responsibilities will include collaborating closely with the implementation and physical design team, addressing flow issues through debugging, evaluating the impact of technology changes on area, power, and timing by running test designs, and automating new flow practices to enhance design efficiency. To excel in this role, you should hold an M.Tech in Electronics Engineering or Computer Engineering with a minimum of 6 years of semiconductor experience, or a B.Tech in the same field with at least 8 years of relevant experience. You should have a strong background in physical design CAD flow encompassing synthesis, place & route, and floor planning, and it would be advantageous to have experience in power distribution, static timing analysis, and physical design verification. Your expertise should extend to hierarchical P&R and flow development, with proficiency in floorplanning, power distribution, pad ring construction, placement, clock tree synthesis, and routing. Proficiency in scripting languages like TCL, Perl, and Makefile is crucial, along with a knack for developing intricate algorithms and managing P&R flows effectively. Furthermore, familiarity with chip-finishing aspects such as metal fill, spare cells, DFM rules, and boundary cells for the latest process technologies is desirable. Adept communication skills and problem-solving abilities will be key in your success in this role. At Ampere, we offer a competitive benefits package that includes premium medical, dental, and vision insurance, parental benefits, retirement plans, and generous paid time off to support your well-being and work-life balance. Our inclusive culture encourages employees to innovate, grow, and contribute to sustainable future designs. Join us at Ampere to be a part of a team that is shaping the future of computing and cloud technology. #LI-SF1,

Qualcomm India Private Limited is looking for a Hardware Engineer with over 12 years of experience in SoC design. You should have a strong understanding of AMBA protocols such as AXI, AHB, and APB, as well as SoC clocking, reset, debug architecture, and peripherals like USB, PCIE, and SDCC. Knowledge of memory controller designs and microprocessors would be an added advantage. In this role, you will be responsible for constraint development and timing closure, working closely with SoC verification and validation teams for pre/post Silicon debug. Hands-on experience in Low power SoC design is required, along with expertise in Synthesis and understanding of timing concepts for ASIC. You should also have experience in Multi Clock designs and Asynchronous interface. Familiarity with tools in ASIC development such as Lint, CDC, Design compiler, and Primetime is necessary. Minimum qualifications include a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 6+ years of Hardware Engineering experience, or a Master's degree in the same field with 5+ years of experience, or a PhD with 4+ years of experience. If you are an individual with a disability and need accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. For reasonable accommodations, you may contact disability-accommodations@qualcomm.com. Qualcomm expects all employees to adhere to applicable policies and procedures, including security and confidentiality requirements. Please note that Qualcomm's Careers Site is for individuals seeking jobs at Qualcomm. Staffing agencies and individuals represented by agencies are not authorized to use this site. Unsolicited submissions from agencies will not be accepted. For more information about this role, please contact Qualcomm Careers.,

JOB NAME : AMS Verification Engineer (Mandatory to have AMS verification with UVM test : As per market : Hyderabad Please Note : it will be virtual interview, WFO initially later depends on the project and project manager, General Description : The position involves design verification of next generation IPs /SoCs with emphasis on verifying and signing off performance and power along with functionality by developing the needed RNM models . This role will require the candidate to understand and work on all aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies including simulation, GLS . Candidate Will Require Close Interactions With Design, SoC , Validation, Synthesis PD Teams For Design Convergence. Candidate Must Be Able To Take Ownership Of IP/Block/SS To work in AMS Verification domain with UVM test batch relevant experience in mixed signal SOCs or subsystems/IPs. Leading a project for AMS requirements is a value add. Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools. Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. Candidate should be familiar with the concepts of behavioral modeling both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus. Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected. Experience working on AMS Verification on multiple SOCs or sub-systems. Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus. Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment. Delivery oriented, Passionate to learn and explore, Transparent in communication, Flexibility related to project situations. Candidates should have a good knowledge of analog and mixed signal electronics, test-plan development, tools and flows. Develop and execute top-level test cases, self-checking test benches and regressions suites. Developing and validating high-performance behavior models. Verifying of block-level and chip-level functionality and performance. Team player with good communication skills and previous experience in delivering solutions for a multi-national client. Tool suites : Predominantly analog (Cadence Virtuoso). SPICE simulator experience. Fluent with Cadence-based flowCreate schematics, Simulator/Netlist options etc.. Ability to extract simulation results, capture in a document and present to the team for peer review. Supporting silicon evaluation and comparing measurement results with simulations. UVM and assertion knowledge would be an Level : 8-12 years in Industry(3+yrs Requirements : Bachelor or Masters degree in Electrical and/or Computer Qualifications : Proficient in at least one of the following languages : Verilog, System Verilog, Verilog AMS. Strong understanding of analog circuits, digital design processes, and top-level integration. Basic knowledge of PMIC and DC-DC converters. Excellent simulation debugging skills, with the ability to analyze waveforms and identify issues in schematics, models, or RTL. Proficient in Unix environment and shell scripting, with a basic understanding of Qualifications : Mentoring skills. Exceptional problem-solving skills. Good written and oral communication Perks : Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun. Equity Rewards (RSUs). Employee Stock Purchase Plan (ESPP). Insurance plans with Outpatient cover. National Pension Scheme (NPS). Flexible work policy. Childcare support. (ref:hirist.tech)

AIML Incubator Internship Opportunity IQVIA is offering an exciting opportunity to work on cutting-edge problem-solving using Generative AI and automation technologies. If you're passionate about innovation, thrive in a fast-paced environment, and want to make a tangible impact across teams—this role is for you! What You’ll Do Conduct research and experimentation with state-of-the-art generative AI models, including but not limited to LLMs, diffusion models, and audio/video synthesis models. Explore and evaluate the latest AI technologies to address business use cases, prototype solutions, and present demos Develop and integrate Retrieval-Augmented Generation (RAG) pipelines to enhance the contextual relevance and accuracy of generative model outputs. Apply Prompt Engineering techniques to optimize LLM behavior across diverse tasks and domains. Design and implement scalable, efficient AI-driven solutions tailored to diverse team needs. Collaborate with stakeholders to validate solutions and refine outcomes Design and manage scalable deployment pipelines for AI models using Azure and other cloud platforms. Benchmark and evaluate AI/ML services across major cloud providers (Azure, AWS, GCP) for performance, cost, and scalability. What We’re Looking For Strong problem-solving skills and a creative mindset. Proficiency in Python and experience with AI/ML frameworks (e.g., PyTorch, TensorFlow). A self-starter with a strong passion for AI/ML research, automation, and innovation who constantly learns and applies new AI frameworks and tools. Proven ability to work independently and deliver high-impact results. Excellent communication skills for presenting ideas and solutions clearly. Location: This role requires working from our Kochi office on a daily basis. We believe in the value of in-person collaboration to drive innovation and team synergy. Duration: 12 months Come join Us to Shape the Future with Generative AI & Automation! IQVIA is a leading global provider of clinical research services, commercial insights and healthcare intelligence to the life sciences and healthcare industries. We create intelligent connections to accelerate the development and commercialization of innovative medical treatments to help improve patient outcomes and population health worldwide. Learn more at https://jobs.iqvia.com

The job requires a deep understanding of protocols such as USB, PCIE, MIPI, JEDEC, I2C, and SPI. You will be responsible for designing and verifying RTL code for high-speed SerDes digital blocks. Your communication skills, both verbal and written, should be excellent. Experience in synthesizing complex SoCs block/top level and writing timing constraints is necessary. You should also have experience in formal verification RTL-to-netlist and netlist-to-netlist with DFT constraints, as well as post-layout STA closure and timing ECOs. Previous work in technology nodes of 45nm and below is preferred. Your mandatory skills should include Timing Closure, STA, ECOs, Synthesis, and SDC. A qualification of BE/B.Tech in VLSI/ECE is required. You should have at least 3 years of experience in the verification of analog mixed signal blocks. Proficiency in tools such as Cadence AMS tools, Verilog, VerilogA, and VAMS languages is essential. For any career-related inquiries or applications, please reach out to hr@terminuscircuits.com.,

Qualcomm India Private Limited is a leading technology innovator that strives to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, your responsibilities will include planning, designing, optimizing, verifying, and testing electronic systems. This involves working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment, packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge products. Collaboration with cross-functional teams is essential to meet performance requirements and develop innovative solutions. To qualify for this position, you should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field along with 4+ years of Hardware Engineering experience. Alternatively, a Master's degree with 3+ years or a PhD with 2+ years of relevant work experience would be considered. We are seeking bright ASIC design engineers with strong analytical and technical skills to be part of a dynamic team responsible for delivering Snapdragon CPU design for Mobile, Compute, and IOT markets. Key responsibilities include participating in ASIC development projects, focusing on Place and Route Implementation, Timing Closure, Low Power, Power Analysis, and Physical Verification. You will be involved in creating design experiments, conducting PPA comparison analysis, and collaborating closely with RTL design, Synthesis, low power, Thermal, Power analysis, and Power estimation teams to optimize Performance, Power, and Area (PPA). Additionally, developing Place & Route recipes for optimal PPA, tabulating metrics results for analysis, and contributing to the ASIC flow with low power, performance, and area optimization techniques are crucial aspects of this role. The ideal candidate should have 10-15 years of High-Performance core Place & Route and ASIC design Implementation work experience. Proficiency in Place & Route with FC or Innovus, experience with STA using Primetime and/or Tempus, and strong problem-solving skills are preferred qualifications. Knowledge in constraint generation and validation, power domain implementation, formal verification, scripting languages like Perl/Tcl, Python, C++, as well as exposure to Verilog coding and CPU micro-architecture will be advantageous. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact disability-accommodations@qualcomm.com. The company's work environment is inclusive and supportive of individuals with disabilities. Applicants should adhere to all relevant policies and procedures, including security measures and confidentiality of company information. Qualcomm does not accept unsolicited resumes or applications from staffing agencies. For more information about this role, please reach out to Qualcomm Careers.,

You will be responsible for executing block level P&R and Timing closure activities, including owning up block level P&R and performing Netlist2GDS on blocks. You will work on the implementation of multimillion gate SoC designs in cutting edge process technologies such as 28nm, 16nm, 14nm, and below. Your role will require strong hands-on expertise in physical design aspects like Synthesis, Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning, Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS), DFM, and DFY, and Tapeout. You should have expertise in analyzing and converging on crosstalk delay, noise glitch, and electrical rules in deep submicron processes, along with an understanding of process variation effects. Experience in variations analysis/modeling techniques and convergence mechanisms would be a plus. Proficiency in Synopsys ICC2 and PrimeTime physical design tools is essential for this role. Additionally, skill and experience in scripting using Tcl or Perl are highly desirable. Qualifications required for this position include a BE/BTech or ME/MTech degree with a specialization in the VLSI domain. The ideal candidate should have 5-10 years of relevant experience in the field.,

Job title: HSE Auditor Location: Hyderabad About The Job Sanofi is a global life sciences company committed to improving access to healthcare and supporting the people we serve throughout the continuum of care. From prevention to treatment, Sanofi transforms scientific innovation into healthcare solutions, in human vaccines, rare diseases, multiple sclerosis, oncology, immunology, infectious diseases, diabetes and cardiovascular solutions. As a company with a global vision of drug development and a highly regarded corporate culture, Sanofi is recognized as one of the best pharmaceutical companies in the world and is pioneering the application of Artificial Intelligence (AI) with strong commitment to develop advanced data standards to increase reusability & interoperability and thus accelerate impact on global health. The Global M&S Services acts as a cornerstone to this effort. Our team is responsible for delivering and supporting M&S teams in the area of regulatory compliance, maintenance of product licenses and technical writing of CMC documents. Within the international team in charge of HSE Audits “Third Parties”, your mission will consist in leading and analyzing HSE audits on third parties’ sites and providing feedback to Global HSE and other internal partners (External Manufacturing, Procurement, CSR, etc.). Main Responsibilities Carry out HSE audits on suppliers and service-providers’ sites: Organize and conduct the audit according to Sanofi process, on site or remotely. Establish a diagnosis of major HSE risks of the supplier that could affect Sanofi's legal liability, reputation and supply continuity. Write the audit report and executive summary. Communicate them to stakeholders and organize immediate mitigation plans in case of critical risks. Follow up the corrective action plans. Check the relevance of planned actions and their implementation (on site or remotely). Ensure documentation traceability within Sanofi tools. Contribute to continuous improvement: Inform local internal partners (Procurement, external manufacturing) of audit outcome and contribute to the optimization of third-parties portfolio. Prioritize critical situation and escalate identified risks. Provide Global HSE with trend analysis and valuable data linked to your audit perimeter, proposing process optimization initiatives and updates and regulation evolutions. About You Experience: 10 – 14 years of experience in the pharmaceutical industry. Soft skills: Personal and professional skills: Analysis and synthesis skills. Interview / audit techniques. Communication and transversal collaboration skills. Great autonomy Rigor and method. Knowledge of multicultural environments Frequent trips are to be within the country of location and abroad (around 15 - 20 weeks per year). Technical skills: Expertise in HSE practices: management system, process safety, fire explosion risk, occupational exposure, air emissions, water release, waste, management of pharmaceuticals in the environment, etc. Industrial experience. HSE experience on an industrial or R&D site. Local regulatory knowledge (China & India) Education: Scientific training (general engineer / organic chemistry / chemical engineering). Languages: Fluent English is essential. Why choose us? Bring the miracles of science to life alongside a supportive, future-focused team. Discover endless opportunities to grow your talent and drive your career, whether it’s through a promotion or lateral move, at home or internationally. Enjoy a thoughtful, well-crafted rewards package that recognizes your contribution and amplifies your impact. Take good care of yourself and your family, with a wide range of health and wellbeing benefits including high-quality healthcare, prevention, and wellness programs and at least 14 weeks’ gender-neutral parental leave. Opportunity to work in an international environment, collaborating with diverse business teams and vendors, working in a dynamic team, and fully empowered to propose and implement innovative ideas. null Pursue Progress . Discover Extraordinary . Join Sanofi and step into a new era of science - where your growth can be just as transformative as the work we do. We invest in you to reach further, think faster, and do what’s never-been-done-before. You’ll help push boundaries, challenge convention, and build smarter solutions that reach the communities we serve. Ready to chase the miracles of science and improve people’s lives? Let’s Pursue Progress and Discover Extraordinary – together. At Sanofi, we provide equal opportunities to all regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity, protected veteran status or other characteristics protected by law.

Aquaworks Private Limited As a part of the global industrial organization Marmon Holdings—which is backed by Berkshire Hathaway—you’ll be doing things that matter, leading at every level, and winning a better way. We’re committed to making a positive impact on the world, providing you with diverse learning and working opportunities, and fostering a culture where everyone’s empowered to be their best. Supervises a team of scientists who conduct theoretical or applied scientific research aimed at advancing technical knowledge and/or solving complex problems. Monitors progress of projects and reviews experiments to ensure that they adhere to established quality standards. Marmon Water Research Center – IIT-Madras ICCW, Chennai, India Position: Domain / Subject Matter Expert, Membrane Modification/ Adsorbent/Absorbent Innovation [Alternative: Sorption Innovation (Ion Exchange, Adsorption, Absorption] Marmon Water, Inc., a Marmon Holdings, Inc., Berkshire Hathaway Company, has established a research and innovation center at IIT-Madras ICCW Chennai, India. Marmon Water is an international leader in water treatment technologies, systems and chemistries with manufacturing and product development centers located in the United States, India, China and Singapore. The Marmon Water Research Center – India will be dedicated to working with all Marmon Water Business Units to develop innovative technologies that will be disruptive to our industry. Reports to: Director, Marmon Water India Research Center Responsibilities And Duties Independently research new sorption technologies: membranes/ adsorbent/ absorbents/ exchangers In collaboration with the Business Unit Technical Teams, maintain and update a pertinent literature and patent library, periodically report on status. Examine other global literature sources as available. In collaboration with the Business Unit Technical Teams, find, review and screen new technologies based on technical viability, potential IP position and ultimate cost to implement. Develop promising technologies to a proof of concept stage up to and including lab scale technology/process studies to prove/define process and viability. Document and report on all efforts. Interactively support ongoing development of technologies once past proof of concept stage. Directly design, conduct and analyze sorption experiments in coordination with the Business Units’ technical team. The Candidate Will Be Expected To Work with the business units to find, evaluate and develop new technologies from worldwide sources (universities, startups and other companies). Staff and develop a high-level team that can: Design patentable solutions through the proof-of-concept stage for handoff to the business units’ technical teams. Technology focus will be on water treatment solutions to improve water quality and consumer health. The candidate will need to have a working knowledge of Intellectual Property processes both in India and the United States. Understanding user needs through the eyes of our business and marketing teams; solving problems with unique technology(ies). Selection Criteria Qualifications: Ph.D. in Polymer/Organic Chemistry, Material Sciences, or closely related field. Preference to: Candidates who have shown a background in functional polymer synthesis and water treatment. 1-2 years minimum experience in a technology discovery/development role in water related field. Experience with experimental design Experience with polymer modification Experience in Analytical Instrumentation and analytical methods to support development and performance evaluation. Including: NMR, ICP-MS, GPC, GC-MS, FTIR, SEM, TGA, extractables, others Experience in contaminant reduction technologies a plus. Self-starting/motivated. Able to assess work, draw conclusions and move forward independently. Outstanding organizational skills. Lead by example – including conducting laboratory experiments, Strong team skills – will need to work sufficiently closely with Marmon Water Business Units. If chosen, candidate will be part of the Marmon Water Sorption Team, which meets monthly by conference call to discuss sorption related technologies and challenges in testing. Proficient computer skills (Microsoft Office, i.e., Word, Excel, PowerPoint, etc.). Physical Demands/Work Environment: Work in a laboratory environment safely with chemicals/materials/apparatuses as needed to develop/demonstrate sorption technologies. Due to the nature of this position, the applicant will be exposed to potentially hazardous substances. Leadership ability: Proven track record of accomplishment leading research efforts and teams. Technical achievement: Proven expertise in chosen discipline including patents and publications. Has presented at international academic or industrial conferences in English. Ideal Competencies Results oriented leader. Hands-on leader who leads by example. Collaborative. Strategic Thinker. Mastery of US English. Excellent presentation skills. Able to achieve results with limited resources. Desirable Personal And Professional Characteristics Candid, ethical, integrity Empathetic Able to make tough decisions. Travel International and regional travel required. Travel 10-20%. Salary Range Competitive salary and benefits. Marmon Water is seeking candidates for the position of Domain Expert, functional materials, to be a part of our innovative technology teams. The candidate must have knowledge of synthesis of the functional polymers and its characterization using NMR, FTIR, TGA, GPC etc. The candidate should have a personal and professional interest in clean-water technologies with a background in functional polymers/media / resin/membrane development and testing. The ideal candidate will hold a PhD in Polymer Chemistry, Materials Science, or similar with a research emphasis on the design or evaluation of advanced water treatment technologies. Candidates not having this specific research background will be considered if they have worked in a technology development role in the design or evaluation of media and fiber technologies to remove contaminants form water. The candidate will be responsible for coordinating research activities between the MW Business Units and the MWRC – India. The preferred candidate will have proven leadership experience, but will be expected to build equipment, carry out experiments and enjoy working in the laboratory. The preferred candidate will have a background in research and development, and experience in writing and evaluating patents. The ideal candidate will work with Marmon Water worldwide technical teams to find and evaluate new technologies to treat known and emerging contaminants. Travel up to and including 30% should be expected. This person will report to the Director of the Marmon Water Indian Research Center. The Domain Expert, Functional Polymer, will be working alongside other Domain Experts and is expected to generate innovative ideas and solutions for water treatment technologies (in the sorption field). Semiannual trips to international locations for collaboration both internal and external to Marmon Water will be expected. As the Marmon Water Research Center – India is being developed, Marmon Water seeks out candidates who are willing to work in a start-up like atmosphere. This is a great opportunity to build a research program and team to deliver innovative technologies to the water treatment market. Following receipt of a conditional offer of employment, candidates will be required to complete additional job-related screening processes as permitted or required by applicable law.

About the Company: Think of TEKsystems Global Services (TGS) as the growth solution for enterprises today. We unleash growth through technology, strategy, design, execution and operations with a customer-first mindset for bold business leaders. We deliver cloud, data and customer experience solutions. Our partnerships with leading cloud, design and business intelligence platforms fuel our expertise. We value deep relationships, dedication to serving others and inclusion. We drive positive outcomes for our people and our business, and we stay true to our commitments and act in harmony with our words. We exist to create significant opportunity for people to achieve fulfillment through career success. Website https://www.teksystems.com/en/careers-in-india Position Summary: We are seeking a highly skilled and experienced AI/ML Engineer with 3-5 years of hands-on experience in developing and deploying advanced AI solutions, specifically focusing on Generative AI and Agentic AI. The ideal candidate will possess a strong understanding of large language models (LLMs), prompt engineering, and the principles behind building autonomous AI agents capable of reasoning, planning, and taking actions to achieve complex objectives. You will be instrumental in designing, implementing, and integrating these cutting-edge AI systems on leading cloud platforms (AWS, Azure, or GCP). Key Responsibilities: • Generative AI Development: Design, develop, and implement advanced generative AI models (e.g., LLMs, GANs, VAEs, Diffusion Models) for diverse applications such as content creation, code generation, data synthesis, or other relevant domains. • Agentic AI System Design & Implementation: Architect, develop, and deploy autonomous AI agents capable of breaking down complex goals, making decisions based on context, interacting with external tools and APIs, and taking multi-step actions to achieve objectives with minimal human intervention. • Prompt Engineering & Orchestration: Master prompt engineering techniques to optimize the behavior and output of LLMs and design sophisticated orchestration mechanisms for coordinating multiple AI agents in complex workflows. • Cloud Platform Deployment: Leverage expertise in AWS, Azure, or GCP to deploy, manage, and scale Generative and Agentic AI models and pipelines. Utilize relevant cloud services (e.g., AWS SageMaker, Azure ML, Google AI Platform, Kubernetes, serverless functions, MLOps tools). • Model Training & Optimization: Train, fine-tune, and optimize generative and agentic AI models for performance, scalability, reliability, and efficiency, utilizing large datasets and advanced techniques. • Tool Integration for Agents: Integrate AI agents with various external tools, APIs, and data sources to expand their capabilities and enable them to interact with real-world systems. • Data Management for AI: Work with large and diverse datasets, including data collection, cleaning, transformation, and feature engineering, to ensure high-quality input for both generative and agentic models. This includes handling unstructured data (PDFs, HTML, audio, video) for processing. • Research & Innovation: Stay abreast of the latest advancements in Generative AI, Agentic AI, LLMs, and multi-agent systems research. Experiment with new frameworks (e.g., LangChain, AutoGen, CrewAI, LangGraph, Semantic Kernel) and identify opportunities to apply novel techniques. • MLOps & Productionization: Implement robust MLOps practices for the full lifecycle of AI models, including versioning, continuous integration/continuous delivery (CI/CD), monitoring, and automated retraining. Ensure the reliability and scalability of deployed AI systems. • Evaluation & Responsible AI: Develop and implement rigorous evaluation frameworks for assessing the performance, safety, and ethical implications of generative and agentic AI systems. Promote and adhere to principles of responsible AI development. • Collaboration & Communication: Collaborate effectively with cross-functional teams (data scientists, software engineers, product managers, business stakeholders) to translate business requirements into technical solutions and communicate complex AI concepts clearly. Required Skills & Qualifications: • Bachelor's or Master's degree in Computer Science, Artificial Intelligence, Machine Learning, Data Science, or a closely related quantitative field. • 3-5 years of hands-on experience in AI/ML engineering, with a demonstrable focus on Generative AI and/or Agentic AI projects. • Strong practical experience with Generative AI models (e.g., LLMs, Transformers, GANs, Diffusion Models) and their applications. • Hands-on experience in designing, building, and deploying autonomous AI agents or multi-agent systems, utilizing frameworks like LangChain, AutoGen, CrewAI, or LangGraph. • Proficiency in Python and strong experience with major ML frameworks such as TensorFlow, PyTorch, or Keras. • Demonstrated experience with prompt engineering techniques for optimizing LLM behavior. • Proven ability to deploy and manage AI/ML solutions on at least one major cloud platform: o AWS: Experience with services like SageMaker, EC2, Lambda, Bedrock, Open Search. o Azure: Experience with Azure Machine Learning, Azure Functions, Azure OpenAI Service. o GCP: Experience with Google AI Platform (Vertex AI), Cloud Functions. • Solid understanding of machine learning algorithms, deep learning architectures, natural language processing (NLP), and information retrieval techniques (e.g., RAG). • Familiarity with containerization technologies (Docker, Kubernetes). • Experience with MLOps principles and tools for model deployment, monitoring, and lifecycle management. • Excellent problem-solving, analytical, and critical thinking skills. • Strong verbal and written communication skills, with the ability to articulate complex technical concepts to diverse audiences. Preferred Skills (Nice to Have): • Experience with vector databases (e.g., Pinecone, Weaviate, FAISS, Azure AI Search) and knowledge graphs. • Familiarity with full-stack development, including building RESTful APIs using frameworks like FastAPI, Flask, or Django. • Experience with model evaluation tools like DeepEval, FMeval, or RAGAS. • Knowledge of prompt engineering frameworks (e.g., LangChain, LlamaIndex). • Knowledge of reinforcement learning and multi-agent reinforcement learning. • Contributions to open-source AI projects or relevant publications. • Experience with data orchestration tools (e.g., Apache Airflow).

Greetings!!! We are seeking for a API - Research & Development Synthesis role for a Pharma Manufacturing Company at Chennai . Role & responsibilities: Develop and optimize synthetic routes for APIs and intermediates. Conduct lab-scale experiments and process development for scale-up. Perform literature surveys and impurity profiling. Interpret analytical data (NMR, HPLC, GC, IR) for structural confirmation. Prepare development reports and support tech transfer to kilo/pilot plant. Ensure compliance with GMP, EHS, and regulatory requirements. Collaborate with cross-functional teams (QA/QC, Regulatory, Manufacturing). Maintain accurate documentation for regulatory submissions (DMF, ANDA, etc.). Interested Candidates kindly share your updated cv to srinidhi@bvrpc.com

Applications are invited from interested and motivated candidates for the post of Junior Research Fellow (JRF) in a time bound research project for a temporary period, purely on contractual basis as per the following details. Position Junior Research Fellow (JRF) Number of Vacancy 01 Project Title High temperature corrosion and mechanical behavior of AM fabricated Haynes 282 alloy Department Mechanical Engineering Project Tenure 3 years Job Description The project aims to investigate the corrosion behavior and high temperature mechanical behavior of additively manufactured Haynes 282 alloy. Knowledge about Selective Laser Melting, corrosion, Fatigue, microstructural characterization is required. Strong communication and writing skills are desirable. Essential Qualification Minimum requirement: B.Tech in Mechanical Engineering/Materials Engineering/ Materials and Metallurgical Engineering with a valid GATE score. Desirable: M.Tech in Mechanical Engineering/ Materials Engineering/ Materials and Metallurgical Engineering with a valid GATE score. Age Limit JRF-28Yrs. Age relaxation The upper age limit is relax-able up-to 5 years in the case of candidates belonging to scheduled castes/tribes/OBC, women and physically handicapped candidates. Fellowship Junior Research Fellow (JRF)- Rs.37,000/-p.m. Principal investigator Dr. Devasri Fuloria Assistant Professor Senior (Grade I) School of Mechanical Engineering Vellore Institute of Technology Vellore, Tamil Nadu - 632014 Send your resume along with relevant documents pertaining to the details of qualifications, GATE/NET score card, scientific accomplishments, experience (if any) and latest passport size photo etc. on or before (5/08/2025) through online http://careers.vit.ac.in Please note that the CV should include contact details (address, mobile phone no., email ID), date of birth, qualifications mentioned clearly. Complete information regarding publications of research papers in SCI Journals should be mentioned in the CV. Incomplete applications will be rejected. No TA and DA will be paid for appearing in the interview. Shortlisted candidates will be called for an interview at a later date which will be intimated by email. The selected candidate will be expected to join at the earliest.

Perform Sub system level floor planning, placement, and routing for high-performance microprocessor design. Collaborate with cross-functional teams to achieve design goals. Close the design to meet timing, power, and area requirements. Implement engineering change orders (ECOs) to rectify functional bugs and timing issues. Ensure the quality and efficiency of the RTL to GDS2 implementation process. Required education Master's Degree Preferred education Bachelor's Degree Required technical and professional expertise 8+ years of industry experience Good knowledge and hands on experience in physical design , timing and methodology which include logic synthesis, placement, clock tree synthesis, routing , post route closure. Should be knowledgeable in physical verification ( LVS,DRC. etc) ,Noise analysis, Power analysis and electro migration . Good knowledge and hands on experience in static timing analysis (closing timing at chip level) good understanding of timing constraints . Should have experience in handling asynchronous timing, multiple corner timing closure.

We are seeking highly motivated individuals with a BS, MS, or PhD degree in Computer Science, Computer Engineering/ECE, ready to handle the challenging problems in future technologies and designs. We are also looking for candidates with Strong C/C++background to lead our leading-edge algorithmswithin our EDA solutions to increase our design team’s productivity and chip quality and performance. Our dynamic global team is looking to enlist enthusiastic professionals to join world-class hardware design teams responsible for developing the most challenging and complex systems in the world. We are seeking energetic, highly motivated individuals willing to go the extra mile with the aim of helping the overall IBM development team. Strong interpersonal skills are needed to coordinate deliverables and requirements from several areas within and outside of the organization.There are many opportunities to gain and utilize a deep understanding of future issues and provide input towards decisions affecting system development, logical and physical design as well as sophisticated methodology directions. Individuals who are chosen to become a part of our world class development teams will be helping advance IBM’s leadership in developing the highest performing computers and changing hardware solutions. Do you want to be an IBMerCome THINK with us! Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 4+ years of IT experience Strong C/C++programming skills in a Unix/Linux environment is a must. VLSI knowledge, Knowledge in front end linting tools and checkers and RTL Checkers. Great scripting skills – Perl / Python/Shell Proven problem-solving skills and the ability to work in a team environment are a must Preferred technical and professional experience RTL Lint Checkers , Front end verification flow, VLSI knowledge, VHDL/Verilog, computer architecture

DYNAMICNEXT is one of the leading Game Development Studios in India. Our focus is on creating top-quality mobile games for international markets. We have launched several successful game titles, received millions of downloads, and have a strong player community. We are looking for a Generative AI Engineer with hands-on experience in developing generative AI solutions. The ideal candidate should be skilled in working with AI systems and capable of handling creative AI tools that enhance game development workflows. Key Responsibilities Design and implement generative AI systems using tools like ChatGPT, Midjourney, Stable Diffusion, Runway, ElevenLabs, and 3D platforms such as Luma AI, Meshy, Scenario, Kaedim, Triplo3D Research and experiment with GenAI models across modalities to generate images, videos, audio, narrative, and 3D assets Build, fine-tune, and evaluate open-source or foundation models as needed to improve content quality or fit specific game styles Develop pipelines for generating low-poly 3D models, props, and environments, optimized for Unity integration Engineer scalable, modular, and automatable AI content pipelines and infrastructure to accelerate asset creation workflows Collaborate with engineers, product managers, game designers, analytics teams, and artists to ensure technical alignment and creative fidelity Stay current with emerging AI frameworks, APIs, and research, integrating promising technologies into the studio’s content production stack Key Attributes Familiarity with prompt engineering and fine-tuning Experience working with game assets is a plus Strong creative thinking to apply generative AI in narrative, level design, or game asset generation. Ability to experiment, prototype rapidly, and iterate based on feedback. Experience with text-to-image, text-to-animation, or voice synthesis tools. Desired Profile Bachelor’s or Master’s degree in Computer Science, Artificial Intelligence, Machine Learning, or a related field. 1–3 years of hands-on experience with AI systems, with a strong focus on generative models. Demonstrated experience in building or integrating AI tools into creative pipelines—ideally within gaming, animation, or interactive media. Passion for AI and games Open to experimentation and learning Join us and build the next big thing in gaming. Apply Now!

Aquaworks Private Limited As a part of the global industrial organization Marmon Holdings—which is backed by Berkshire Hathaway—you’ll be doing things that matter, leading at every level, and winning a better way. We’re committed to making a positive impact on the world, providing you with diverse learning and working opportunities, and fostering a culture where everyone’s empowered to be their best. Under close supervision, conducts analyses and experiments on organic and inorganic substances to determine and evaluate their chemical and physical properties and to investigate their applications. Learning role with 1 to 3 years of experience. Reports to: Marmon Water Research Center – IITM Research Park, Chennai, India Position: Junior Chemist Marmon Water, Inc., a Marmon Holdings, Inc., Berkshire Hathaway Company, has established a research and innovation center at IIT-Madras ICCW Chennai, India. Marmon Water is an international leader in water treatment technologies, systems and chemistries with manufacturing and product development centers located in the United States, India, China and Singapore. The Marmon Water Research Center – India will be dedicated to working with all Marmon Water Business Units to develop innovative technologies that will be disruptive to our industry. Research Scientist Expert Responsibilities And Duties Performed laboratory experiments related to polymer/adsorbent modifications for water treatment applications with minimal supervision. Designing and executing laboratory testing of modified polymer/adsorbent/membranes in line with standard testing procedures, recording observations, and interpreting findings. Recording all experimental data and test results accurately and in the specified format (written and/or electronic.) Ensuring that safety guidelines are adhered to at all times within the laboratory. Maintaining daily logs and equipment record books. Cleaning, maintaining, and calibrating laboratory equipment. Keeping up to date with relevant scientific and technical developments. The Candidate Will Be Expected To Adaptability & flexibility Self-motivated Hardworking Selection Criteria Qualifications: MSc (Organic/Polymer/Analytical Chemistry) Ideal Competencies 1-3 years of academic /industrial research experience in water treatment Experience in organic synthesis, polymer modifications and characterization. Basic understanding of polymer membranes would be advantageous. Following receipt of a conditional offer of employment, candidates will be required to complete additional job-related screening processes as permitted or required by applicable law.

Amex GBT is a place where colleagues find inspiration in travel as a force for good and – through their work – can make an impact on our industry. We’re here to help our colleagues achieve success and offer an inclusive and collaborative culture where your voice is valued. What You’ll Do on a Typical Day Work in a SCRUM team Design, develop and test new applications and features Participate in the evolution and maintenance of existing systems Contribute in the deployment of features Monitor the platform Propose new ideas to enhance the product either functionally or technically What We’re Looking For Operational knowledge of C# or python development, as well as in Docker Experience with PostgreSQL or Oracle Knowledge of AWS S3, and optionally AWS Kinesis and AWS Redshift Real desire to master new technologies Unit test & TDD methodology are assets Team spirit, analytical and synthesis skills Passion, Software Craftsmanship, culture of excellence, Clean Code Fluency in English (multicultural and international team) What Technical Skills You’ll Develop C# .NET and/or Python Oracle, PostgreSQL AWS ELK (Elasticsearch, Logstash, Kibana) GIT, GitHub, TeamCity, Docker, Ansible #GBTJobs Location Gurgaon, India The #TeamGBT Experience Work and life: Find your happy medium at Amex GBT. Flexible benefits are tailored to each country and start the day you do. These include health and welfare insurance plans, retirement programs, parental leave, adoption assistance, and wellbeing resources to support you and your immediate family. Travel perks: get a choice of deals each week from major travel providers on everything from flights to hotels to cruises and car rentals. Develop the skills you want when the time is right for you, with access to over 20,000 courses on our learning platform, leadership courses, and new job openings available to internal candidates first. We strive to champion Inclusion in every aspect of our business at Amex GBT. You can connect with colleagues through our global INclusion Groups, centered around common identities or initiatives, to discuss challenges, obstacles, achievements, and drive company awareness and action. And much more! All applicants will receive equal consideration for employment without regard to age, sex, gender (and characteristics related to sex and gender), pregnancy (and related medical conditions), race, color, citizenship, religion, disability, or any other class or characteristic protected by law. Click Here for Additional Disclosures in Accordance with the LA County Fair Chance Ordinance. Furthermore, we are committed to providing reasonable accommodation to qualified individuals with disabilities. Please let your recruiter know if you need an accommodation at any point during the hiring process. For details regarding how we protect your data, please consult the Amex GBT Recruitment Privacy Statement. What if I don’t meet every requirement? If you’re passionate about our mission and believe you’d be a phenomenal addition to our team, don’t worry about “checking every box;" please apply anyway. You may be exactly the person we’re looking for!