2205 Synthesis Jobs - Page 7

Job Title: IP Design Technical Lead/ Staff ASIC RTL Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and forward-thinking digital design expert with a strong foundation in ASIC RTL design and a proven track record of delivering complex, high-performance IP cores. With a Bachelor’s or Master’s degree in EE, EC, or VLSI and over four years of relevant industry experience, you thrive in dynamic, multi-site environments and excel at translating functional specifications into robust, scalable architectures. You’re adept at working with advanced protocols such as Ethernet, DDR, PCIe, and USB, and have hands-on experience in data path and control path design, including Reed Solomon FEC, BCH codes, and MAC SEC engines. Your expertise extends to synthesizable Verilog/SystemVerilog coding, timing closure, CDC analysis, and P&R-aware synthesis, complemented by a keen understanding of design trade-offs in area, latency, and throughput. You are comfortable leveraging version control systems like Perforce and scripting languages such as Perl or Shell to automate and streamline workflows. As a natural leader, you are ready to mentor and technically guide a team of designers, fostering a collaborative and inclusive culture. Communication comes easily to you, and you’re known for your proactive problem-solving skills, attention to detail, and unwavering commitment to design quality. You’re seeking an opportunity to take ownership of challenging projects, contribute to cutting-edge innovation, and grow alongside a team of world-class engineering professionals. What You’ll Be Doing: Architecting and implementing state-of-the-art RTL designs for the DesignWare IP family, targeting commercial, enterprise, and automotive applications. Translating standard and functional specifications into detailed micro-architectures and comprehensive design documentation for medium to high complexity features. Leading and contributing hands-on to RTL coding, synthesis, CDC analysis, debug, and test development tasks. Collaborating with global teams and engaging directly with customers to understand and refine specification requirements. Driving technical excellence in design processes, including linting, static timing analysis, formal checking, and P&R-aware synthesis using tools such as Fusion Compiler. Mentoring and technically leading a team of designers, providing guidance on best practices and innovative design methodologies. Utilizing version control systems and scripting to manage design flows and automate repetitive tasks for improved efficiency. The Impact You Will Have: Enable Synopsys to deliver industry-leading, high-performance IP cores that power next-generation technologies. Contribute to the successful execution of complex, global projects that set new standards in chip design and verification. Accelerate time-to-market for customers in commercial, enterprise, and automotive sectors by delivering robust, reliable IP solutions. Elevate the technical capabilities of your team through mentorship and leadership, cultivating a culture of continuous learning and innovation. Drive improvements in design quality, efficiency, and scalability through process optimization and automation. Directly influence product architecture and feature enhancements, ensuring alignment with customer needs and emerging industry trends. What You’ll Need: Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related field. 4+ years of hands-on industry experience in ASIC RTL design, with a strong portfolio of completed projects. Deep expertise in data path and control path design, including experience with Reed Solomon FEC, BCH codes, CRC architectures, and MAC SEC engines. Proficiency in synthesizable Verilog/SystemVerilog, simulation tools, and design flows including lint, CDC, synthesis, and static timing analysis. Familiarity with high-speed design (>600MHz), P&R-aware synthesis, and EDA tools such as Fusion Compiler. Experience with version control systems (e.g., Perforce) and scripting languages (Perl, Shell) for design automation. Knowledge of industry protocols: Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA (AMBA2, AXI). Exposure to quality processes in IP design and verification is an advantage. Prior experience as a technical lead or mentor is highly desirable. Who You Are: Innovative thinker with a solutions-oriented mindset and a passion for technology. Excellent communicator who thrives in collaborative, multicultural, and multi-site environments. Natural leader with mentoring abilities, fostering inclusion and diversity within the team. Detail-oriented professional with strong analytical and problem-solving skills. Self-motivated, adaptable, and eager to drive technical excellence and process improvements. Committed to continuous learning and staying ahead of industry trends. The Team You’ll Be A Part Of: You will join the R&D Solutions Group at our Bangalore Design Center, as part of the DesignWare IP Design team. This diverse and innovative group is dedicated to architecting, developing, and delivering cutting-edge IP cores that enable Synopsys’ global customers to achieve their design goals. The team thrives on collaboration, technical excellence, and shared success, working in a supportive environment that values creativity, knowledge sharing, and continuous growth. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

As an Applications Engineer (AE) at Synopsys, you will play a crucial role in driving innovation and shaping the future in the Era of Pervasive Intelligence. You will have the opportunity to work with high-end customers in the Mobile Industry Processor Interface (MIPI) domain, providing top-tier technical support and guidance with your strong technical background in ASIC design. Your role will involve partnering with customers through the full cycle of ASIC design, conducting reviews on major design milestones, and ensuring successful integration of Synopsys MIPI IP solutions into customers" SoCs. Your impact will be significant as you enhance customer satisfaction by providing expert support, drive innovation through collaboration on cutting-edge SoC designs, and contribute to the development of industry-leading IP solutions. You will expand Synopsys" market presence in the MIPI domain and support the growth of Synopsys" IP portfolio by addressing customer needs and promoting the adoption of Synopsys IP through impactful documentation. To succeed in this role, you will need a Bachelor's degree with 5+ years or a Master's degree with 2+ years of relevant experience in the ASIC design process. Proficiency in Verilog HDL, synthesis, simulation, and verification is required, and knowledge of Place and Route, Design Reuse, Physical Design, or Analog Design is a plus. Familiarity with MIPI UFS/UniPro protocols, high-speed SERDES, or parallel interfaces is advantageous, as well as experience with Synopsys tool suites. Strong verbal and written communication skills in English are essential. As an Applications Engineer at Synopsys, you will join a dedicated and innovative team focused on supporting customers in the Synopsys Intellectual Property (IP) domain. You will have the opportunity to collaborate with a customer-centric approach, drive customer success, and advance the capabilities of Synopsys IP solutions. Synopsys offers a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process. If you are an excellent communicator, a problem solver who thrives in a dynamic environment, a collaborative team player with a passion for technology and continuous learning, then you are the perfect fit for this role.,

We're excited to welcome applications for fully-funded PhD positions in our pioneering research team at Amrita Vishwa Vidyapeetham, Amritapuri campus Research Domains: Our group specializes in cutting-edge experimental and analytical research across: - Supercapacitor development for next-generation energy storage - Advanced sensors for biomedical, environmental, and industrial applications - Focus on material synthesis, electrochemical characterization, and device fabrication Ideal Candidates: Students from interdisciplinary backgrounds who bring curiosity and commitment, including: - Chemistry - Physics - Chemical Engineering - Strong knowledge of analytical chemistry We especially encourage applicants with interest in electrochemical analysis, energy materials, biosensing platforms, and smart diagnostics. We Offer: - Collaborative research with real-world impact - Publishing, patenting, and networking opportunities - Access to world-class facilities and global academic collaborations

NVIDIA is seeking a passionate, creative, and highly motivated engineer to work on architectural power estimation for the world’s leading GPUs and SOCs. In this position, the responsibility includes development of advanced power models to estimate chip and board power under product driven use cases. You are expected to understand the high-level chip architecture, application use-cases, low power design techniques, process technology aspects which impact dynamic and leakage power, develop the estimation infrastructure, estimate power consumption under various scenarios. You will be working with architecture, design, synthesis, timing, circuit, and post silicon teams to accomplish your tasks. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.” What You’ll Be Doing Architecture, development and correlation of power estimation models/tools for NVIDIA's chips Help architect and develop power models for use-cases, Idle power and IO power. Chip in to design the tools based on these models and their testing methodology/infrastructures Correlate and Calibrate the power models using measured silicon data Analyze and help decide the chip configuration and process technology options to optimize power/performance for Nvidia's upcoming chips Help study and contribute to Performance/Watt improvement ideas for Nvidia's GPUs and SOCs What We Need To See B.Tech./M.Tech and 1+ years of experience related to Power / Performance estimation and optimization techniques Strong fundamentals in power including transistor-level leakage/dynamic characteristics of VLSI circuits Familiarity with low power design techniques such as multi VT, Clock gating, Power gating, and Dynamic Voltage-Frequency Scaling (DVFS) Strong background in power estimation techniques, flows and algorithms Good programming skills - Python preferred. Good skills with object-oriented programming and design. Ways To Stand Out From The Crowd Exposure to lab setup including power measurement equipment such as scope/DAQ with ability to analyze board level power issues is a plus Exposure to power analysis EDA tools such as PTPX/EPS Good communication skills & desire to work as a great teammate With competitive salaries and a generous benefits package, Nvidia is widely considered to be one of the most desirable employers in the world. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. JR1997191

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day. Requirement Physical design Lead Engineer Will be responsible for Physical Design tasks at subsystem, sub-chip, and/or full-chip level. The tasks will include Synthesis, Floorplanning, Power planning, Placement, CTS and custom clocking, Routing, Static Timing analysis, Physical Verification, Formal Equivalency, IREM analysis. Expertise in FullChip tasks is added advantage. Should have leadership skills , leading team , handling flat projects. PnR tools (Innovus, ICC2) STA (Tempus, Primetime) 7+ years Expertise in: Physical design flow from RTL to GDSII Mandatory skills: Proficiency in TCL, Perl scripting M.Tech/B.Tech (Or) equivalent graduation Hyderabad We’re doing work that matters. Help us solve what others can’t.

Job Description Primary Duties & Responsibilities Architect, design, implement and test HDL modules for the payload following best practices such as efficiency, maintainability, and testability. Gather, define, and document requirements to meet existing and anticipated needs for payload systems. Develop, analyze, and review data to validate and verify the system meets specifications and design requirements. Implement real-time control algorithms and data processing routines to meet mission-critical performance requirements. Work closely with the software and hardware engineers to integrate and develop formal design verification and validation plans and perform or oversee testing. Maintain high-quality documentation of the entire design. Develop user manuals and troubleshooting guidelines for end-users. Ensure that the FPGA/RTL design meets industry standards. Work with cross-functional global teams with external stakeholders. Education & Experience Bachelors / master's degree in engineering. Minimum 5 years of experience in Firmware Development and FPGA development. Strong understanding of FPGA development tools, synthesis, simulation, and verification process. Experience with Intel-based SoCs, Quartus Prime, Modelsim, NIOS, etc. Proficient in FAGA designing and RTL(verilog) programming. Strong experience in the FPGA design process and writing device drivers in VHDL and or Verilog-embedded applications on FPGAs. Skills Experience with designing state machines and hardware interfacing with the understanding of high-speed communication interfaces (SPI, I2C, UART, and LVDS). Experience with software/firmware verification with test benches to verify design logic and generate high-quality documentation of the design and test results. Experience working in the hardware lab with knowledge of electronic equipment such as multimeters, function generators, oscilloscopes, logic analyzers, etc. Familiarity with digital signal processing (DSP) and high-speed data interfaces. Knowledge of how to optimize for memory/timing/power under resource constraints. Knowledge of understanding hardware design and SoC's specific schematics. Must be hard-working with good communication skills. Must be able to work both independently with minimal guidance, as well as part of a team. Be flexible and ability to excel in a cross-organizational, cross-cultural, global team environment. Good to have knowledge of c/c++/python/shell programming. Experience working on multiple stages of the product development lifecycle (project initiation, design completion, release, and maintenance with version control) Working Conditions Should be flexible to work outside of business hours. The work mode of Finisar India is Hybrid i.e. 3 days at office. Culture Commitment Ensure adherence to company’s values (ICARE) in all aspects of your position at Coherent Corp.: I ntegrity – Create an Environment of Trust C ollaboration – Innovate Through the Sharing of Ideas A ccountability – Own the Process and the Outcome R espect – Recognize the Value in Everyone E nthusiasm – Find a Sense of Purpose in Work Coherent Corp. is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law. Finisar India (Subsidiary of Coherent Corp) is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to gender identity, sexual orientation, race, color, religion, national origin, disability, or any other characteristic protected by law. About Us Coherent is a global leader in lasers, engineered materials and networking components. We are a vertically integrated manufacturing company that develops innovative products for diversified applications in the industrial, optical communications, military, life sciences, semiconductor equipment, and consumer markets. Coherent provides a comprehensive career development platform within an environment that challenges employees to perform at their best, while rewarding excellence and hard-work through a competitive compensation program. It's an exciting opportunity to work for a company that offers stability, longevity and growth. Come Join Us! Note to recruiters and employment agencies: We will not pay for unsolicited resumes from recruiters and employment agencies unless we have a signed agreement and have required assistance, in writing, for a specific opening. LinkedIn

We are excited to share a fantastic opportunity for the AI Lead/Sr. AI-ML Engineer position at Gritstone Technologies . We believe your skills and experience could be a perfect match for this role, and we would love for you to explore this opportunity with us. Design and implement scalable, high-performance AI/ML architectures with Python tailored for real-time and batch processing use cases. Lead the development of robust, end-to-end AI pipelines, including advanced data preprocessing, feature engineering, model development, and deployment. Define and drive the integration of AI solutions across cloud-native platforms (AWS, Azure, GCP) with optimized cost-performance trade-offs. Architect and deploy multimodal AI systems, leveraging advanced NLP (e.g., LLMs, OpenAI-based customizations, scanned invoice data extraction), computer vision (e.g., inpainting, super-resolution scaling, video-based avatar generation), and generative AI technologies (e.g., video and audio generation). Integrate domain-specific AI solutions, such as reinforcement learning, and self-supervised learning models. Implement distributed training and inferencing pipelines using state-of-the-art frameworks. Drive model optimization through quantization, pruning, sparsity techniques, and mixed-precision training to maximize performance across GPU hardware. Develop scalable solutions using large vision-language models (VLMs) and large language models (LLMs). Define and implement MLOps practices for version control, CI/CD pipelines, and automated model deployment using tools like Kubernetes, Docker, Kubeflow, and FastAPI. Enable seamless integration of databases (SQL Server, MongoDB, NoSQL) with AI workflows. Drive cutting-edge research in AI/ML, including advancements in RLHF, retrieval-augmented generation (RAG), and multimodal knowledge graphs. Experiment with emerging generative technologies, such as diffusion models for video generation and neural audio synthesis. Collaborate with cross-functional stakeholders to deliver AI-driven business solutions aligned with organizational goals. null 5+ years of Experience

Applications are invited for the Post of Junior Research Fellow ( JRF ) for the ANRF Funded Project in the Department of Physics, School of Advanced Sciences (SAS), at Vellore Institute of Technology (VIT), Vellore, T.N, India. Title of the Project : “Development of cost-efficient and scalable perovskite based colloidal nanoparticles for high performance plastic scintillators” Qualification : M.Sc./ M.Tech. in Physics/ Materials Science or related fields from recognized universities/institutes with a minimum of first class and with GATE / CSIR-UGC JRF / NET-LS qualification. Mandatory Skills : Candidates should have a strong research background in synthesis and characterization of nanomaterials. Experience with colloidal semiconductor nanomaterials and related photo physics is desirable. Stipend : Rs. 37,000 p.m. + 8% HRA for the first two years (JRF); Rs. 42,000 p.m.+ 8% HRA for the third year (SRF) will be as per Institute norms. No. of Vacancies : 01 Post (ONE) Age Limit (if any) : Not exceeding 30 years i.e. Age must be from 18 to 30 years Sponsoring Agency : ANRF, PMECRG program, New Delhi, India Duration : 36 Months Principal Investigator : Dr. Abhinav Anand, Assi stant Professor, Department of Physics School of Advanced Sciences, Vellore Institute of Technology (VIT) Vellore - 632 014, Tamil Nadu. Interested candidates with the above-mentioned qualifications can send your resume along with relevant documents pertaining to the details of qualifications, scientific accomplishments, experience (if any) and latest passport size photo etc. on or before ( 18/08/2025) through the website: http://careers.vit.ac.in No TA and DA will be paid for appearing the interview. Shortlisted candidates will be called for an interview at a later date which will be intimated by email. The selected candidate will be expected to join at the earliest.

Company Description We are a chemical research and manufacturing company based out of Saykha, Bharuch. We are into the fields of active pharmaceutical ingredient, agrochemical and related areas. Role Description This is a full-time on-site role for a Synthesis Chemist (R&D) at Pravishma Orgchem. The Synthesis Chemist will be responsible for conducting laboratory experiments, in-process quality control, utilizing analytical skills, and contributing to research and development projects on a day-to-day basis. Qualifications Laboratory Skills and Analytical Skills Research and Development (R&D) proficiency Strong research abilities Excellent problem-solving and critical thinking skills Ability to work effectively in a team environment Master's in Organic Chemistry or related field Job Type: Full-time Pay: ₹200,000.00 - ₹300,000.00 per year Benefits: Food provided Experience: total work: 2 years (Required) Work Location: In person Expected Start Date: 01/08/2025

Title: Executive - API R&D Date: Jul 25, 2025 Location: Tandalja - R&D Company: Sun Pharmaceutical Industries Ltd Role: To execute activities related to R&D Peptide Process Development & Scale-ups, along with a group comprising of Research Officers/ Research Assistants in co-ordination with Team/Group Leader Details of Previous Work Experience (Mandatory Requirement) Literature search and ROS (Route of Synthesis) finalization Basic knowledge of Orthogonal protected amino acid and Peptide Solid phase peptide Synthesis/Oligonucleodtide Synthesis Handling of hazardous chemical like Trifluoroacetic acid Knowledge of handling of analytical HPLC/Oligo Synthesis Purification using Preparative HPLC Preparative column packing and usage. Computer literacy etc. Knowledge of Phosphoramidalin /handling/storage Job Description: Literature search with respect to assigned project and finalizing the non-infringing synthetic route Experimentation (Process development, DoE study, optimization and validation). Purification of Peptide and knowledge of lyophilisation of pure solution. Handling of analytical HPLC and preparation of buffer. Characterisation of Peptide using HRMS,2D NMR, IR, Peptide mapping and sequencing. Preparation of Technology transfer documents. Scaling-up of process developed at R&D. Assisting to RA in filing DMF. General Laboratory Management etc.

Job Description Work together with system architects and micro architects to define high level specifications that are implementable. Contribute to RTL development including running tool flows like lint, CDC, Conformal low power and DFT checks Work closely with functional verification teams on test-plan development and debug. Understand timing constraints, run synthesis and deliver synthesized netlist to PD team and provide constraints support for PD teams. UPF writing, power aware equivalence checks and low power checks. Collaborate with other functional teams including DFT, physical design and emulation teams to achieve project milestones. Provide support to functional validation teams in post silicon debug. Qualifications MTech/BTech in EE/CS with hardware engineering experience of 1 to 15 years. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA Experience in Microcontroller and Microprocessor architecture, Interconnect, Cache Coherency. Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR/DDR3/4) and memory controllers. Strong domain knowledge of clocking, system modes, power management, debug, security and other architectures is a must. Any of following experience would be a plus: High Speed Peripherals like DDR, PCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; Flash memory subsystems. Experience with post-silicon bring-up and debug is a plus. Able to work with teams across the globe and possess good communication skills Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement . Job title Senior/Staff/Senior Staff/Principal - RTL Design Engineer Department Engineering Location Noida Remote No Requisition ID 20017793_2024-11-20

Job Description Collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Own end-to-end SOC RTL delivery while analysing and optimizing design for power, performance, and area (PPA) targets. Influence SoC definition, features, and adopt physical design friendly partitioning. Lead RTL design and integration of multi-subsystem SoCs , supporting complex architectures with multi-core, multi-power, and multi-reset domains . Demonstrate strong proficiency with front-end flows , including Lint, CDC, low-power (UPF) checks, synthesis, DFT , and Static Timing Analysis (STA) . Drive the development of robust Safety, Security, and Debug architectures for advanced SoCs with multiple interconnects. Design and integrate standard interface protocols such as AHB, AXI, CHI , and memory interfaces including ROM, RAM, Flash, LPDDR/DDR3/4 . Engage cross-functionally with DFT, physical design, verification, emulation, and validation teams to ensure first-time-right silicon and on-time project delivery. Support post-silicon debug, bring-up, and validation , working closely with lab and silicon validation teams. Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle. Mentor junior engineers, review their work, and provide technical leadership and guidance across multiple design projects. Provide overall leadership and tracking of the team’s goals. Contribute to the innovation quotient of the team via Desing Patents, Industry Standard Publications, AI-enabled design methodologies etc. Qualifications M.Tech/ B.Tech in Electrical Engineering or Computer Science with 12+ years of RTL design experience. Proven expertise in Verilog/SystemVerilog RTL design, integration, and microarchitecture. Strong understanding of SoC architecture, AMBA protocols (AXI, AHB, APB), clock/power domains, and memory subsystems. Experience with EDA tools for synthesis, lint, CDC, RDC, and timing analysis. Familiarity with UPF/low-power design, formal verification techniques, and static/dynamic checks. Excellent leadership, communication, and project management skills. Experience working with global cross-functional teams. Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement . Job title Principal Engineer,RTL Department Engineering Location Noida Remote No Requisition ID 20019236_2025-03-01

Job Description Summary This position is responsible for designing highly complex modules, critical components or a whole application/product in its entirety. Has the vision to integrate it across multiple systems. This position works independently and is seen as a technical leader. The position is responsible for driving the design and development efforts related to architecture, scalability, availability and performance in alignment with the product/application roadmap. Job Description Roles and Responsibilities In This Role, You Will Be responsible for providing technical leadership and defining, developing, and evolving software in a fast paced and agile development environment using the latest software development m and infrastructure Provide guidance to developers with either planning and execution and/or design architecture using agile methodologies such as SCRUM Work with Product Line Leaders (PLLs) to understand product requirements & vision Drive increased efficiency across the teams, eliminating duplication, leveraging product and technology reuse Capture system level requirements by brainstorming with CTO, Sr. Architects, Data Scientists, Businesses & Product Managers Leads impact assessment and decision related to technology choices, design /architectural considerations and implementation strategy. Subject matter expert in processes and methodologies with ability to adapt and improvise in various situations. Expert in navigating through ambiguity and prioritizing conflicting asks. Expert level skills in design, architecture and development, with an ability to take a deep dive in the implementation aspects if the situation demands. Leads the architecture and design efforts across the product / multiple product versions and is an expert in architecting custom solutions off the base product. Expert in core data structures as well as algorithms and has the ability to implement them using language of choice when necessary – as a value offering. Education Qualification Bachelor's Degree in Computer Science or “STEM” Majors (Science, Technology, Engineering and Math) with 12+ Years of Experience. Desired Characteristics Technical Expertise 12+ year's experience relevant to software development, validation, architecting in industry space. Hands on with application software development in both monolithic and microservice architecture. Basic knowledge of UI/UX tools and development process. Expertise in C# (.NET Core) for architecting robust and scalable applications. Expertise in microservices architecture and containerization technologies such as Docker, Kubernetes etc. comfortable in building microservices with distributed systems. Deep understanding of data architecture, Data Mesh etc. Strong knowledge of data platforms (e.g., Databricks, Redshift). Strong Proficient in multiple databases (RDBMS,NOSQL, TSDB, Columnar Database) Experience in Apache Arrow/Apache Calcite Experience in Database Design and Architecture Proficient in implementing and optimizing database interactions, ensuring efficient and scalable data processing. Proficient with performance optimizations, secure coding, multi-threading, caching Proficient in design principles, design patterns, and debugging techniques. Proficient with cluster deployments, load-balancing, HA, redundancy Proficient in NUnit framework for unit testing. Proficient in Message Queueing and Event Streaming platforms like Kafka, Rabbit MQ Proficient with the CI/CD tools Proficient with monitoring tools like Grafana and Prometheus Autonomous and able to work asynchronously (due to time zone difference) Job Requirements Facilitates and coaches software engineering team sessions on requirements estimation and alternative approaches to team sizing and estimation. Leads a community of practice around estimation to share best practices among teams Knowledgeable about developments in various contexts, businesses, and industries. Quantifies effectiveness of design choices by gathering data. Drives accountability and adoption. Publishes guidance and documentation to promote adoption of design. Proposes design solutions based on research and synthesis; creates general design principles that capture the vision and critical concerns for a program. Demonstrates mastery of the intricacies of interactions and dynamics in Agile teams. Demonstrates advanced understanding of Lean Six Sigma principles (e.g., Black belt certified). Guides new teams to adopt Agile, troubleshoots adoption efforts, and guide continuous improvement. Provides training on Lean / Agile. Drives elimination of inefficiencies in coding process. Teaches XP practices to others. Actively embraces new methods and practices that increase efficiency and effectiveness. Business Acumen Evaluates technology to drive features and roadmaps. Maps technology trends to internal vision. Differentiates buzzwords from value proposition. Embraces technology trends that drive excellence beyond traditional practices (e.g., Test automation in lieu of traditional QA practices). Balances value propositions for competing stakeholders. Recommends a well-researched recommendation of buy vs. build solution. Conveys the value proposition for the company by assessing financial risks and gains of decisions and return on investment (ROI). Manages the process of building and maintaining a successful alliance. Understands and successfully applies common analytical techniques, including ROI, SWOT, and Gap analyses. Able to clearly articulate the business drivers relevant to a given initiative. Leadership Influences through others; builds direct and "behind the scenes" support for ideas. Pre-emptively sees downstream consequences and effectively tailors influencing strategy to support a positive outcome. Uses experts or other third parties to influence. Able to verbalize what is behind decisions and downstream implications. Continuously reflecting on success and failures to improve performance and decision-making. Understands when change is needed. Participates in technical strategy planning. Proactively identifies and removes project obstacles or barriers on behalf of the team. Able to navigate accountability in a matrixed organization. Communicates and demonstrates a shared sense of purpose. Learns from failure. Personal Attributes Able to effectively direct and mentor others in critical thinking skills. Proactively engages with cross-functional teams to resolve issues and design solutions using critical thinking and analysis skills and best practices. Finds important patterns in seemingly unrelated information. Influences and energizes other toward the common vision and goal. Maintains excitement for a process and drives to new directions of meeting the goal even when odds and setbacks render one path impassable. Innovates and integrates new processes and/or technology to significantly add value to GE. Identifies how the cost of change weighs against the benefits and advises accordingly. Proactively learns new solutions and processes to address seemingly unanswerable problems. Note Note To comply with US immigration and other legal requirements, it is necessary to specify the minimum number of years' experience required for any role based within the USA. For roles outside of the USA, to ensure compliance with applicable legislation, the JDs should focus on the substantive level of experience required for the role and a minimum number of years should NOT be used. This Job Description is intended to provide a high level guide to the role. However, it is not intended to amend or otherwise restrict/expand the duties required from each individual employee as set out in their respective employment contract and/or as otherwise agreed between an employee and their manager. Additional Information Relocation Assistance Provided: Yes

Qualcomm India Private Limited is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world-class products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements. The position available is for a Principal Engineer/Manager, CAD tools & Methodology based in Noida. The ideal candidate will lead a 20+ CAD team in Noida, delivering tools/flows/methodologies to enable Qualcomm to build its most complex SoCs in cutting-edge process nodes. Responsibilities include managing all CAD functions in Noida, driving tools, flows, methodologies globally, leading the local EDA vendor eco-system, and serving as the interface to Qualcomm execution teams in Noida. Qualifications for this role include at least 15 years of experience in the development of tools/flows/methodologies in RTL, DV, synthesis, PnR, or Signoff. The candidate should have a proven record of driving new innovative tool/flow/methodology solutions and have experience managing a medium-sized team. A preferred educational background is a Masters in VLSI or Computer Science, with a minimum requirement of a Bachelors in Electronics/Electrical Engineering/Computer Science. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If accommodations are needed during the application/hiring process, individuals can reach out to disability-accommodations@qualcomm.com or call Qualcomm's toll-free number. The company expects its employees to abide by all applicable policies and procedures, including security and confidentiality requirements. Please note that Qualcomm's Careers Site is only for individuals seeking a job at Qualcomm, and unsolicited submissions from staffing and recruiting agencies will not be accepted. For more information about this role, interested individuals can contact Qualcomm Careers directly.,

Qualcomm India Private Limited is a company of inventors that unlocked 5G, leading to rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. In the Invention Age, inventive minds with diverse skills, backgrounds, and cultures are needed to turn 5G's potential into world-changing technologies and products. As part of the successful engineering team at Qualcomm, whose deliveries are present in billions of mobile, compute, and IoT products globally, you will play a crucial role. This position, based in Qualcomm's Bangalore office, focuses on Low Power controller IP cores and subsystem digital design for industry-leading Snapdragon SoCs in mobile, compute, IoT, and Automotive markets. Your responsibilities will include micro-architecture and RTL design for Cores/subsystems, working closely with various teams for design convergence, enabling SW teams to utilize HW blocks, qualifying designs using static tool checks, and reporting progress against expectations. Preferred qualifications for this role include 4 to 10 years of experience in digital front-end design, expertise in RTL coding in Verilog/SV/VHDL, familiarity with UPF and power domain crossing, experience in synthesis, logical equivalence checks, and netlist CLP, proficiency in various bus protocols, low power design methodology, formal verification, and post-Si debug. Additionally, expertise in scripting languages like Perl/TCL/Python, database management flows, and effective communication skills are desired. Minimum qualifications entail a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 4+ years of relevant experience, or a Master's degree with 3+ years of experience, or a PhD with 2+ years of experience. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. The company expects its employees to adhere to all applicable policies and procedures, including security and confidentiality requirements. Qualified applicants are encouraged to apply, and staffing/recruiting agencies are advised not to submit unsolicited profiles, applications, or resumes. For more information about this role, please contact Qualcomm Careers.,

You should be a PNR Lead with over 8 years of experience, based in Bangalore. Your role will involve handling Full chip PnR tasks such as timing, congestion, and CTS issues, with an understanding of IO ring, package support, and multi-voltage design. It is crucial to have a deep understanding of synthesis, place & route, CTS, timing convergence, IR/EM checks, and signoff DRC/LVS closure. Your responsibilities will include independently planning and executing all aspects of physical design, such as floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, and DFM. You must have experience participating in all design stages including floor planning, placement, CTS, routing, physical verification, and IREM. Furthermore, your expertise should cover timing closure methodologies, DRC, LVS, ERC, and PERC rule files for lower tech node layout verification. Experience in lower tech nodes (<7nm) is required, along with strong automation skills in PERL, TCL, and EDA tool-specific scripting. You should be capable of taking complete ownership of a Block/sub-system throughout the execution cycle and possess out-of-the-box thinking to meet tighter PPA requirements.,

As a Qualcomm Hardware Engineer, you will play a crucial role in the planning, design, optimization, verification, and testing of electronic systems. Your responsibilities will include working on various types of systems such as circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment, packaging, test systems, FPGA, and/or DSP systems to help in the development of cutting-edge products. You will be involved in the front-end implementation of MSIP designs, RTL development, validation for linting, clock-domain crossing, low power and DFT rules, and collaborating with the functional verification team on test-plan development and debug. Your role will also entail developing timing constraints, providing support for physical design team, UPF writing, power-aware equivalence checks, low power checks, DFT insertion, ATPG analysis, SoC integration support, and chip level pre/post-silicon debug. To be successful in this role, you should hold an MTech/BTech in EE/CS with at least 5 years of hardware engineering experience. You should have expertise in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks), synthesis, DFT, functional verification, and static timing analysis. Experience with post-silicon bring-up and debug will be an added advantage. Additionally, the ability to collaborate effectively with global teams and strong communication skills are essential for this role.,

Search by Keyword Search by Location Show More Options Loading... Location All Select How Often (in Days) To Receive An Alert: Create Alert Select How Often (in Days) To Receive An Alert: Apply Now » Apply Now Start applying with LinkedIn Please wait... Title: Executive - API R&D Date: Jul 25, 2025 Location: Tandalja - R&D Company: Sun Pharmaceutical Industries Ltd Role: To execute activities related to R&D Peptide Process Development & Scale-ups, along with a group comprising of Research Officers/ Research Assistants in co-ordination with Team/Group Leader Details Of Previous Work Experience (Mandatory Requirement) Literature search and ROS (Route of Synthesis) finalization Basic knowledge of Orthogonal protected amino acid and Peptide Solid phase peptide Synthesis/Oligonucleodtide Synthesis Handling of hazardous chemical like Trifluoroacetic acid Knowledge of handling of analytical HPLC/Oligo Synthesis Purification using Preparative HPLC Preparative column packing and usage. Computer literacy etc. Knowledge of Phosphoramidalin /handling/storage Job Description: Literature search with respect to assigned project and finalizing the non-infringing synthetic route Experimentation (Process development, DoE study, optimization and validation). Purification of Peptide and knowledge of lyophilisation of pure solution. Handling of analytical HPLC and preparation of buffer. Characterisation of Peptide using HRMS,2D NMR, IR, Peptide mapping and sequencing. Preparation of Technology transfer documents. Scaling-up of process developed at R&D. Assisting to RA in filing DMF. General Laboratory Management etc. Apply Now » Apply Now Start applying with LinkedIn Please wait...

LOCATION : Bangalore, India DEPARTMENT : Chemistry Solutions Office Location : Bangalore, Bangalore Years of experience : 0 to 0 Salary Range : INR to (Annual) Scope This role is responsible for executing chemical reactions to synthesize required quantities of molecules/compounds as per client specifications using efficient routes and techniques. Responsibilities Set-up and execute reactions for synthesis of target molecules/compounds: Understand the project requirements as specified by the client, the synthetic route. Understand and discuss the MSDS (Material Safety Data Sheet) with team members. Identify and mitigate any potential safety risks with the help of a supervisor. Plan and execute reactions with proper reagents and equipment (glassware, stirrers, vacuum pumps, etc.) maintaining specified conditions (temperature, pressure, etc.), with optimum usage and minimum wastage. Ensure parallel execution of multiple reactions. Monitor the reaction by observing progress using analytical techniques. Identify and execute appropriate workup and purification techniques to produce an intermediary/final compound of desired quality. Analyze analytical data, evaluate and interpret results from the synthesis and report. Meet productivity benchmarks on number of reactions/number of steps/number of compounds/quality/compound purity/project timelines. Ensure safety at work through enforcement of good laboratory practices: Follow safety and quality systems in the labs. Maintenance and usage of equipment/apparatus/instruments as per SOPs and general housekeeping norms. Maintain records, data integrity, and IP confidentiality: Document reactions executed, research findings/observations accurately in lab notebooks as per client requirements to ensure data integrity. Maintain strict IP confidentiality and adhere to all related policies. Prepare final reports as required. Ensure high morale and skill development of the team: Improve knowledge of organic chemistry (particularly synthesis)/analytical techniques, etc. through one-on-one discussions with supervisor/regular classroom training/project training/further education programs, etc. Functional/Technical Skills Knowledge of Chemistry & Execution Knowledge of Safety Protocols Knowledge of IP & Confidentiality and Data Integrity Ability to conduct cost-benefit analysis and optimum usage of resources Required Educational Qualification & Relevant Experience MSc (Organic/Medicinal Chemistry) with 1 - 5 years of relevant experience Additional Requirements Candidates with their research publications in leading journals would be preferred. Additional Responsibilities: Reporting Team Reporting Designation Reporting Department : Educational Qualifications Preferred Category: Field specialization: Degree: Academic score: Institution tier: Required Certification/s Required Training/s : Required Work Experience Industry: Role: Years of experience: Key Performance Indicators: Required Competencies: Required Knowledge: Required Skills: Required Abilities Physical: Other: Work Environment Details: Specific Requirements Travel: Vehicle: Work Permit: Other Details Pay Rate: Contract Types: Time Constraints: Compliance Related: Union Affiliation:

Location: Bangalore, India Department: Chemistry Solutions Office Location: Bangalore, Bangalore Years of Experience: 0 to 0 Salary Range: INR to (Annual) Scope This role is responsible for executing chemicals reactions to synthesize required quantities of molecules/compounds as per client specifications using efficient routes and techniques. Responsibilities Set-up and execute reactions for synthesis of target molecules/compounds: Understand the project requirements as specified by the client, the synthetic route Understand and discuss the MSDS (Material Safety Data Sheet) with team members Identify and mitigate any potential safety risk with the help of the supervisor Plan and execute reactions with proper reagents and equipment (glassware, stirrers, vacuum pumps, etc.) maintaining specified conditions (temperature, pressure, etc.), with optimum usage and minimum wastage Ensure parallel execution of multiple reactions Monitor the reaction by observing progress using analytical techniques Identify and execute appropriate workup and purification techniques to produce an intermediary/final compound of desired quality Analyze analytical data, evaluate and interpret results from the synthesis, and report Meet productivity benchmarks on the number of reactions/number of steps/number of compounds/quality/compounds purity/project timelines Ensure safety at work through enforcement of good laboratory practices: Follow safety and quality systems in the labs Maintenance and usage of equipment/apparatus/instruments as per SOPs and general housekeeping norms Maintain records, data integrity, and IP confidentiality: Document reactions executed, research findings/observations accurately in lab notebooks as per client requirements to ensure data integrity Maintain strict IP confidentiality and adhere to all related policies Prepare final reports as required Ensure high morale and skill development of the team: Improve knowledge of organic chemistry (particularly synthesis)/analytical techniques, etc. through one-on-one discussions with supervisor/regular classroom training/project training/further education programs, etc. Functional/Technical Skills Knowledge of Chemistry & Execution Knowledge of Safety Protocols Knowledge of IP & Confidentiality and Data Integrity Ability to conduct cost-benefit analysis and optimum usage of resources Required Educational Qualification & Relevant Experience MSc (Organic/Medicinal Chemistry) with 1-5 years of relevant experience Additional Requirements Candidates with their research publications in leading journals would be preferred Additional Responsibilities: Reporting Team Reporting Designation Reporting Department: Educational Qualifications Preferred Category: Field Specialization: Degree: Academic Score: Institution Tier: Required Certification/s Required Training/s: Required Work Experience Industry: Role: Years of Experience: Key Performance Indicators: Required Competencies: Required Knowledge: Required Skills: Required Abilities Physical: Other: Work Environment Details: Specific Requirements Travel: Vehicle: Work Permit: Other Details Pay Rate: Contract Types: Time Constraints: Compliance Related: Union Affiliation:

LOCATION: Bangalore, India DEPARTMENT: Chemistry Solutions Office Location: Bangalore Bangalore Years of Experience: 0 to 0 Salary Range: INR to (Annual) Scope This role is responsible for executing chemicals reactions to synthesize required quantities of molecules/compounds as per client specifications using efficient route and techniques. Responsibilities Set-up and execute reactions for synthesis of target molecules/compounds: Understand the project requirements as specified by the client, the synthetic route. Understand and discuss the MSDS (Material Safety Data Sheet) with team members. Identify and mitigate any potential safety risk with the help of supervisor. Plan and execute reactions with proper reagents and equipment (glassware, stirrers, vacuum pumps etc.) maintaining specified conditions (temperature, pressure etc.), with optimum usage and minimum wastage. Ensure parallel execution of multiple reactions. Monitor the reaction by observing progress by using analytical techniques. Identify and execute appropriate workup and purification technique to produce an intermediary/final compound of desired quality. Analyze analytical data, evaluate and interpret results from the synthesis and report. Meet productivity benchmarks on number of reactions/number of steps/number of compounds/quality/compounds purity/project timelines. Ensure safety at work through enforcement of good laboratory practices: Follow safety and quality systems in the labs. Maintenance and usage of equipment/apparatus/instruments as per SOPs and general housekeeping norms. Maintain records, data integrity and IP confidentiality: Document reactions executed, research findings/observations accurately in lab notebooks as per client requirements to ensure data integrity. Maintain strict IP confidentiality and adhere to all related policies. To prepare final reports as required. Ensure high morale and skill development of team: Improve knowledge of organic chemistry (particularly synthesis)/Analytical techniques etc. through one-on-one discussions with supervisor/regular classroom trainings/project trainings/further education programs etc. Functional/Technical Skills Knowledge of Chemistry & Execution Knowledge of Safety Protocols Knowledge of IP & Confidentiality and Data Integrity Ability to conduct cost-benefit analysis and optimum usage of resources Required Educational Qualification & Relevant Experience MSc (Organic/Medicinal Chemistry) with 1 - 5 years of relevant experience Additional Requirements Candidates with their research publications in leading journals would be preferred Additional Responsibilities: Reporting Team Reporting Designation: Reporting Department: Educational Qualifications Preferred Category: Field Specialization: Degree: Academic Score: Institution Tier: Required Certification/s: Required Training/s: Required Work Experience Industry: Role: Years of Experience: Key Performance Indicators: Required Competencies: Required Knowledge: Required Skills: Required Abilities Physical: Other: Work Environment Details: Specific Requirements Travel: Vehicle: Work Permit: Other Details Pay Rate: Contract Types: Time Constraints: Compliance Related: Union Affiliation:

LOCATION: Bangalore, India DEPARTMENT: Chemistry Solutions Office Location: Bangalore Years of Experience: 0 to 0 Salary Range: INR to (Annual) Scope This role is responsible for executing chemical reactions to synthesize required quantities of molecules/compounds as per client specifications using efficient routes and techniques. Responsibilities Set-up and execute reactions for synthesis of target molecules/compounds: Understand the project requirements as specified by the client, the synthetic route. Understand and discuss the MSDS (Material Safety Data Sheet) with team members. Identify and mitigate any potential safety risk with the help of a supervisor. Plan and execute reactions with proper reagents and equipment (glassware, stirrers, vacuum pumps, etc.) maintaining specified conditions (temperature, pressure, etc.), with optimum usage and minimum wastage. Ensure parallel execution of multiple reactions. Monitor the reaction by observing progress using analytical techniques. Identify and execute appropriate workup and purification technique to produce an intermediary/final compound of desired quality. Analyze analytical data, evaluate and interpret results from the synthesis, and report. Meet productivity benchmarks on number of reactions/number of steps/number of compounds/quality/compounds purity/project timelines. Ensure safety at work through enforcement of good laboratory practices: Follow safety and quality systems in the labs. Maintenance and usage of equipment/apparatus/instruments as per SOPs and general housekeeping norms. Maintain records, data integrity, and IP confidentiality: Document reactions executed, research findings/observations accurately in lab notebooks as per client requirements to ensure data integrity. Maintain strict IP confidentiality and adhere to all related policies. Prepare final reports as required. Ensure high morale and skill development of team: Improve knowledge of organic chemistry (particularly synthesis)/Analytical techniques, etc. through one-on-one discussions with supervisor/regular classroom trainings/project trainings/further education programs, etc. Functional/Technical Skills Knowledge of Chemistry & Execution Knowledge of Safety Protocols Knowledge of IP & Confidentiality and Data Integrity Ability to conduct cost-benefit analysis and optimum usage of resources Required Educational Qualification & Relevant Experience MSc (Organic/Medicinal Chemistry) with 1 - 5 years of relevant experience Additional Requirements Candidates with their research publications in leading journals would be preferred Additional Responsibilities Reporting Team Reporting Designation: Reporting Department: Educational Qualifications Preferred Category: Field specialization: Degree: Academic score: Institution tier: Required Certification/s: Required Training/s: Required Work Experience Industry: Role: Years of experience: Key Performance Indicators: Required Competencies: Required Knowledge: Required Skills: Required Abilities Physical: Other: Work Environment Details: Specific Requirements Travel: Vehicle: Work Permit: Other Details Pay Rate: Contract Types: Time Constraints: Compliance Related: Union Affiliation:

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience in Application-Specific Integrated Circuit (ASIC) development, with power optimization. Experience with low power schemes, power roll up, and power estimations. Experience in ASIC design verification, synthesis, timing analysis. Preferred qualifications: Experience with coding languages (e.g., Python or Perl). Experience in System on a Chip (SoC) designs and integration flows. Experience with power optimization and power modeling tools. Knowledge of high performance and low power design techniques. About The Job In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be part of a team developing Application-Specific Integrated Circuits (ASICs) used to accelerate machine learning computation in data centers. You will collaborate with members of architecture, verification, power and performance, physical design, etc. to specify and deliver quality designs for next generation data center accelerators. You will also solve problems with micro-architecture and practical reasoning solutions, and evaluate design options with performance, power and area in mind. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Responsibilities Participate in defining power management schemes and low power modes. Create power specifications and Unified Power Format (UPF) definition for System on a Chip (SoC) and subsystems. Estimate and track through all phases of the project. Run power optimization tools, suggest ways to improve power and drive convergence. Work with cross-functional teams for handoff of power intent and power projections. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

Role To execute activities related to R&D Peptide Process Development & Scale-ups, along with a group comprising of Research Officers/ Research Assistants in co-ordination with Team/Group Leader Details Of Previous Work Experience (Mandatory Requirement) Literature search and ROS (Route of Synthesis) finalization Basic knowledge of Orthogonal protected amino acid and Peptide Solid phase peptide Synthesis/Oligonucleodtide Synthesis Handling of hazardous chemical like Trifluoroacetic acid Knowledge of handling of analytical HPLC/Oligo Synthesis Purification using Preparative HPLC Preparative column packing and usage. Computer literacy etc. Knowledge of Phosphoramidalin /handling/storage Job Description Literature search with respect to assigned project and finalizing the non-infringing synthetic route Experimentation (Process development, DoE study, optimization and validation). Purification of Peptide and knowledge of lyophilisation of pure solution. Handling of analytical HPLC and preparation of buffer. Characterisation of Peptide using HRMS,2D NMR, IR, Peptide mapping and sequencing. Preparation of Technology transfer documents. Scaling-up of process developed at R&D. Assisting to RA in filing DMF. General Laboratory Management etc.

This Job is based in Australia The Opportunity The University of New South Wales (UNSW) Sydney, in partnership with ANSTO (Australia), Imperial College London (UK), and Tokamak Energy (UK), is launching a groundbreaking research program focused on developing new materials for compact tokamak reactors. We are recruiting a Postdoctoral Research Associate to join the team and contribute to this initiative. Working closely with materials modelling experts, you will have a primary role in planning experimental materials testing, characterisation, and subsequent design synthesis leading to improved materials performance. The role will give you access to cutting-edge facilities at UNSW and ANSTO, including the OPAL Research Reactor. International facilities will also provide opportunities for ion irradiation studies and in-situ testing. The broader goals of the research include the development of improved materials for modular and compact fusion reactors, fundamental insight into neutron and ion irradiation damage, and development of Australia’s capabilities and facilities for nuclear materials research. This is a highly collaborative role where you will work seamlessly with research groups at both UNSW and ANSTO, manage your time and responsibilities, and cultivate productive relationships at both locations with a wide range of stakeholders. This will be one of a potential six postdoc hires in the research group for 2025. At ANSTO, you will have the opportunity to work closely with both the Nuclear Materials Research and Technology Group and the Nuclear Analysis Section of Reactor Operations. At UNSW, you will become part of a vibrant materials research community within in the School of Mechanical and manufacturing Engineering, and the UNSW Nuclear Innovation Centre. This position is best suited for candidates with a strong background in materials characterisation, structural integrity, nuclear materials and/or radiation damage research. The role reports to Associate Professor Edward Obbard and has no direct reports. Salary (Level A) – AUD $110,059 to $117,718 per annum + 17% superannuation Full time Fixed-term contract – 3 years Location: Kensington – Sydney, Australia About Us UNSW isn’t like other places you’ve worked. Yes, we’re a large organisation with a diverse and talented community; a community doing extraordinary things. But what makes us different isn’t only what we do, it’s how we do it. Together, we are driven to be thoughtful, practical, and purposeful in all we do. If you want a career where you can thrive, be challenged, and do meaningful work, you’re in the right place. The School of Mechanical and Manufacturing Engineering that is internationally recognised for its excellence in research and teaching. Our mission is to nurture students to become industry leaders who will generate societal, economic, and environmental benefits. The School is one of the largest and most prestigious schools Australia for thriving research programs and contribution to education excellence in Aerospace, Mechanical Engineering, Advanced Manufacturing Engineering, Robotics and Mechatronic Engineering. Our Schools QS ranking for 2023 is #49 globally and the highest in Australia The ARWU (Shanghai) Rankings for 2023 ranked the subject Mechanical Engineering at #36 globally and the highest in Australia. Aerospace Engineering at UNSW was ranked #45 globally. For further information on our school go to - https://www.unsw.edu.au/engineering/our-schools/mechanical-and-manufacturing-engineering The UNSW Nuclear Innovation Centre is a pioneering hub dedicated to advancing Australia’s nuclear science industry. Launched in February 2024, the Centre fosters cross-disciplinary and cross-industry collaborations, focusing on areas such as medicine, irradiated materials, waste management, space exploration, and mining. By bringing together experts from various fields, the Centre aims to drive innovation, develop a skilled workforce, and nurture future leaders. Its mission is to enhance research, education, and training, ensuring the prosperity and competitiveness of Australia’s nuclear technology sector. For more information please visit - https://www.unsw.edu.au/research/nuclear-innovation-centre Skills & Experience A PhD in a related discipline, and/or relevant work experience. Experience in handling active materials or in planning and performing irradiation campaigns of materials with neutrons or charged particles. Proven experience in characterization of materials using a range of analytical techniques. Proven commitment to proactively keeping up to date with discipline knowledge and developments. Demonstrated ability to undertake high quality academic research and conduct independent research with limited supervision. Demonstrated track record of publications and conference presentations relative to opportunity. Demonstrated ability to work in a team, collaborate across disciplines and build effective relationships. Evidence of highly developed interpersonal skills. Demonstrated ability to communicate and interact with a diverse range of stakeholders and students. An understanding of and commitment to UNSW’s aims, objectives and values in action, together with relevant policies and guidelines. Knowledge of health and safety responsibilities and commitment to attending relevant health and safety training. Additional details about the specific responsibilities for this position can be found in the position description. This is available via JOBS@UNSW. To Apply: Please click the apply now button and submit your CV, Cover Letter and Responses to the Skills and Experience. You should systematically address the Skills and Experience listed within the position description in your application. Please note applications will not be accepted if sent to the contact listed below. Contact : Eugene Aves – Talent Acquisition Consultant E: eugene.aves@unsw.edu.au Applications close: 11:55 pm (Sydney time) on Tuesday 19 August 2025 UNSW is committed to evolving a culture that embraces equity and supports a diverse and inclusive community where everyone can participate fairly, in a safe and respectful environment. We welcome candidates from all backgrounds and encourage applications from people of diverse gender, sexual orientation, cultural and linguistic backgrounds, Aboriginal and Torres Strait Islander background, people with disability and those with caring and family responsibilities. UNSW provides workplace adjustments for people with disability, and access to flexible work options for eligible staff. The University reserves the right not to proceed with any appointment.