2205 Synthesis Jobs - Page 5

Role: Scientist - Peptide Chemistry. Qualification: M.Sc. Organic Chemistry with 2 to 6 years of experience on synthetic and analytical knowledge and experience of peptide molecules. Areas Of Responsibility Synthesis and Characterization of peptides Plan and execute the synthesis of peptide molecules with adequate purity and quantity as per project requirements. Develop good trouble shooting skills and comply with IPM and Safety norms. Developing appropriate methods for special functionalized peptides. Key intermediates are prepared through solution phase synthesis and used as building blocks for the synthesis of final target molecules. IN ORDER TO: successfully synthesize and deliver target compounds as per project specifications. Data Interpretation: To interpret the analytical data to identify the synthesized targets and key intermediates. IN ORDER TO: successfully characterize the synthesized targets. Safety Compliance To follow the lab safety and industrial hygiene practices.

Key Responsibilities Design and execute synthetic routes for the preparation of novel peptide-based compounds. Characterize and analyze synthesized peptides using state-of-the-art analytical techniques. Contribute to the design and optimization of peptide synthesis processes to improve efficiency and productivity. Work closely with cross-functional teams to understand project requirements and deliver on project goals. Keep abreast of the latest developments in peptide chemistry and bring innovative ideas to the table.

Key Responsibilities To work in peptide/ peptidomimetic purification and analysis. To purify complex peptides with purity as low as To work on PREP HPLC Purification of peptides and purification for Scale up activities. To maintain individual productivity that includes number of purifications and number of analysis. To maintain instruments like HPLC, MPLC, lyophilizer, peptide synthesizer, centrifuge etc. & comply with SHE/regulatory guidelines. To work in close collaboration with peptide synthesis team. To prepare regular updates (power point/excel). To maintain Lab note book is requires. Competencies Should have good communication & interpersonal relationships Ability to work with cross functional teams Should have positive attitude and problem-solving ability Should have good analytical skills.

Aurigene Pharmaceutical Services Limited is seeking a talented and motivated Scientist - Medicinal Chemistry - to join our growing team. In this role, you will play a key role in the discovery and development of novel drug candidates by designing, synthesizing, and characterizing target molecules. Responsibilities Synthesize novel target molecules according to client specifications, working independently and efficiently. Utilize your broad knowledge of modern organic chemistry and synthetic methods, including: Heterocyclic chemistry Metal-catalyzed reactions Handling air/moisture sensitive reagents Hydrogenations Multi-step synthesis Apply a wide range of techniques in synthesis and purification: Chromatographic methods (including expertise in MPLCs) Spectroscopic characterization of novel compounds (NMR, LCMS, HPLC, IR) Demonstrate problem-solving skills and the ability to think creatively to overcome synthetic challenges. Maintain laboratory notebooks and meticulously, adhering to client guidelines. Generate final reports and other scientific documents as required. Demonstrate a strong understanding of safety protocols and adhere to EHS guidelines as per our zero-tolerance policy. Key Skills And Competencies M.Sc. in Organic Chemistry with 2to 8 years of relevant experience. Strong knowledge of modern organic chemistry principles and synthetic methods. Expertise in various techniques for organic synthesis, purification, and characterization. Excellent problem-solving and critical thinking skills. Ability to work independently and as part of a team. Strong communication and interpersonal skills. Proficiency in scientific writing and record keeping.

Job Description: Experience: 4+ years of Experience Tapeout experience in block level PnR implementation including synthesis for medium to complex blocks o Good to have experience in TSMC/Intel lower technology node(16/14nm or below) o Experience in independently analyzing/resolving congestion, timing issues and basic understanding of clock tree build o Basic Timing understanding to independently analyze timing paths o Experience in ICC2/Innovus/DC tools, Fusion compiler being added advantage o Basic equivalency check understanding. Good to have Conformal LEC experience. o Should have understanding of basic shell scripting, tool based TCL scripting to automate redundant tasks

As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. This will involve working on a variety of components including yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to bring cutting-edge products to the market. Collaboration with cross-functional teams is a key aspect of this role to ensure that solutions meet performance requirements. The ideal candidate should have a minimum of 4 to 6 years of work experience in ASIC RTL Design. Experience in Logic design, micro-architecture, and RTL coding is essential. Hands-on experience with the design and integration of complex multi clock domain blocks is a must. Proficiency in Verilog/System-Verilog and knowledge of AMBA protocols such as AXI, AHB, APB, clocking/reset/debug architecture are also required. Candidates should have experience in Multi Clock designs and Asynchronous interface. Familiarity with ASIC development tools like Lint, CDC, Design compiler, and Primetime is necessary. An understanding of Automotive System Designs, Functional Safety, Memory controller designs, and microprocessors would be advantageous. The role involves close collaboration with Design verification and validation teams for pre/post Silicon debug. Prior experience in Low power design is preferred. Additionally, expertise in Synthesis and a solid grasp of timing concepts for ASIC are must-haves for this position.,

Qualcomm India Private Limited is looking for a Hardware Engineer to join their Engineering Group. As a Qualcomm Hardware Engineer, you will play a crucial role in planning, designing, optimizing, verifying, and testing electronic systems. Your responsibilities will include working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge, world-class products. Collaboration with cross-functional teams will be essential to meet performance requirements and develop innovative solutions. To be considered for this role, you should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 3 years of Hardware Engineering experience. Alternatively, a Master's degree with 2+ years of experience or a PhD with 1+ year of experience will also be considered. You should have 2-6 years of experience in Synthesis, Constraints, and interface timing Challenges, along with a strong domain knowledge in RTL Design, implementation, and Timing analysis. Experience with RTL coding using Verilog/VHDL/System Verilog, micro-architecture & designing cores and ASICs, and familiarity with Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc., will be highly beneficial. Exposure in scripting languages such as Pearl/Python/TCL and strong debugging capabilities are also required for this role. As a Qualcomm Hardware Engineer, you will collaborate closely with cross-functional teams to research, design, and implement performance, constraints, and power management strategies for the product roadmap. Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. If you require an accommodation during the application/hiring process, you can reach out to disability-accommodations@qualcomm.com. The company expects its employees to adhere to all applicable policies and procedures, including those related to the protection of confidential information. If you are a proactive team player with the ability to independently debug and solve issues, and meet the qualifications mentioned above, we encourage you to apply for this exciting opportunity at Qualcomm India Private Limited.,

Eximietas is currently seeking Senior Physical Design Leads/Architects with at least 10+ years of experience to join their team in Visakhapatnam. Immediate joiners or those with a short notice period are preferred for this role. Qualifications: - A minimum of 10+ years of experience in Physical Design using mainstream P&R tools. - A Bachelor's or Master's Degree in Electronics, Electrical, Telecom, or VLSI Engineering. In this role, you will: - Work on designs using advanced nodes such as 10nm/7nm/5nm or lower, collaborating with various customers to meet performance, area, and power targets. - Develop flow and methodology for placement, clock-tree synthesis, and routing. - Provide training and technical support to customers. Key Technical and Professional Requirements: - Proficiency in place & route flow, including placement guidelines, clock-tree synthesis, routing, and timing optimizations. - Experience in hierarchical designs and Low Power implementation is advantageous. - Familiarity with Synthesis, collaborating with RTL and implementation designers for improved results. - Knowledge of Floor Plan design, encompassing placement of hard macros, padring, power grid, and custom analog routes. - Experience in Static Timing Analysis tasks such as constraints development, parasitic extractions, and sign-off requirements. - Understanding of Physical Verification processes including DRC, LVS, DFM, and chip finishing. If you are interested in this opportunity, please share your resume with maruthiprasad.e@eximietas.design. We look forward to receiving your applications!,

Position: Lead - NITI for States Employment type: 1 year contract with open to extension Location: Delhi Business Unit: Foundations Language preference: English and Hindi About Sattva We Partner to deliver social impact at scale Sattva Consulting is a global impact consulting firm from India. Since 2009 we have been engaging with communities, business and government to achieve societal impact at scale. We believe that Civil society, Business and Government all have a critical role to play in building an equitable and sustainable world, and we actively partner with all stakeholders to enable impact through our advisory & orchestration services, knowledge and data platforms which we have built as public goods for the ecosystem and collaborative solutions and partnerships. Our teams are based in India, Singapore, Denmark and UK, but as a global organization our work has spanned 25 countries and 5 continents. For more information, please visit: www.sattva.co.in About The Team The Foundations team partners with a diverse network of global and domestic philanthropic organisations to inform, influence, and drive collective action towards better social outcomes. We focus on catalysing ecosystem-level transformation by deeply understanding challenges, designing strategic and actionable solutions, and ensuring inclusive stakeholder engagement that balances diverse interests. The Opportunity This opportunity entails leading Sattva’s engagement with NITI Aayog to shape and scale the NITI for States digital platform - an initiative to empower state-level policymakers with actionable data, sectoral insights, and contextual tools to drive effective governance and development outcomes across India. As the Lead for this engagement, you will drive high quality strategic alignment with senior stakeholders across central and state ministries, ensuring the platform’s relevance, adoption, and long-term impact. This role requires strong advisory and research-driven capabilities, leveraging deep sectoral expertise, evidence-based analysis, and policy insight to shape the platform’s governance and strategic evolution. In addition to anchoring strategic stakeholder engagement, you will also collaborate closely with internal teams across content, data, technology, and outreach tracks to drive a user-centric, scalable, and impactful digital experience for public sector decision-makers. This role will require you to work out of the client office 5 days a week. Roles and Responsibilities Government Engagement Build and manage trusted relationships with key government and non-government stakeholders. Facilitate multi-stakeholder consultations, co-creation workshops, and review forums to gather insights, drive alignment, and encourage shared ownership. Represent Sattva in strategic forums with policymakers, driving thought leadership on data-driven governance and state capability development. Navigate complex government structures and political contexts to enable adoption and integration of the platform at the central and state level. Sectoral Research & Insight Generation Anchor in-depth research and knowledge generation across primary development sectors (e.g., health, education, livelihoods, skilling, etc.) to inform platform content and strategic direction. Enable meaningful synthesis of evidence from diverse sources into actionable insights tailored for central and state-level decision-makers Support in identifying use cases where data driven decision making can be enabled at different levels of the government using public and credible private sector data Work with the governments to drive effective use of Data and AI in changing last mile behaviours in usage of data Stay abreast of key trends in public policy, digital transformation, and sectoral innovations to inform content quality and platform’s evolution Platform Governance & Evolution Work with product, content, and data teams to co-create a platform roadmap that is user-centric, impactful, and scalable. Manage the command center to continuously monitor platform adoption; Gauge and analyse user experience and feedback on an ongoing basis to guide iterative improvements. Program & Team Leadership Anchor project planning, timelines, deliverables, financials and quality assurance to ensure desired outcomes are achieved Manage a multidisciplinary team comprising policy researchers, data analysts, consultants, and product specialists to ensure timely and high-quality delivery. Drive cross-functional collaboration between internal teams and government partners. Build a high-performance culture anchored in ownership, learning, and innovation; Facilitate internal learning, capacity building, and performance management within the team Key Qualifications And Experiences We are looking for individuals who align with Sattva’s mission of alleviating poverty in our lifetime and have the following skill sets, experiences and qualifications: 16+ years of experience in government advisory, digital governance & transformation, consulting, finance, research, or development sector leadership. Master’s degree in Economics, Data Sciences, Statistics or a related field. Additional certifications or executive programs in public policy, public administration, digital transformation, or data for development are a plus. Proven experience of working on research and data across diverse sectors. Proven experience of analysing public data and working with government data systems. Experience in digital product development or digital public infrastructure initiatives is highly desirable. Demonstrated experience in primary development sectors such as education, health, livelihoods, etc., is highly desirable. Proven experience working with or advising senior government stakeholders at the central and/or state level. Proven track record of managing complex programs including strategy, execution, stakeholder management, and team leadership. Outstanding communication skills in English and Hindi, with an ability to present complex ideas clearly and persuasively to diverse audiences. Why Sattva? It's not about us really- Because IMPACT is everybody’s business. Create Impact: Make an impact with the work you do and solutions you design Work Environment: Thrive in a diverse, inclusive and collaborative environment Learn & Grow: Challenge yourself to learn, grow and deliver the best you can Future Ready: Work on critical issues of today that will affect our collective tomorrow How to Prepare? This is your opportunity to showcase not only your qualifications but also your unique personality and passion for making a meaningful impact. Approach your application with intentionality, ensuring that each word reflects your commitment to excellence and aligns seamlessly with the values of Sattva. Sattva is an equal opportunity employer and considers qualified applicants regardless of race, religion, caste, creed, gender, sexual orientation, physical or mental disability, or any other legally protected and/or marginalized characteristics. Diversity, Equity, and Inclusion are essential to our business and we foster an environment of respect and a culture that celebrates diversity and promotes equity and inclusion. We are committed to providing all employees with education, training, and development opportunities to create a workplace where everyone feels safe, respected, and included.

You are invited to apply for the position of "ASIC RTL Engineer" at Semi Leaf consulting Service located in Bangalore. With 3-8 years of experience, if you are available to join within 30 days and prefer working in a WFO mode, this opportunity might be just for you. As an ASIC RTL Engineer at Semi Leaf, your responsibilities will include working on ASIC RTL design, RTL Logic Synthesis, LEC, Conformal, ECO, FC Check, and having proficiency in either TCL or Python. You must have Synthesis or Implementation experience, familiarity with the Linux environment, excellent communication skills, and experience with at least one serial protocol like UART, I2C, SPI. Skills with SOC Architecture, experience in CDC and Lint, and working on Cortex-M4 core/Sub-system verification/execution environment bring-up are desirable. Additionally, you should be able to develop verification infrastructure for Cortex-M4 Core/Sub-system bring-up, have knowledge of Coresight/Functional Debug architecture, and expertise in UVM/SV knowledge to develop scoreboard/checkers. If you are interested in this opportunity and possess the required experience, kindly share your updated resume with vagdevi@semi-leaf.com. Referrals are also highly appreciated. Join us at Semi Leaf consulting Service and be part of a team of experts dedicated to finding candidates with specialized skills in Semiconductor/VLSI/EDA & Embedded domains.,

Position: Lead - NITI for States Employment type: 1 year contract with open to extension Location: Delhi Business Unit: Foundations Language preference: English and Hindi About Sattva We Partner to deliver social impact at scale Sattva Consulting is a global impact consulting firm from India. Since 2009 we have been engaging with communities, business and government to achieve societal impact at scale. We believe that Civil society, Business and Government all have a critical role to play in building an equitable and sustainable world, and we actively partner with all stakeholders to enable impact through our advisory & orchestration services, knowledge and data platforms which we have built as public goods for the ecosystem and collaborative solutions and partnerships. Our teams are based in India, Singapore, Denmark and UK, but as a global organization our work has spanned 25 countries and 5 continents. For more information, please visit: www.sattva.co.in About The Team The Foundations team partners with a diverse network of global and domestic philanthropic organisations to inform, influence, and drive collective action towards better social outcomes. We focus on catalysing ecosystem-level transformation by deeply understanding challenges, designing strategic and actionable solutions, and ensuring inclusive stakeholder engagement that balances diverse interests. The Opportunity This opportunity entails leading Sattva’s engagement with NITI Aayog to shape and scale the NITI for States digital platform - an initiative to empower state-level policymakers with actionable data, sectoral insights, and contextual tools to drive effective governance and development outcomes across India. As the Lead for this engagement, you will drive high quality strategic alignment with senior stakeholders across central and state ministries, ensuring the platform’s relevance, adoption, and long-term impact. This role requires strong advisory and research-driven capabilities, leveraging deep sectoral expertise, evidence-based analysis, and policy insight to shape the platform’s governance and strategic evolution. In addition to anchoring strategic stakeholder engagement, you will also collaborate closely with internal teams across content, data, technology, and outreach tracks to drive a user-centric, scalable, and impactful digital experience for public sector decision-makers. This role will require you to work out of the client office 5 days a week. Roles and Responsibilities Government Engagement Build and manage trusted relationships with key government and non-government stakeholders. Facilitate multi-stakeholder consultations, co-creation workshops, and review forums to gather insights, drive alignment, and encourage shared ownership. Represent Sattva in strategic forums with policymakers, driving thought leadership on data-driven governance and state capability development. Navigate complex government structures and political contexts to enable adoption and integration of the platform at the central and state level. Sectoral Research & Insight Generation Anchor in-depth research and knowledge generation across primary development sectors (e.g., health, education, livelihoods, skilling, etc.) to inform platform content and strategic direction. Enable meaningful synthesis of evidence from diverse sources into actionable insights tailored for central and state-level decision-makers Support in identifying use cases where data driven decision making can be enabled at different levels of the government using public and credible private sector data Work with the governments to drive effective use of Data and AI in changing last mile behaviours in usage of data Stay abreast of key trends in public policy, digital transformation, and sectoral innovations to inform content quality and platform’s evolution Platform Governance & Evolution Work with product, content, and data teams to co-create a platform roadmap that is user-centric, impactful, and scalable. Manage the command center to continuously monitor platform adoption; Gauge and analyse user experience and feedback on an ongoing basis to guide iterative improvements. Program & Team Leadership Anchor project planning, timelines, deliverables, financials and quality assurance to ensure desired outcomes are achieved Manage a multidisciplinary team comprising policy researchers, data analysts, consultants, and product specialists to ensure timely and high-quality delivery. Drive cross-functional collaboration between internal teams and government partners. Build a high-performance culture anchored in ownership, learning, and innovation; Facilitate internal learning, capacity building, and performance management within the team Key Qualifications And Experiences We are looking for individuals who align with Sattva’s mission of alleviating poverty in our lifetime and have the following skill sets, experiences and qualifications: 16+ years of experience in government advisory, digital governance & transformation, consulting, finance, research, or development sector leadership. Master’s degree in Economics, Data Sciences, Statistics or a related field. Additional certifications or executive programs in public policy, public administration, digital transformation, or data for development are a plus. Proven experience of working on research and data across diverse sectors. Proven experience of analysing public data and working with government data systems. Experience in digital product development or digital public infrastructure initiatives is highly desirable. Demonstrated experience in primary development sectors such as education, health, livelihoods, etc., is highly desirable. Proven experience working with or advising senior government stakeholders at the central and/or state level. Proven track record of managing complex programs including strategy, execution, stakeholder management, and team leadership. Outstanding communication skills in English and Hindi, with an ability to present complex ideas clearly and persuasively to diverse audiences. Why Sattva? It's not about us really- Because IMPACT is everybody’s business. Create Impact: Make an impact with the work you do and solutions you design Work Environment: Thrive in a diverse, inclusive and collaborative environment Learn & Grow: Challenge yourself to learn, grow and deliver the best you can Future Ready: Work on critical issues of today that will affect our collective tomorrow How to Prepare? This is your opportunity to showcase not only your qualifications but also your unique personality and passion for making a meaningful impact. Approach your application with intentionality, ensuring that each word reflects your commitment to excellence and aligns seamlessly with the values of Sattva. Sattva is an equal opportunity employer and considers qualified applicants regardless of race, religion, caste, creed, gender, sexual orientation, physical or mental disability, or any other legally protected and/or marginalized characteristics. Diversity, Equity, and Inclusion are essential to our business and we foster an environment of respect and a culture that celebrates diversity and promotes equity and inclusion. We are committed to providing all employees with education, training, and development opportunities to create a workplace where everyone feels safe, respected, and included.

You are a highly experienced RTL Design Engineer with 12-20 years of experience, specializing in PCIe IP development. Based in Noida/Bangalore, you will be responsible for designing and supporting the RTL of Cadence's PCIe IP solution. Your role will involve working with existing RTL, adding new features, ensuring customer configurations are clean, supporting customers, and ensuring design compliance with LINT and CDC guidelines. To qualify for this position, you must hold a BE/BTech/ME/MTech degree in Electrical/Electronics/VLSI and have extensive experience as a design and verification engineer, with a focus on RTL design using Verilog. Additionally, you should have experience with System Verilog, UVM-based environments, AXI3/4/5, and preferably PCIe. Previous experience in RTL design of complex protocols and IP development teams is highly advantageous. As a member of the Cadence High-Speed SerDes PHY IP Front end Design team, you will be responsible for defining microarchitecture, leading ASIC design, collaborating with cross-functional teams, mentoring junior members, and fostering a high-performance team culture. Requirements for this role include a Bachelor's degree in Electronics Engineering with at least 7 years of experience, a Master's degree with 5 years, or a Ph.D. with 2 years in Digital Design. You should have hands-on experience in micro-architecting digital blocks, RTL implementation in Verilog/SV, SDC definition, STA, Lint Checks, CDC, and Synthesis. Knowledge of protocols such as Ethernet, USB, PCIe, MIPI(DPHY), and HDMI/Display is desired, along with the ability to work closely with Analog design teams and develop high-speed critical digital circuits and signal processing blocks.,

The Opportunity We&aposre looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrows future by accelerating the critical data communication at the heart of our digital world from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. Alphawave Semi is expanding its team in PCIe IP design and development! We are looking for talented RTL Design Engineers to contribute to enhance and develop our IP. This is an incredible opportunity to be part of the PCIe and CXL development cycle, from specification to design. As an RTL Design Engineer, you will work in IP design and integration. You will be responsible for microarchitecture, RTL coding, create microarchitecture documents, Lint and Synthesis cycle and Timing closure. You will work with verification team on achieving test plan, the code & functional coverage. What You&aposll Do Deliver standards-compliant PCIe IP block. Will work on Micro-architect and document the design. Develop RTL design using Verilog and/or System Verilog. Work closely with the verification team in reviewing test suite/plans. Issue and track bug reports from launch to closure. Will refine IP development process with advancing tools/scripting. Work with our external customers or internal engineers to deliver designs for use. Collaborate with the team. You will be reporting to Principal Engineer of the Design team. What You&aposll Need B.E/M.Tech with 8+ years of experience in IP, ASIC or FPGA development. Knowledge and experience in any serial protocols and AMBA (AHB, AXI and CXS) protocol. Experience working on PCIe/CXL protocol is advantageous. Solid experience with Verilog, and System Verilog. Experience with FPGA development cycle is desirable. Experience with Lint, CDC, Synthesis, Timing closure, FPGA validation, Power analysis and LEC tools. Experience in ASIC tape-outs is a plus. Good experience with debugging tools and solid debugging skills. Experience with Unix/Linux Shell scripting and/or Perl, TCL, Python and C/C++ programming. Strong communication skills. "We have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process. Show more Show less

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . We are seeking a Senior Digital Design Engineer with deep expertise in high-performance controller and bridge design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solutions. Key Responsibilities Design and implement high-performance digital solutions, including RTL development and synthesis. Collaborate with cross-functional teams on IP integration for processor IPS and peripherals Deep knowledge of processor boot process and peripheral implementation with boot firmware in mind Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ? 16nm. Ensure timing closure, assess verification completeness, and oversee pre- and post-silicon debug. Utilize tools from Synopsys/Cadence and apply expertise in UVM-based verification flows Basic Qualifications Bachelor&aposs in Electronics /Electrical Engineering (Master&aposs preferred). 5+ years of digital design experience, with 3+ years focused on processor, peripherals and full chip implementation. Proven expertise in RTL development, synthesis, and timing closure. Experience with front-end design, gate-level simulations, and design verification. Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude. Required Expertise Hands-on experience with processor IP (ARM/ARC) Hands-on pre-silicon and post-silicon implementing peripherals for I2C/SPI/UART Strong proficiency in System Verilog/Verilog and scripting (Python/Perl). Silicon bring-up and post-silicon debug experience. Familiarity with Synopsys/Cadence tools and UVM-based design verification. Preferred Experience Hands-on experience with complex DMA engines and FW interaction Knowledge of system-level design with ARM/ARC/RISC-V processors sub systems Experience with block-level and full-chip design at advanced nodes (? 16nm). Understanding of PAD design, DFT, and floor planning. Experience with NIC, switch, or storage product development. Familiarity with working in design and verification workflows in a CI/CD environment. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities. Show more Show less

About BNP Paribas India Solutions Established in 2005, BNP Paribas India Solutions is a wholly owned subsidiary of BNP Paribas SA, European Union’s leading bank with an international reach. With delivery centers located in Bengaluru, Chennai and Mumbai, we are a 24x7 global delivery center. India Solutions services three business lines: Corporate and Institutional Banking, Investment Solutions and Retail Banking for BNP Paribas across the Group. Driving innovation and growth, we are harnessing the potential of over 10000 employees, to provide support and develop best-in-class solutions. About BNP Paribas Group BNP Paribas is the European Union’s leading bank and key player in international banking. It operates in 65 countries and has nearly 185,000 employees, including more than 145,000 in Europe. The Group has key positions in its three main fields of activity: Commercial, Personal Banking & Services for the Group’s commercial & personal banking and several specialised businesses including BNP Paribas Personal Finance and Arval; Investment & Protection Services for savings, investment, and protection solutions; and Corporate & Institutional Banking, focused on corporate and institutional clients. Based on its strong diversified and integrated model, the Group helps all its clients (individuals, community associations, entrepreneurs, SMEs, corporates and institutional clients) to realize their projects through solutions spanning financing, investment, savings and protection insurance. In Europe, BNP Paribas has four domestic markets: Belgium, France, Italy, and Luxembourg. The Group is rolling out its integrated commercial & personal banking model across several Mediterranean countries, Turkey, and Eastern Europe. As a key player in international banking, the Group has leading platforms and business lines in Europe, a strong presence in the Americas as well as a solid and fast-growing business in Asia-Pacific. BNP Paribas has implemented a Corporate Social Responsibility approach in all its activities, enabling it to contribute to the construction of a sustainable future, while ensuring the Group's performance and stability Commitment to Diversity and Inclusion At BNP Paribas, we passionately embrace diversity and are committed to fostering an inclusive workplace where all employees are valued, respected and can bring their authentic selves to work. We prohibit Discrimination and Harassment of any kind and our policies promote equal employment opportunity for all employees and applicants, irrespective of, but not limited to their gender, gender identity, sex, sexual orientation, ethnicity, race, colour, national origin, age, religion, social status, mental or physical disabilities, veteran status etc. As a global Bank, we truly believe that inclusion and diversity of our teams is key to our success in serving our clients and the communities we operate in. About Business Line/Function BNP Paribas IT teams are providing infrastructure, development and production support services to all applications used worldwide by all business lines. There is a great variety of technologies and infrastructures from legacy systems to cutting edge Cloud technologies. Within BNP Paribas Group IT, the filiere “FORTIS” oversees operationally to the challenges of IT applications with an end-to-end vision and consistently across the Bank. Several domains of these filiere contribute to this, including the domain “Service Offering DevOps”, which provides the DevSecOps platform for IT Group, Control Center, DB Activities and move to Cloud project. BNP Paribas Fortis is a bank that is responsible and socially committed. The environment, diversity, cultural support, sponsorship... Through various and concrete ways, we are dedicated to meeting our customers’ expectations and proud to demonstrate our values: responsible, human, innovative and enthusiastic Job Title MQ system administrator Date Department: ITGP Location: Chennai Business Line / Function BNPP Fortis Reports To (Direct) NA Grade (if applicable) (Functional) Number Of Direct Reports Directorship / Registration: NA Position Purpose Provide a brief description of the overall purpose of the position, why this position exists and how it will contribute in achieving the team’s goal. In the Agile Production Services at BNPP Fortis, the message based system engineer is in charge of putting in place, operating and maintaining the MQ infrastructure of the Bank. Responsibilities Direct Responsibilities Set up and configure MQ Series components in the cloud Administration of the existing infra (queues managers) Prepare, document, plan, organizes, execute, and validate changes Follow-up incidents and participate to root cause analysis Analyze possibilities to automates activities, propose solutions and implement it Security Management Contributing Responsibilities Technical & Behavioral Competencies Broad knowledge of IBM MQ (v9). Platform is running on Mainframe, AIX, Windows, Linux. Knowledge of the mainframe Cloud (Iaas, Paas) Knowledge of MQ server and client setup and management. Knowledge and experience of automation and scripting in MQ environments Knowledge of MQ on Mainframe Agile environment. Follows the Customer processes for projects, incident and change management. Being standalone and team worker, analytical minded, meet commitment, ability to work in a dynamic and multi-cultural environment, flexible, customer-oriented, understand risk awareness. Motivated self-starter, process-oriented with high attention to detail Quick self-starter, pro-active attitude. Good communication skills, Good analytical and synthesis skills. Autonomy, commitment, and perseverance. Ability to work in a dynamic and multicultural environment. Flexibility (in peak periods extra efforts may be required). Open minded and show flexibility in self-learning new technologies/tools. You are customer minded and can translate technical issues into non-technical explanations You are always conscious about continuity of services. You have a very good team spirit and share your knowledge and experience with other members of the team. Working in collaboration with team. Client-oriented, analytical, initiative oriented and able to work independently. Be flexible and ready to provide support outside of Business hours (on-call). Able to take additional responsibility. Able to work from base location Chennai/Mumbai (Whichever is your base location) during hybrid model Skills Referential Specific Qualifications (if required) Behavioural Skills: (Please select up to 4 skills) Ability to collaborate / Teamwork Personal Impact / Ability to influence Organizational skills Ability to deliver / Results driven Transversal Skills: (Please select up to 5 skills) Ability to understand, explain and support change Analytical Ability Ability to develop and adapt a process Ability To Develop Others & Improve Their Skills Choose an item. Education Level Bachelor Degree or equivalent Experience Level At least 7 years

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Job Overview: This position centers on floor-planning expertise at both block and top levels for industry-leading CPU core designs, with a strong emphasis on scalability and achieving aggressive Power, Performance, and Area (PPA) targets. The role involves working on cutting-edge technology nodes and applying advanced physical design techniques to push the boundaries of CPU performance and efficiency. Preferred Qualifications: Masters degree in Electrical/Computer Engineering 8+ years of direct top level floor-planning large and high frequency IP experience In depth end to end experience from RTL2GDS, taping out at least 5 complex designs Direct hands-on experience with bus/pin/repeater planning for entire IP Key responsibilities include: Driving floorplan architecture and optimization in collaboration with PD/RTL teams to maximize PPA Engaging in cross-functional collaboration with Physical design, timing, power, and packaging teams to ensure holistic design convergence Partnering with EDA tool vendors and internal CAD teams to develop and enhance automation flows and methodologies for improved design efficiency Making strategic trade-offs in design decisions to achieve optimal PPA outcomes while maintaining schedule and quality targets End to End Physical verification closure for subsystem. The ideal candidate will have/demonstrate the following: Experience in Physical design which includes floor-planning, placement, clock implementation, routing for complex, big and high speed designs Experience with physical synthesis and implementation tools - Cadence Innovus/Genus and Synopsys Fusion Compiler. Must have good knowledge of static timing analysis, reliability, and power analysis Strong understanding of CMOS circuit design and design techniques to push Power, Performance and Area of complex designs Ability to think outside the box for innovative solutions to improve power and eliminate performance bottlenecks Strong understanding of CPU micro-architecture and collaborate with RTL designers to improve bottlenecks for power and performance Solid working knowledge of scripting skills including tcl, perl or python Excellent communication skills and collaborating in a team environment is a must Excellent understanding of Physical Verification flow with in-depth experience in analyzing and debugging DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck issues. (Mostly Working on Calibre tool) Experience in IO, Bump planning and RDL routing Strategy. Preferred Skills: Clock implementation, power delivery network design choices, process technology, prior experience in flow and methodology development, block closure Close interaction with design and architecture teams to influence scalable floor-plans and optimal bus/pin/repeater planning for entire IP and its sub-blocks Hands on experience with Synthesis, DFT, Place and Route, Timing and Reliability Signoff Hands on experience working with very complex designs that push the envelope of Power, Performance and Area Hands on experience working with sub-micron technology process nodes eg. 5nm, 4nm and below is highly advantageous Hands on experience on Innovus/FC tool based scripting & python/TCL scripting. Prior experience in flow and methodology development is an advantage Excellent debug and analytical skills and demonstrated successes in floor-planning large IP and high frequency designs Ability to drive Physical Implementation teams in Floor-planning and work well in a collaborative environment with multi-disciplined teams Minimum Qualifications: Bachelors degree in Electrical/Computer Engineering 8+ years of direct top level floor-planning large and high frequency IP experience which includes bus/pin/repeater planning at the top level Strong background in VLSI design, physical implementation and scripting Strong background and experience working with industry standard Synthesis and Place and Route tools including Signoff tools Hands on experience taping out designs in sub-micron technology node design Expect strong self-motivation and time management skills Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail or call Qualcomm's toll-free number found . Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact .

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. About The Role As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Additional About The Role Additional About The Role Job Role * Work with multiple SOC Design teams to rollout robust Logic Synthesis, UPF synthesis, QoR optimization and netlist Signoff flows* Provide implementation flows support and issue debugging services to SOC design teams across various site* Develop and maintain 3rd party tool integration and product enhancement routines * Should lead implementation flow development effort independently by working closely with design team and EDA vendors * Should drive new tool evaluation, methodology refinement for PPA optimization Skill Set * Proficiency in Python/Tcl * Familiar with Synthesis tools (Fusion Compiler/Genus), * Fair knowledge in LEC, LP signoff tools* Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking* Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus* Should be sincere, dedicated and willing to take up new challenges Experience 13+ years of experience in RTL,UPF & Physical aware Synthesis for cutting edge technology nodes, logic equivalence checking, Scripting and Netlist Timing Signoff Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience 3+ years of experience in RTL,UPF & Physical aware Synthesis for cutting edge technology nodes, logic equivalence checking, Scripting and Netlist Timing Signoff Proficiency in Python/Tcl * Familiar with Synthesis tools (Fusion Compiler/Genus), * Fair knowledge in LEC, LP signoff tools * Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking * Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus * Should be sincere, dedicated and willing to take up new challenges Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Responsibilities Defining chip and macro level power domains System Level Power Modeling Mixed signal power analysis Power Island/Power Gating/Power Isolation Structural Low power design of level shifter and isolation cell topology and associated rules Architectural analysis and development of digital power optimization logic/circuits/SW Work with Power Management IC developers for power grid planning Creating detailed architecture and implementation documents Education Requirements RequiredBachelor's, Computer Engineering and/or Electrical Engineering PreferredMaster's, Computer Engineering and/or Electrical Engineering Work with cross-functional teams on SoC Power and architecture for mobile SoC ASICs. Skills/Experience At least 4-12 years of experience are required in the following areas Low power intent concepts and languages (UPF or CPF) Power estimation and reduction tools (PowerArtist/PTPX,Calypto) Power dissipation and power savings techniques- Dynamic clock and voltage scaling Power analysis (Leakage and dynamic) and thermal impacts Power Software features for power optimization Voltage regulators including Buck and Low Drop out ASIC Power grids and PCB Power Distribution Networks Additional skills in the following areas are a plus: Mobile Baseband application processors chipset and power grid understanding UPF-based synthesis and implementation using Design Compiler Structural low power verification tools like CLP or MVRC Outstanding written and verbal communication skills Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space. Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications 10-15 years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience Education Requirements RequiredBachelor's, Electrical Engineering or equivalent experiencePreferredMaster's, Electrical Engineering or equivalent experience Keywords Innovus, FC, UPF, STA, Formal Verification, Genus, Primetime, Tempus, SOD Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: About The Role Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in. You will be joining a successful engineering team whose deliveries can be found in billions of mobile, compute and IoT products worldwide. Based out of Qualcomm's Bangalore office, this role offers a position in Low Power controller IP cores and subsystem digital design targeted for variety of industry leading Snapdragon SoCs for mobile, compute, IoT and Automotive markets. Key Responsibilities Micro-architecture and RTL design for Cores / subsystems. Work in close coordination with Systems, Verification, SoC, SW, PD & DFT teams for design convergence. Enable SW teams to use HW blocks. Qualify designs using static tool checks including Lint, CDC, LEC and CLP. Synthesis, LEC and Netlist CLP Report status and communicate progress against expectations. Preferred Qualifications 4 to 10 years of strong experience in digital front end design (RTL design) for ASICs Expertise in RTL coding in Verilog/SV/VHDL of complex designs with multiple clock domains and multiple power domains Familiar with UPF and power domain crossing Experience in Synthesis, Logical Equivalence checks, RTL and Netlist CLP Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI Experience in low power design methodology and clock domain crossing designs Experience in Spyglass Lint/CDC checks and waiver creation Experience in formal verification with Cadence LEC Understanding of full RTL to GDS flow to interact with DFT and PD teams Expertise in Perl/TCL/Python language Experienced in database management flows with Clearcase/Clearquest. Expertise in post-Si debug is a plus Excellent oral and written communications skills to ensure effective interaction with Engineering Management and team members. Team player, self-motivated, should be able to work with minimal supervision. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Roles and Responsibilities Perform various electrical analyses at block and top levels, including static/dynamic IR, power/signal EM, and ESD Drive block and top-level electrical verification closure Develop power grid specs based on power/performance/area targets of different SOC blocks. Implement power grids in industry standard PnR tool environments. Work closely with the PI team to optimize the overall PDN performance. Work with CAD and tool vendors to develop and validate new flows and methodologies. Preferred qualifications BS/MS/PhD degree in Electrical Engineering; 4+ years of practical experience In-depth knowledge of EMIR tools such as Redhawk and Voltus Experience in developing and implementing power grid Good knowledge of system-level PDN and power integrity Practical experience with PnR implementation, verification, power analysis and STA Proficient in scripting languages (TCL/Perl/Python) Experience with industry standard EMIR tools such as Redhawk and Voltus Basic knowledge of the physical design flow and industry standard PnR tools Experience with scripting languages such as TCL, Perl and Python Ability to communicate effectively with cross-functional teams 4+ yrs exp in STA Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. 7-14 yrs experience in Physical Design and timing signoff for high speed cores. Should have good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology. Masters/Bachelors Degree in Electrical/Electronics science engineering with at least 7+ years of experience in IC design. Experience in leading block level or chip level Physical Design, STA and PDN activities. Work independently in the areas of RTL to GDSII implementation. Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.) Circuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.) Tcl/Perl scripting Willing to handle technical deliveries with a small team of engineers. Strong problem-solving skills. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Physical Implementation activities for Sub systems "which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl /Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Bachelor's/ Masters degree in Electrical /Electronic Engineering from reputed institution 2-10 years of experience in Physical Design/Implementation Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Preferred Qualifications 2-9 years of experience in SoC design Educational Requirements2+ years of experience with a Bachelors/ Masters degree in Electrical engineering Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail myhr.support@qualcomm.com or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.