1188 Synthesis Jobs - Page 48

Principal STA / Synthesis Engineer Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ BangaloreA US based well-funded product-based startup looking for Highly talented Engineers for the following roles.Constraint developmentConstraint managementConstraint validationChip top level synthesis, sta and Timing Closure.RTL2GDS flow.Ability to handle synthesis,sta, lec, upf flow methodologies.TCL/perl/python scripting.Candidate with 12+ yrs exp in Synthesis / STA roleExperience in handling complex data path-oriented multi-million gate synthesisWorking Knowledge of Physical synthesis using tools like Genus, Design CompilerExperience in debugging for multi-clock domains hierarchical/flat timing analysis.Hands-on experience in LEC along with strong debugging skills for resolving issues/aborts.Netlist and constraint sign in checks and validation.Prime time constraint development at full chip level and clean up.Multimode multi corner timing knowledge and timing closure at block/top level using tools like DMSAExcellent debugging skills in timing convergence issues and ability to come up with creative solutions .Technical leadership and ability to mentor and make the team deliver. Contact:UdayMulya Technologiesmuday_bhaskar@yahoo.com"Mining The Knowledge Community"

Senior SoC Director / SoC DirectorHyderabadFounded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/Bangalore A US based well-funded product-based startup looking for highly talented SoC Director for the following roles Senior Director / SoC Director of SOC is : Trust, loyalty, and ability to command Technical respect with foreign partners after having Taped out Successfully multiple chips to high volume production….this should be easily achieved under his/her belt !!!!!!!!Somebody we can trust to drive on the World stage without embarrassing us Job Description:We are seeking an experienced professional to lead full chip design for multi-million gate SoCs. The ideal candidate will have expertise in digital design and RTL development, with a deep understanding of the design convergence cycle, including architecture, micro-architecture, synthesis, timing closure, and verification.Key Responsibilities:Proficiency inInterconnect FabricCache CoherencyD2DC2COversee full chip design for complex SoCs.Develop and implement digital designs (RTL).Manage IP dependencies and track all front-end design tasks.Drive project milestones across design, verification, and physical implementation phases.Qualifications:At least 15-25 years of solid experience in SoC design.Proven ability to develop architecture and micro-architecture from specifications.Familiarity with bus protocols such as AHB and AXI, as well as peripherals like QSPI, NVMe, and I3C.Knowledge of memory controller designs and microprocessors is a plus.Understanding of chip I/O design and packaging is advantageous.Experience in reviewing top-level test plans.Expertise in Synopsys Design Compiler for synthesis and formal verification.Strong working knowledge of timing closure processes.Experience with post-silicon bring-up and debugging.Familiarity with SoC integration challenges.Knowledge of design verification aspects is essential.Experience from SoC specification to GDS and commercialization is highly desired.Ability to make timely and effective decisions, even with incomplete information.Demonstrated expertise in specific technical areas, with significant experience in related fields.Provide direction, mentoring, and leadership to small to medium-sized teams.Strong communication and leadership skills are necessary for effective collaboration with program stakeholders. Contact:UdayMulya Technologiesmuday_bhaskar@yahoo.com"Mining The Knowledge Community"

Exp: 3 to 15 YrsLocation: Hyderabad / Bangalore The core skill set expected from the team is : Exceptional Digital fundamentalsHands on experience in System Design with FPGA devices with relevant FPGA EDA toolsExperience in designing and implementing FPGA based solutions in Microchip or Xilinx or Altera FPGAsWrite high quality code in Verilog/System Verilog, VHDL and C code for embeddedprocessors. Maintain existing code.Developing testbenches using Verilog/System Verilog and verifying validation designs in simulation environment using BFM/VIPExperience in using Synthesis, Placement constraintsSTA constraint definition and Timing closure for high speed designsValidation of FPGA based implementation on HW boardExperience in writing embedded FW programs in C/C++Strong Lab debug experience and enthusiasm & patience to solve systems level hardware issues using Lab equipment, Embedded debuggers and RTL debuggersBe conversant with on-chip debug toolsExperienced with scripting tcl/perlExposure to Version management systems, GitHub, SVNExcellent verbal and written communication skills in EnglishStrong technical background in silicon validation, failure analysis and debugUnderstand hardware architectures, use models and system level design implementations required to utilize the silicon feature s.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and highly motivated ASIC Physical Design Engineer with a passion for technology and a knack for problem-solving. With over 5 years of relevant experience, you have honed your skills in state-of-the-art CAD tools and technologies, specifically ICC2/FC, ICV, and FinFet. You thrive in dynamic environments and are adept at handling crises with composure. Your excellent communication skills, both verbal and written, enable you to effectively collaborate with internal and external teams. You possess a strong desire to learn and explore new technologies, demonstrating excellent exploration and problem-solving skills. You are autonomous in your work, often guiding junior peers, and you bring innovative solutions to complex project challenges. Your ability to network with senior personnel and your awareness of project management issues make you a valuable asset to any team. What You’ll Be Doing: Implementing DDR and HBM PHYs for customer ASICs and SOCs in the DDR and HBM PHY Hardening service line.Performing synthesis, physical design, verification, design for test, and ATPG.Contributing as a senior member of a design team or as a project design engineer working with both internal and external design teams.Providing regular updates to the manager on project status.Representing the organization on business unit and/or company-wide projects.Guiding more junior peers with aspects of their job and frequently networking with senior internal and external personnel in your area of expertise. The Impact You Will Have: Enhancing the reliability and performance of DDR and HBM PHYs for customer ASICs and SOCs.Contributing to the success of complex projects through innovative problem-solving and technical expertise.Ensuring timely delivery of high-quality design solutions to our customers.Improving the efficiency and effectiveness of the design process through your autonomous judgment and technical knowledge.Strengthening Synopsys' position as a leader in chip design and verification through your contributions.Mentoring and guiding junior team members, fostering a collaborative and innovative team environment. What You’ll Need: A minimum of 5+ years of related experience in ASIC Physical Design.Proficiency in state-of-the-art CAD tools such as DC, PT, ICC2/FC, and ICV.Experience with advanced technologies like FinFet.Strong problem-solving skills and the ability to autonomously resolve a wide range of issues.Excellent verbal and written communication skills. Who You Are: An innovative thinker with a passion for technology and continuous learning.A collaborative team player who excels in a dynamic and fast-paced environment.A mentor and guide for junior team members.A strong communicator with the ability to network effectively with senior personnel.A composed and reliable professional who can handle risks and uncertainty with ease. The Team You’ll Be A Part Of: You will be part of an engineering team dedicated to implementing DDR and HBM PHYs for customer ASICs and SOCs. The team focuses on the DDR and HBM PHY Hardening service line, encompassing synthesis, physical design, verification, design for test, and ATPG. You will collaborate with both internal and external design teams, contributing to complex projects and driving technological innovation. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X). Job Description Provide technical and managerial Leadership to a PD team for a SoC Chip development owning partitions and full-chip from synthesis to place and route through all sign-off including timing signoff, physical verification, EMIR signoff, and formal verification.Influence tools, flows, and overall design methodology in design construction, signoff, and optimization.Work closely with architecture/RTL/DFT/DV/Package development teams.Be a technology expert in the area of Physical Design with in the team and business Unit. Minimum Qualifications 10 to 15 years of experience in Physical Design.Proven experience in implementing designs through synthesis, Floorplanning, place and route, extraction, timing, and physical verification.Technically lead a team of PD engineers on the Physical Design activities of complex SoCs. Strong understanding of constraints generation, timing optimization, and timing closure and STA.Strong technical problem solving and debugging abilityExperience in EDA tools related to Place and route, Synthesis, Physical Verification , STA etc.Proficient understanding of CTS and different clock building techniquesExperience with multi-clock, multi-power-domain design, UPF etcExperience in IP integration (memories, IO’s, embedded processors, hard macros, Analog IP)Knowledge of Microelectronics conceptsScripting skills in Python, Tcl, C etcAbility to collaborate and work directly with the tool vendors to resolve tools bugs, as well as implement the required improvementsGreat communication and teamwork skills For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process. Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group. Job Req Type: Experienced Required Travel: Yes, 10% of the time Shift Type: 1st Shift/Days

Locations: Bengaluru | Gurgaon Who We Are Boston Consulting Group partners with leaders in business and society to tackle their most important challenges and capture their greatest opportunities. BCG was the pioneer in business strategy when it was founded in 1963. Today, we help clients with total transformation-inspiring complex change, enabling organizations to grow, building competitive advantage, and driving bottom-line impact. To succeed, organizations must blend digital and human capabilities. Our diverse, global teams bring deep industry and functional expertise and a range of perspectives to spark change. BCG delivers solutions through leading-edge management consulting along with technology and design, corporate and digital ventures—and business purpose. We work in a uniquely collaborative model across the firm and throughout all levels of the client organization, generating results that allow our clients to thrive. What You'll Do As a part of BCG's X team, you will work closely with consulting teams on a diverse range of advanced analytics and engineering topics. You will have the opportunity to leverage analytical methodologies to deliver value to BCG's Consulting (case) teams and Practice Areas (domain) through providing analytical and engineering subject matter expertise.As a Data Engineer, you will play a crucial role in designing, developing, and maintaining data pipelines, systems, and solutions that empower our clients to make informed business decisions. You will collaborate closely with cross-functional teams, including data scientists, analysts, and business stakeholders, to deliver high-quality data solutions that meet our clients' needs. YOU'RE GOOD AT Delivering original analysis and insights to case teams, typically owning all or part of an analytics module whilst integrating with a case team. Design, develop, and maintain efficient and robust data pipelines for extracting, transforming, and loading data from various sources to data warehouses, data lakes, and other storage solutions.Building data-intensive solutions that are highly available, scalable, reliable, secure, and cost-effective using programming languages like Python and PySpark.Deep knowledge of Big Data querying and analysis tools, such as PySpark, Hive, Snowflake and Databricks.Broad expertise in at least one Cloud platform like AWS/GCP/Azure.* Working knowledge of automation and deployment tools such as Airflow, Jenkins, GitHub Actions, etc., as well as infrastructure-as-code technologies like Terraform and CloudFormation.Good understanding of DevOps, CI/CD pipelines, orchestration, and containerization tools like Docker and Kubernetes.Basic understanding on Machine Learning methodologies and pipelines.Communicating analytical insights through sophisticated synthesis and packaging of results (including PPT slides and charts) with consultants, collecting, synthesizing, analyzing case team learning & inputs into new best practices and methodologies. Communication Skills Strong communication skills, enabling effective collaboration with both technical and non-technical team members. Thinking Analytically You should be strong in analytical solutioning with hands on experience in advanced analytics delivery, through the entire life cycle of analytics. Strong analytics skills with the ability to develop and codify knowledge and provide analytical advice where required. What You'll Bring Bachelor's / Master's degree in computer science engineering/technologyAt least 2-4 years within relevant domain of Data Engineering across industries and work experience providing analytics solutions in a commercial setting.Consulting experience will be considered a plus.Proficient understanding of distributed computing principles including management of Spark clusters, with all included services - various implementations of Spark preferred.Basic hands-on experience with Data engineering tasks like productizing data pipelines, building CI/CD pipeline, code orchestration using tools like Airflow, DevOps etc.Good to have:-Software engineering concepts and best practices, like API design and development, testing frameworks, packaging etc.Experience with NoSQL databases, such as HBase, Cassandra, MongoDBKnowledge on web development technologies.Understanding of different stages of machine learning system design and development #BCGXjob Who You'll Work With You will work with the case team and/or client technical POCs and border X team. Boston Consulting Group is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, age, religion, sex, sexual orientation, gender identity / expression, national origin, disability, protected veteran status, or any other characteristic protected under national, provincial, or local law, where applicable, and those with criminal histories will be considered in a manner consistent with applicable state and local laws. BCG is an E - Verify Employer. Click here for more information on E-Verify.

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting Principal Duties And Responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 8+ years Hardware Engineering experience or related work experience. 6+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3071188

Role Description Role Proficiency: Execute any internal project or small tasks of customer project in any field of VLSI Frontend Backend or Analog design under minimal supervison from the Lead Outcomes As an Individual contributor work on any one task of RTL Design/Module in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc. Analyse and complete the assigned task in the defined domain(s) successfully on-time with minimal support from senior engineersEnsure quality delivery as approved by the senior engineer or project lead Measures Of Outcomes Quality –verified using relevant metrics by Lead/Manager Timely delivery - verified using relevant metrics by Lead/Manager Reduction in cycle time and cost using innovative approaches Number of trainings attended Outputs Expected Quality of the deliverables: Clean delivery of the module in-terms of ease in integration at the top levelEnsure functional spec / design guidelines are met 100% of the time without deviation or limitationDocumentation of the tasks and work performed Timely Delivery Meet project timelines as given by the team lead/program managerHelp with intermediate tasks delivery by other team members to ensure progress Teamwork Teamwork participation; supporting team members in the time of needAble to perform additional tasks in case of any team member(s) is not available Innovation & Creativity Pro-actively plan approach towards repeated work by automating tasks to save design cycle timeParticipation in technical discussion training forum Skill Examples Languages and Programming skills:a. System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice (any one) EDA Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (any one) Technical Knowledge: (any one)a. Understands IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb. Knows Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec. Good knowledge of Physical Design / Circuit Design / Analog Layout d. Good understanding of Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verificatione. Knowledge in Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below Required technical skills and prior design knowledge to execute assigned tasks Ability to learn new skills in case required technical skills are not present to a level needed to execute the project Able to deliver tasks with quality and 100% on-time per quality guidelines and GANTT Strong communication skillsGood analytical reasoning and problem-solving skills with attention to detail Knowledge Examples Previous project experience in any of the design by executing any one of the following RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc. Good Understanding of the design flow and methodologies used in designing Understand the assigned tasks and have sufficient knowledge to execute the project tasks assigned by the client / manager per skill set Additional Comments Required Primary Key skills – STA, nano time Job Description: You will be part of a Physical Design / Timing Closure team for projects with GHz freq range and cutting-edge technologies. You will develop timing constraints for full chip or block level and be responsible for STA signoff for a complex multi-clock, multi-voltage SoCs. You will be responsible for Synthesis, Timing Analysis (STA), CTS at Full Chip or block level for Lower tech node ( Below 14nm) Desired Skills and Experience: B. Tech. / M. Tech. with 2-8 years of experience in Synthesis, STA Expertise in synthesis of complex SoCs at block/top level and writing timing constraints for complex designs with multiple clocks and multiple voltage domains Worked on pre and post layout timing analysis and resolving the issues Expertise on post layout timing closure for multiple tape outs, including timing ECOs and STA signoff Expertise in I/O constraints developments for Industry standard protocols (e.g. DDR1/2/3, SDR, LPDDR, Flash, SPIs, Ethernet, USBHS, USBFS, JTAG, Display etc...) Hands-on experience of working on technology nodes like 28nm, 20nm, 14nm, 10nmGood knowledge of EDA tools from RC, DC, PT, PTSI Experience in formal verification RTL-to-netlist and netlist-to-netlist with DFT constraints Good knowledge of VLSI process and device characteristics Good understanding of deep submicron parasitic effects, crosstalk effects etc.TCL, perl scripting Skills Vlsi,Tlc,Perl

About The Job Our Team: Sanofi Global Hub (SGH) is an internal Sanofi resource organization based in India and is setup to centralize processes and activities to support Specialty Care, Vaccines, General Medicines, CHC, CMO, and R&D, Data & Digital functions. SGH strives to be a strategic and functional partner for tactical deliveries to Medical, HEVA, and Commercial organizations in Sanofi, Globally. Main Responsibilities The overall purpose and main responsibilities are listed below: Create HEVA communications deliverables (including manuscripts, posters, abstracts, slide decks) aligned with HEVA strategy and global HEVA communication plan across relevant business units and product teams. Manage core HEVA communication processes, templates, and products across the portfolio in accordance with the scientific and value messages aligned with Core Value Dossier, the US AMCP Dossier, and HEVA contributions as appropriate to other submissions. Ensure Core Value Decks for key products are established and maintained, making available a regularly updated synthesis of critical HEVA evidence on the value of products. Maintain accountability for adherence to the publication standard operating procedure (SOP) and other compliance expectations relevant to HEVA communication processes. Seek opportunities to innovate HEVA value communications to increase the relevance and impact of HEVA evidence and inform optimal access and reimbursement decisions. Develop and maintain therapeutic area expertise. Coach junior HEVA writers and develop and review content created by them. Manage end to end process through iEnvision (previously, Datavision/Matrix). Collaborate effectively with stakeholders: HEVA, RWE, and Scientific communication global and/or local teams. People: (1) Maintain effective relationships with the end stakeholders within the allocated GBU and product – with an end objective to develop education and communication content as per requirement for HEVA communications; (2) Interact effectively with healthcare professionals on publication content; and (3) Constantly assist other writers (junior) in developing knowledge and sharing learningPerformance: (1) Create HEVA communications deliverables (including manuscripts, posters, abstracts, and slide decks) aligned with HEVA strategy and global HEVA communication plan across relevant business units and product teams as per agreed timelines and quality; and (2) Provide strategic support with individuals and institutions, which may serve as resources for publications purpose, etcProcess: (1) Develop complex publications material; (2) Act as an expert in the field of medical communication for the assigned therapeutic area; (3) Assist the assigned scientific communication team in conducting comprehensive publication-needs analysis; (4) Manage core HEVA communication processes, templates, and products across the portfolio in accordance with the scientific and value messages aligned with Core Value Dossier, the US AMCP Dossier, and HEVA contributions as appropriate to other submissions; (5) Ensure Core Value Decks for key products are established and maintained, making available a regularly updated synthesis of critical HEVA evidence on the value of products; (6) Maintain accountability for adherence to the publication SOP and other compliance expectations relevant to HEVA communication processes; (7) Maintain accountability for adherence to the publication SOP and other compliance expectations relevant to HEVA communication processes; (8) Implement relevant element of publication plan and associated activities for the year identified for the region; (9) Work with selected vendors within the region to deliver the required deliverables as per defined process; and (10) Design an overall plan of action based on end-user feedback and improve course content and deliveryStakeholder: (1) Work closely with HEVA global and local teams, RWE global and local teams and scientific communication teams in regions/areas to identify publications needs and assist in developing assigned deliverables; and (2) Liaise with HEVA global and local teams to prepare relevant and customized deliverables About You Experience: >4 years of experience in content creation for the pharmaceutical/healthcare industry, or academiaSoft skills: Stakeholder management; communication skills; and ability to work independently and within a team environmentTechnical skills: Relevant training/experience in health economics, public health, epidemiology, or other relevant health-related scientific discipline (including but not limited to therapeutic area/domain knowledge exposure; knowledge of Good Publication Practice; publication submission; and/or project management)Education: Advanced degree in life sciences/pharmacy/similar discipline or medical degreeLanguages: Excellent knowledge of English language (spoken and written) Pursue progress, discover extraordinary Better is out there. Better medications, better outcomes, better science. But progress doesn’t happen without people – people from different backgrounds, in different locations, doing different roles, all united by one thing: a desire to make miracles happen. So, let’s be those people. At Sanofi, we provide equal opportunities to all regardless of race, colour, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, or gender identity. Watch our ALL IN video and check out our Diversity Equity and Inclusion actions at sanofi.com! null

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence Design Systems is looking for a highly motivated engineer to be part of the Modus R&D team, with a focus on validating and supporting Design-for-test (DFT) technologies. Candidate must have 2+ years of experience in DFT/ATPG/ASIC Design flows and knowledge of RTL Verilog/VHDL coding styles, Synthesis. This position requires excellent communication skills (written and oral) to interface with Product Engineers (PEs) and R&D and will occasionally also involve direct customer support responsibilities. Will work on complex problems that require innovative thinking, debugging customer reported problems and collaboration with R&D to propose out-of-box solutions with emphasis on robustness, PPA and scalability. Role Responsibility Work as a DFT Product Validation Engineer on insertion and validation of DFT technologies such as 1500 Wrapper, Compression, RTL DFT, Low Pin Count Test, Hierarchical Test, LBIST etc. using Cadence Synthesis tool Genus and ATPG using Cadence Test tool Modus on in-house and customer designs. Create testplans for verification of new features and execute them by creating new test cases requiring application of Design & DFT skills; Report bugs/enhancements in tool. Collaborate with R&D and Product Engineering teams to review feature specifications, testplans & customer issues. Debug issues reported by customers and suggest/implement measures to plug the gaps. Position Requirements B.E/B.Tech with 2+ years or M.E/MTech in Electronics/Electrical of experience Strong in Digital electronics, Verilog Good understanding of DFT techniques and methodologies Familiarity with Test standards like 1149.1, 1500, 1687 is a plus Experience with Cadence Test or other Test tools is preferred Modus is a DFT (Design for Testability) software tool from Cadence used by leading chip design companies during DFT synthesis & ATPG (Automatic Test Pattern Generation) phase of chip design We’re doing work that matters. Help us solve what others can’t.

We believe real value is powered by the unique skills and experiences of our professionals. The interchange of ideas from a diverse group of people gives our teams an expanded perspective and the ability to find better solutions for our clients. Req Id : 107042 Job Title : Environmental and Social Analyst Business Unit sector : CPL-STRGW-GLOBAL ADVISORY Department: BVCPL - GLOBAL ADVISORY Work Location : INMUMBAI2 Opportunity Type : Staff Relocation eligible : Yes Full time/Part time : Full-Time Contract Hire Only for this Project: No Visa Sponsorship Available: [[custVisaSponsorship]] Recruiter : Sonia Suresh Bangera Job Summary Compiling analysis and preparation of deliverables to contribute to the completion of multiple engagement phases of a project. Demonstrate capabilities with moderate to high level of supervision, depending on complexity and scope of the project. Key Responsibilities Undertake LTA (Lender’s Technical Advisor), Environmental & Social Due Diligence, ESIA, Support in Environmental and Permitting Review in Technical Due Diligence (TDD) and Operations / Construction Monitoring activities and reporting engagements Compiling analysis and preparation of deliverables to contribute to the completion of multiple engagement phases of a project. Demonstrate capabilities with low level of supervision Support sustainability and decarbonization related project activities Guide and mentor more junior colleagues, share specialist knowledge with the broader Global Advisory team Support proposal development activities under the supervision of project and proposal management professionals Consulting Capability: Delivers or contributes to the development of work products throughout at least one phase of an engagement Co-facilitates group discussions with team members or client representatives Uses recognized methods to deliver work products Contributes to risk and issue identification and synthesis of solutions Industry knowledge capability: delivers work products and demonstrates a broad knowledge of an industry or market including trends, current state of the art and driving factors collects and analyzes information specific to the industry to recommend alternatives proactively develops additional knowledge applicable to the area of expertise Project delivery: manages personal accountabilities during at least one phase in an overall engagement; ability to lead simple deliverables related to core competency Management Responsibilities Individual Contributor Preferred Qualifications Must have - Masters in Environmental Sciences Preferrable Secondary qualifications in related field PG Diploma in Social Science/Sociology or Environmental Law 4-7 years’ experience in environmental & permitting roles for power and oil & gas. Excellent English speaking and report writing skills, ability to work with multi-cultural teams across different time zones and in a virtual setting Good communication skills and personal presence for client interactions Willingness to travel and multi-task to meet tight timelines while working independently with minimal supervision Minimum Qualifications Bachelor's Degree + 2-4 years experience OR Master's degree. 2-4+ years experience in a business/consulting environment. All applicants must be able to complete pre-employment onboarding requirements (if selected) which may include any/all of the following: criminal/civil background check, drug screen, and motor vehicle records search, in compliance with any applicable laws and regulations. Certifications Certifications related to area of expertise, where applicable preferred Work Environment/Physical Demands B&V Office or Client environment - travel up to 100% Competencies Action oriented Customer focus Interpersonal savvy Salary Plan CST: Consulting Job Grade 002 BVH, Inc., its subsidiaries and its affiliated companies, complies with all Equal Employment Opportunity (EEO) affirmative action laws and regulations. Black & Veatch does not discriminate on the basis of age, race, religion, color, sex, national origin, marital status, genetic information, sexual orientation, gender Identity and expression, disability, veteran status, pregnancy status or other status protected by law. Black & Veatch is committed to being an employer of choice by creating a valuable work experience that keeps our people engaged, productive, safe and healthy. We offer professionals an array of health and welfare benefits that vary based on their geographic region and employment status. This may include health, life accident and disability insurances, paid time off, financial programs and more. Professionals may also be eligible for a performance-based bonus program. By valuing diverse voices and perspectives, we cultivate an authentically inclusive environment for professionals and are able to provide innovative and effective solutions for clients.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: As an ideal candidate for the ASIC Digital Design Engineer, Senior role, you are a highly motivated and innovative individual with a deep understanding of ASIC development flow. You are someone who thrives in dynamic environments and embraces the challenges that come with constant technological changes. You are self-motivated, proactive, and able to balance good design quality with tight deadlines. Your excellent communication skills enable you to interact seamlessly with different design groups and customer support teams. You are known for your ability to resolve issues creatively and exercise independent judgment in selecting methods and techniques to obtain solutions. You are a team player who can produce excellent results both as an individual and as part of a team. What You’ll Be Doing: Supporting development and verification of ASIC digital designs for next-generation NRZ and PAM-based SerDes products.Setting up and running lint/cdc/rdc checks using VC-Spyglass and synthesis flow using Design Compiler/Fusion Compiler.Working with Verilog and VCS to ensure design accuracy.Defining synthesis design constraints and resolving STA issues.Setting up and running FPGA prototyping flows to map RTL designs to Xilinx FPGAs. The Impact You Will Have: Contributing to the development of cutting-edge SerDes products that lead the industry.Enhancing the performance, power, and size efficiency of our silicon IP offerings.Enabling rapid market entry for differentiated products with reduced risk.Driving innovation in high-speed digital design and data recovery circuits.Supporting the creation of high-performance silicon chips and software content.Collaborating with a world-class team to solve complex design challenges. What You’ll Need: BSEE or MSEE with a minimum of 2 years of experience in digital design and front-end flows.Proficiency in running lint/cdc/rdc checks and synthesis flow.Experience in coding, verifying Verilog and System Verilog design.Experience of working with minimum supervision and owning and delivering for front-end activities in IP/SOC.Experience of leading technically for front-end activities.Knowledge of digital design methodologies, DFT insertion, synthesis constraints, and flows.Scripting experience in Shell, Perl, Python, and TCL (preferred). Who You Are: Excellent communicator with the ability to interact with diverse teams.Self-motivated and proactive, with a strong attention to detail.A creative problem-solver who can think independently.Capable of working under tight deadlines while maintaining high-quality standards.A team player who can contribute effectively both individually and collaboratively. The Team You’ll Be A Part Of: Join our highly experienced mixed-signal design and verification team, where you will work alongside experts in digital and mixed-signal engineering. Our team is dedicated to developing innovative solutions for the next generation of high-speed SerDes products, providing continuous training and opportunities for growth. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

To work as a Frontend Lead and taking care of Synthesis, LEC, CLP and Power Analysis for complex SoC projects. Job Description In your new role you will: Implement high-performance, low-power, and area-efficient digital designs.Write and implement block level and top-level constraints for Synthesis, Static Timing Analysis.Optimize designs for power, performance, and area, and meet PPA goals.Power analysis using PT-PX or equivalent flow.Logic Equivalence Check (LEC) and Low Power Checks (CLP) at block and SoC level designs.Define and evaluate constraints and signoff Test/DFT mode timing requirements. Your Profile You are best equipped for this task if you have: Strong fundamentals and experience in Synthesis and STA domains.Write and implement block level and top-level timing constraints for SynthesisOptimize designs for power, performance, and area, and meet design goals.Knowledge on Power analysis and PT-PX flow.Understanding of DFT flows, including scan insertion.Write and evaluate Test/DFT mode timing constraints.Thorough with Logic Equivalence Check debug capability.Well known about UPF concepts and Low Power Checks at block and full chip level.Defining and verification of STA constraint for Functional and Test/SCAN Modes.Defining PVT’s corners required for covering all desired scenarios for a designKnowledge on OCV/AOCV/POCV derates.Understanding of Prime-Time and TEMPUS tools, which helps in quick debugging of design/timing issues.VASTA timing closure based on chip IR drop.Knowledge on signal SI analysis and PT-PX flow. . Contact: Swati.Gupta@infineon.com #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.