2285 Synthesis Jobs - Page 47

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 5+ years Hardware Engineering experience or related work experience. 5+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. : Would be working on Qualcomm SoC System level Power and Performance in bare-metal validation environment. Develop comprehensive testplan for power and performance validation of the SoC both from a usecase requirement as well as design delta motivated. Determine Key Performance Indicator for the performance study by working closely with the respective IP teams in Design, DV and validation. Validation of System Low Power Modes, SoC shared rail power collapse validation Responsible for driving deep dive analysis on performance issues, bottlenecks and validating fixes or workarounds on subsystem and related SOC Modules. The ideal candidate would have a strong SoC architecture background along with good embedded system concepts on modern ARM/X86 based chipsets. Interface with subsystem validation, debug tools and SW teams during debugs. Develop low-level custom code on ARM and Hexagon Q6 processors using C/C++ and validate functionality and performance KPIs using debug trace dump Job : Bachelor's degree in Engineering, Computer Science, Electronics/Electrical Engineering or related field and 5+ years of full time experience ORMasters's degree in Engineering, Computer Science, Electronics/Electrical Engineering or related field and 3+ years of full time experience Familiar with CPU and SoC Architecture and micro-architecture, preferably ARM or ARM processor-based systems, clocking schemes, hierarchical memory systems, cache configurations and coherency issues in multi-core systems. Fundamental understanding of Static, Leakage and Dynamic power in a semiconductor design Experience with workload performance characterization, bandwidth and latency analysis, and driving microarchitecture investigations on CPU/GPU/Multimedia Systems with relevant performance metrics. Logical thinking and problem-solving ability with focus on performance centric validation Familiar with pre-silicon validation environments with Emulation and Virtual Bring-Up, etc. Basic statistics and data analysis skills to identify performance trends from large data sets and the technical bent to investigate anomalies (Good to have) Strong programming experience in at least one languageC,C++, Python (Must have) Good communication, English speaking/writing and team work attitude

Job Area: Engineering Group, Engineering Group > Machine Learning Engineering General Summary: Job Overview Qualcomm is a company of inventors that unlocked 5G - ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. We are investing in several supporting technologies including 4G, 5G, Edge Computing, and Deep Learning. The Qualcomm AI team is developing hardware and software for Machine Learning solutions spanning the data center, edge, infrastructure, automotive markets and beyond. We are seeking ambitious, bright and innovative engineers with experience in Machine learning frameworks, compiler technology, vectorization and optimization, and machine learning toolchains. Job activities span the whole product life cycle from early design to commercial deployment. The environment is fast-paced and requires cross-functional interaction on a daily basis so good communication, planning and execution skills are a must. We are looking to staff engineers at multiple levels in systems & software, integration and test. Details of one of the roles we are looking to staff are listed below. Responsibilities Research, design, develop, enhance, and implement the different components of machine learning framework, compilers based on performance and code-size needs of the customer workloads and benchmarks. Analyze software requirements, determine the feasibility of design within the given constraints, consult with architecture and HW engineers, and implement software solutions best suited for Qualcomm's SOCs. Analyze and identify system level integration issues, interface with the software development, integration and test teams. Minimum Qualifications Bachelor's degree in Engineering, Information Systems, Computer Science, or related field. 8+ years Systems Engineering or related work experience. Preferred Qualifications Has internal working knowledge of Machine learning frameworks like Pytorch, Tensorflow. Has experience in model level optimization using techniques like torch compile. LLVM or any industrial strength compiler development experience is a plus. Knowledge of the structure and function of the compiler internals. Hands on experience writing SIMD and/or multi-threaded high-performance code is a plus. Hands-on experience implementing DSP Kernels a plus Hands-on Experience in C/C++, Python development (5+ years) Hands-on Experience with Object Orientated Design, TDD development solutions such as GoogleTest etc. (4+ years) Experience with Source Code and Configuration management tools, git knowledge is required Willingness to work in a cohesive software development environment with ability to work on low level implementation (code & test) and interfacing with hardware and simulators Experience in neural network architectures + ML compiler workload synthesis, a plus Prior working experience of hardware accelerators and hardware software co-design Experience in using C++ 14/17 (advanced features) Experience at both the firmware (RTOS) and system level (Linux) in SOC Experience of profiling software and optimization techniques Passion to drive to develop leading-edge "deep learning" framework and algorithms working on mobile and embedded platforms. Minimum Qualifications: Bachelor's degree in Computer Science, Engineering, Information Systems, or related field and 6+ years of Hardware Engineering, Software Engineering, Systems Engineering, or related work experience. OR Master's degree in Computer Science, Engineering, Information Systems, or related field and 5+ years of Hardware Engineering, Software Engineering, Systems Engineering, or related work experience. OR PhD in Computer Science, Engineering, Information Systems, or related field and 4+ years of Hardware Engineering, Software Engineering, Systems Engineering, or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Strong problem-solving skills and good communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3- 6yrs years of experience in Physical Design/Implementation

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Principal Duties and Responsibilities: 5+ Years of Experience in Logic design /micro-architecture / RTL coding Must have hands on experience with SoC design, synthesis and timing analysis for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Work closely with the SoC DFT, Physical Design and STA teams Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as DesignCompiler, Genus, FusionCompiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. As CPU Physical Design CAD engineer, you will build and support the world’s best implementation tools and flows. Your tools and flows will ensure our custom CPUs have industry-leading power, performance and area. Roles and Responsibilities Develop, integrate and release new features in our high-performance place-and-route CAD flow Architect and recommend methodology improvements to ensure our silicon has the best power, performance and area Maintain, support and debug implementation flows, and resolve project-specific issues Work closely with worldwide CPU physical design teams, and provide methodology guidance, tools/flows support and help achieve class-leading PPA. Work with EDA vendors to define roadmap and to resolve tool issues Preferred Qualifications: Bachelors/Masters degree in Electrical/Electronics Engineering or Computer Science Ten+ years of hands-on experience in place-and-route of high-performance chips - either in a design or CAD role High level of proficiency in Tcl as well as Python Experience with automation Experience with a wide variety of Physical Design tasks - ranging all the way from place-and-route, analysis, timing sign-off and PDV Experience with advanced technology nodes (5nm or lower) Solid understanding of digital design, timing analysis and physical verification Strong user of industry-standard place-and-route tools such as Cadence Innovus Proven track record of managing and regressing place-and-route flows

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Function Camera Design Lead/Staff Candidate will be responsible for design/developing next generation SoCs sub systems for mobile phone camera . Candidate will be working on ASIC based on the latest technology nodes. This role will require the candidate to understand and work on all aspects of VLSI development cycle like architecture, micro architecture, Synthesis/PD interaction and design convergence. Skills/Experience 5-10 years with Masters (6 to 10 years with Bachelors) Solid experience in digital front end design for ASICsSolid Expertise in RTL microarchitecture and design coding in Verilog/SV for complex designs with multiple clock and power domainsExpertise with various bus protocols like AHB, AXI and NOC designs Experience in low power design methodology and clock domain crossing designsUnderstanding of full RTL to GDS flow to interact with DFT and PD teams Experience in Tools like Spyglass Lint/CDC checks and waiver creationExperience in formal verification with Cadence LEC Experience in mobile Multimedia/Camera design is a plus DSP /ISP knowledge is a plus. Working knowledge of timing closure is a plusExpertise in Perl, TCL language is a plusExpertise in post-Si debug is a plus Good documentation skillsAbility to create unit level test plan General Should possess good communication skills to ensure effective interaction with Engineering Management and mentor group members. Should be self-motivated and good team working attitude and need to function with little direct guidance or supervision Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Experience 7 to 10 years Physical design of block level with full understanding of PnR cycle. Good understanding of Physical design fundamentals Good hands-on experience on industry standard pnr tools like ICC2/Innovus Good understanding on signoff tool like Prime time , Redhawk and calibre Should be able to guide junior engineers in resolving technical issues. Tools ICC/Innovus, PT, StarRC, Redhawk, Calibre DRC/LVS ScriptingTCL, Perl

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 2-4 yrs experience in Physical Design and timing signoff for high speed cores. Should have good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology. Masters/Bachelors Degree in Electrical/Electronics science engineering with at least 7+ years of experience in IC design . Experience in leading block level or chip level Physical Design, STA and PDN activities. Work independently in the areas of RTL to GDSII implementation. Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.) Circuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.) Tcl/Perl scripting Willing to handle technical deliveries with a small team of engineers. Strong problem-solving skills.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Job Role * Physical Design Life cycle of chip development, especially Floorplanning and PnR * Hands on PD execution at block/SoC level along with PPA improvements * Strong understanding of the technology and PD Flow Methodology enablement. * Work with Physical design engineers to rollout robust, identify areas for flow improvement methodologies. (area/power/performance/convergence), develop plans and deploy/support them * Provide tool support and issue debugging services to physical design team engineers across various sites * Develop and maintain 3rd party tool integration and productivity enhancement routines * Understand advance tech PNR and STA concepts and methodologies and work closely with EDA vendors to deploy solutions. Skill Set * Strong programming experience & Proficiency in Python/Tcl/C++ * Understand physical design flows using Innovus/fc/icc2 tools * Knowledge of one of Encounter/Innovus or FC (or other equivalent PNR tool) is mandatory * Basic understanding of Timing/Formal verification/Physical verification/extraction are desired * Ability to ramp-up in new areas, be a good team player and excellent communication skills desired Experience 3-5 years of experience with the Place-and-route and timing closer and power analysis environment is required Niche Skills Handling support tools like Encounter/Innovus/edi/fc/Icc2 (or other equivalent PNR tool). One or more of the above is mandatory*

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Work with cross-functional teams on SoC Power and architecture for mobile SoC ASICs. Skills/Experience At least 4-12 years of experience are required in the following areas: Low power intent concepts and languages (UPF or CPF) Power estimation and reduction tools (PowerArtist/PTPX,Calypto) Power dissipation and power savings techniques- Dynamic clock and voltage scaling Power analysis (Leakage and dynamic) and thermal impacts Power Software features for power optimization Voltage regulators including Buck and Low Drop out ASIC Power grids and PCB Power Distribution Networks Additional skills in the following areas are a plus: Mobile Baseband application processors chipset and power grid understanding UPF-based synthesis and implementation using Design Compiler Structural low power verification tools like CLP or MVRC Outstanding written and verbal communication skills Responsibilities Defining chip and macro level power domains System Level Power Modeling Mixed signal power analysis Power Island/Power Gating/Power Isolation Structural Low power design of level shifter and isolation cell topology and associated rules Architectural analysis and development of digital power optimization logic/circuits/SW Work with Power Management IC developers for power grid planning Creating detailed architecture and implementation documents Education RequiredBachelor's, Computer Engineering and/or Electrical Engineering PreferredMaster's, Computer Engineering and/or Electrical Engineering Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. J Principal Responsibilities: Senior leader with 20+ CAD/Methodology development experience for team in Bengaluru. Drive tools, flows, methodologies globally as part of world-wide CAD organization. Develop and implement advanced CAD flows and methodologies for front end RTL Design to Verification Methodologies and framework development. Utilize scripting languages (python) to automate CAD/IT processes and increase efficiency. Collaborate with cross-functional teams to ensure successful integration of CAD flows. Stay up-to-date with cutting-edge technology (AI/ML), conduct thorough analysis of CAD tools and make improvements. Work closely with users to troubleshoot and resolve any issues that arise in tools, flows, environment, and infrastructure. Preferred Qualifications: Experience building full stack AI applications, with a focus on practical, production-grade solutions Strong proficiency in Rust for performance-critical systems and Python for AI development and scripting . Solid understanding of large language models (LLMs), their mechanics, and their real-world applications. Experience implementing tool use capabilities for LLMs and agent frameworks Knowledge of evaluation methodologies for fine-tuned language models Good grasp of Retrieval-Augmented Generation (RAG) and latest AI Agent frameworks Ability to stay current with the fast-evolving AI landscape]. Including advancements in LLMs and neural networks Strong understanding of CAD/EDA tools and methodologies. Hands on experience with regression systems, CI/CD, Revision Control System (git, perforce) workflow. Strong fundamentals in digital design, design verification methodologies and EDA tools. Knowledge of SOC architecture is a plus Preferred – Masters in VLSI or Computer Science Minimum – Bachelors in Electronics/Electrical Engineering/Computer Science Atleast 15 years’ experience in development of tools/flows/methodologies in either RTL, DV, synthesis, PnR or Signoff. Should have a proven record of driving new innovative tool/flow/methodology solutions. Should have managed a medium sized team. Level of Responsibility: Works independently with minimal supervision. Work with chip leads in support of design verification. Collaborate with chip leads to understand the design methodology. high-level requirements, determine other areas to support current or future designs that can benefit from automation and tooling. Provides supervision/guidance to other team members. Decision-making is significant in nature and affects work beyond immediate work group. Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm's Bangalore WLAN PHY (Baseband) team is seeking VLSI Digital Design Engineers to lead IP development for the latest WiFi standards. Our WLAN PHY team, comprised of highly passionate and seasoned domain experts, prides itself on years of experience in taking WLAN PHY designs from concept to silicon independently. WLAN PHY team is responsible for delivering the end-to-end Tx/Rx DSP chains – all the way from antenna samples post ADC to raw bits for upper layers and on the reverse path from raw bits to DAC. The team specializes in working with challenges of practical high-speed wireless communication systems and finding innovative solutions to counter them. The team works extensively on typical signal processing functions like filters, matrix transformations (e.g.QR, Cholesky decomposition), channel estimation, equalization (MMSE, MRC, ML), decoders/encoders (e.g.LDPC, Viterbi) , demodulators, FFT etc. on a day-to-day basis, and contributes to the development/ enhancement/ evaluation of signal processing algorithms to cater to new requirements. We are looking for someone as passionate as us and takes pride in their work. WiFi's ubiquity in modern times is undeniable, and the IEEE 802.11 Working Group is continually developing new standards to satisfy the growing demand for high throughput and low-latency real-time applications, such as VR and AR. Qualcomm is at the forefront of the WiFi revolution, aiming to become the global leader in WiFi chip solutions. The WLAN PHY team in Bangalore is instrumental in realizing this vision. : Looking for a candidate with 1 to 3 years of hands-on experience in micro-architecting and developing complex IPs. Expertise in digital design, VLSI concepts, and experience in creating power/area-efficient IPs across multiple clock domains are essential. Proficiency in RTL coding and familiarity with RTL QA flows such as PLDRC, CDC, and CLP (optional) is expected. Candidates should be capable of proposing design alternatives to meet area/power/performance specifications and presenting these options for review. Experience in leading, guiding, or managing junior team members is advantageous. Repeated success in taking IP designs from requirements to silicon is required. While not mandatory, having developed IPs for wireless technologies (WLAN, LTE, NR, BT, UWB, etc.) or past HLS experience would be beneficial. Skills: Must have: Proficient in Verilog RTL coding, uArch, CDC check, PLDRC, Timing constraints, Python/Perl. Experience in design/debugging complex data-path/control-path IPs. Good communication, analytical & leadership skills. Good to have: System Verilog, Visio, Knowledge of signal processing concepts/algorithms and Wi-Fi standards (802.11a/b/g/n/ac/ax), experience with HLS. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Responsibilities: STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs. Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus. Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. Evaluate multiple timing methodologies/tools on different designs and technology nodes. Work on automation scripts within STA/PD tools for methodology development. Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment Experience in design automation using TCL/Perl/Python. Familiar with digital flow design implementation RTL to GDS ICC, Innovous , PT/Tempus Familiar with process technology enablementCircuit simulations using Hspice/FineSim, Monte Carlo. Education B.Tech or MTech/MS in Electrical/Electronics/Microelectronics/VLSI. Preferred Qualification/Skills 5 - 10 years of experience in STA/Timing Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling Hands-on experience with STA tools - Prime-time, Tempus Have experience in driving timing convergence at Chip-level and Hard-Macro level In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling, Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus) Knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation. Proficient is scripting languages – TCL, Perl, Awk Basic knowledge of device physics

Candidate should be exeprinecd in process development in R&D in API synthesis Candidate with the exeprience of handelling Photo reactor will be prefered . Experience in Vitamin synthesis will be prefered

Elevate Your Impact Through Innovation and Learning: Evalueserve is a global leader in delivering innovative and sustainable solutions to a diverse range of clients, including over 30% of Fortune 500 companies. With presence in more than 45 countries across five continents, we excel in leveraging state-of-the-art technology, artificial intelligence, and unparalleled subject matter expertise to elevate our clients' business impact and strategic decision-making. We have 4,500+ talented professionals operating across 45 countries, including India, China, Chile, Romania, the US, and Canada. Our global network also extends to emerging markets such as Colombia, the Middle East, and the rest of Asia-Pacific. Recognized by Great Place to Work® in India, Chile, Romania, the US, and the UK in 2022, we offer a dynamic, growth-oriented, and open culture that prioritizes flexible work-life balance, diverse and inclusive teams, and equal opportunities for all. About Insights & Advisory (IA): Our Insights and Advisory team plays a crucial role in providing strategic guidance and datadriven insights to organizations. By analyzing market trends, consumer behavior, and business data, our team helps decision-makers make informed choices that can positively impact their organization's performance and bottom line. We work across diverse industries and sectors like Technology, Industrials, Energy, Chemicals, Life Sciences and Logistics, including market research, strategy, sales and marketing, R&D, and more. What you will be doing at Evalueserve: • Pharma Business research and Strategy Consulting support: Define problem statement and initial hypothesis; designing an optimal research approach with a mix of research techniques (e.g., primary/secondary/basic modeling) • Should be able to structure and present data and results using relevant frameworks • Ability to arrive at key messages/highlights addressing key objectives as summary of results ready for Executive Leadership consumption • Presenting results of the research to the client and handling client queries • Active participation & contribution in team discussions on project specific areas What we’re looking for: • Proven experience in strategy consulting and advisory within the pharmaceutical and biotech sectors, with a strong track record across key project types including opportunity assessment, competitive benchmarking, portfolio optimization, M&A due diligence, go-tomarket planning, and go/no-go decision frameworks. • Deep expertise in primary market research (both qualitative and quantitative), with the ability to apply advanced analytical models and strategic frameworks for data synthesis, trend identification, and triangulation of insights. • Demonstrated ability to quickly grasp client objectives and deliver high-impact solutions independently or as part of cross-functional teams, ensuring timely and high-quality execution • Skilled in developing strategic reports and executive-level presentations, delivering actionable insights and clear recommendations tailored for senior leadership and C-suite stakeholders. • Strong working knowledge of key pharma and medical data sources, including public databases (e.g., ClinicalTrials.gov, PubMed, FDA, EMA) and commercial platforms (e.g., Citeline, EvaluatePharma, PharmaTell). • Analytical and growth-oriented mindset, with a proactive approach to problem-solving and a commitment to delivering value-driven outcomes. • Excellent written and verbal communication skills, with the ability to convey complex ideas clearly and persuasively. • Strong interpersonal and collaboration skills, with a focus on active listening, stakeholder engagement, and team synergy. • Highly organized and time-conscious, with a consistent ability to manage multiple priorities and meet deadlines effectively. • Proactive contributor to organizational goals, with a keen interest in driving innovation and continuous improvement. • Proficient in MS Office Suite, particularly PowerPoint and Excel, with strong capabilities in data visualization, report writing, and presentation development • M.Tech./ M.Pharm/ B.Pharm/ B.Tech (Biotech)/B.E(Biotech)/ MBA • 6+ years of relevant experience in business research, in Pharmaceutical/ Life Sciences Consulting Organization Disclaimer: The following job description serves as an informative reference for the tasks you may be required to perform. However, it does not constitute an integral component of your employment agreement and is subject to periodic modifications to align with evolving circumstances Interested candidate can apply with their updated resume at aakanksha.pandey1@evalueserve.com

Role & responsibilities Perform lab experiments as per experiments planning in consultation with senior Write the lab note book properly at time of performing experiment Discuss the experiment observation with senior Wear proper PPE while handling chemicals and performing experiments Submit the sample to analytical as per experiment requirement and planning Collect the test report from analytical lab Maintain the project documents and file properly Maintain the lab chemicals as per hazards and compatibility data, study the MSDS sheet Maintain the raw materials, solvents stock and store it properly Maintain the lab glassware and stock Clean and maintain work place area

Research Associate Candidate should be experienced in process development in R&D in API synthesis Technology transfer, scale-up and troubleshooting of Lab developed process at Pilot and Commercial level. To carry experimental work for development / improvement of the products assigned. To carry out any job assigned by immediate supervisor / HOD Analytical Associate Well conversant with operating, handling and troubleshooting in HPLC, GC To maintain analytical records as per IMS. Co-ordinate with ADL dept. / Q.C dept. for method development activity. Development or improvement of methods for the assigned project Desired Profile: M.Sc. - Organic Chemistry/Analytical Chemistry Experience: 02 - 07 years Must be having experience in API

Research Associate Candidate should be experienced in process development in R&D in API synthesis Technology transfer, scale-up and troubleshooting of Lab developed process at Pilot and Commercial level. To carry experimental work for development / improvement of the products assigned. To carry out any job assigned by immediate supervisor / HOD Analytical Associate Well conversant with operating, handling and troubleshooting in HPLC, GC To maintain analytical records as per IMS. Co-ordinate with ADL dept. / Q.C dept. for method development activity. Development or improvement of methods for the assigned project Desired Profile: M.Sc. - Organic Chemistry/Analytical Chemistry Experience: 02 - 07 years Must be having experience in API

Jubilant Biosys is looking for Research Associate - Discovery Chemistry - Bengaluru location Experience: 3-5 Years Qualification: M.Sc. (Organic/ General/ Industrial Chemistry) M. Pharm (Medicinal Chemistry ) Design and plan synthetic routes for target molecules. Execute multi-step organic synthesis reactions, handling milligram to gram scale reactions. Characterize organic compounds using spectroscopic and related techniques. Perform literature searches using scientific databases (e.g., SciFinder). Solve synthetic challenges and troubleshoot issues. Maintain accurate records, including electronic laboratory notebooks (eLNB) and data integrity.

Walk-In Drive For API Research & Development(R&D)- Venue Details : MSN Laboratories Pvt. Ltd, R&D Centre, Pashamylaram (V), Patancheru (M), Sangareddy (D.t), Telangana on Friday 27-06-2025 . Department : API R&D Designation : Executive / Sr. Executive Experience : 1- 7 Years Qualification : M.Sc. Organic Chemistry Work Location : MSN R&D Center, Pashamylaram, Hyderabad Work Location : MSN R&D Center, Pashamylaram, Hyderabad Interview Venue Details : Venue Details : MSN Laboratories Pvt. Ltd, R&D Centre, Pashamylaram (V), Patancheru (M), Sangareddy (D.t), Telangana on Friday 27-06-2025 .

About: At HOTCULT, we are committed to being the authority on South Indian pop culture and consumerism, helping brands connect with this diverse and vibrant audience. We believe in shaping a compelling brand narrative that inspires and educates. As we continue to grow, we are looking for a dynamic Planning & Strategy Manager to join our team. Position Overview - As a Strategy & Brand Planner, you will play a pivotal role in shaping and executing effective brand and communication strategies. You will conduct in-depth research, develop strategic recommendations, and collaborate with internal teams and clients to drive impactful advertising and branding initiatives. Location - Hyderabad. Work type - Work from Office Key Responsibilities Research & Analysis: Conduct primary and secondary research to gather insights on market trends, consumer behavior, and competitive landscapes. Commission and oversee external qualitative and quantitative research. Analyze sales data and market trends to inform strategic decisions and recommendations. Strategic Planning & Development Develop and present comprehensive strategic plans that align with client objectives and market opportunities. Create detailed creative briefs to guide the internal creative team and ensure alignment with strategic goals. Develop positioning recommendations, define brand elements, and establish the brand tone. Client & Internal Collaboration Lead brand workshops and training sessions for client teams to co-create effective communication solutions. Present findings and strategic recommendations to clients, demonstrating a deep understanding of their business, market, and brand. Conduct brainstorming sessions with internal stakeholders to generate innovative ideas and solutions. Campaign Management & Evaluation Oversee and evaluate the effectiveness of campaigns, using insights to refine and enhance strategies. Develop and implement strategies to address business challenges and capitalize on market opportunities. Leadership & Training Lead and manage the local planning team, fostering a collaborative and high-performance environment. Represent the agency at training sessions and industry events, including college outreach programs. Business Development Assist in pitching for new business opportunities, leveraging strategic insights to win new clients. Trend Analysis & Innovation: Stay current with cultural and social trends, and anticipate future developments to ensure forward-thinking strategies. Utilize big-picture thinking, storytelling, and synthesis to set and achieve strategic goals. Requirement - 4-6 years experience in strategic planning, brand development, and market research. Strong ability to analyze data and translate insights into actionable strategies. Excellent communication skills with a track record of successful client presentations and internal collaboration. Leadership experience, with the ability to manage and inspire a team. Familiarity with statistics, research analysis, and marketing strategy. Forward-thinking mindset with a keen understanding of emerging trends and consumer attitudes. Experience in developing creative briefs and working with creative teams. Experience in conducting brand workshops and training sessions. Strong grasp of South Indian cultural nuances and an understanding of cultural codes to craft more impactful and relevant pitches. Proficiency in using criteria development tools and synthesizing research findings into strategic recommendations. Skills: creativity,strategic planning,brand activation,client collaboration,communication,brand strategy,market research,statistics,research,cultural analysis,data analysis,leadership,brand awareness,brand development

Be the First to Apply Job Description Business: PPL Digwal Department: PTS Location: Digwal Job Overview: To perform AR&D actives as per GMP & Safety Travel Requirements: NA Reporting Structure Reports to Research Scientist - AR&D (Service) Key Stakeholders Internal: QC, QA, SCM & Safety External: NA Experience 4-8 Year Experience in manufacturing (API) as per Pharma Manufacturing GMP requirements. Responsibilities for Internal Candidates Key Roles & Responsibilities Capable to handle independent projects Analytical testing support to PDG synthetic group. Coordinate with QA regarding method transfer, CCF and investigation reports. Experience of handling of HPLC, GC, Potentiometer, Polarimeter instruments. API Stability knowledge. Capable to handle analytical method development, Implementation, Validation as per requirement. Should have experience of Analytical method transfer to QC. Experience of making documents like method transfer protocol & report, method validation protocol & report, method development report, specification, standard test procedure etc. Should aware about GLP practices and 21 CFR part-11. Keep the work area clean and the laboratory under controlled temperature. Calibrate the instruments according to the master calibration schedule and follow GLP and SOPs. Understand the safety and environmental aspect. Maintain the reagents and standardize the volumetric solutions as per schedule. Maintain the laboratory journals and instrument log books online. Ensure compliance to Hazardous waste and chemical management. Qualifications Qualification : M.Sc (Analytical Chemistry), (Chemistry) & (Organic Chemistry) Required Skills RCI study, Synthesis About Us In the three decades of its existence, Piramal Group has pursued a twin strategy of both organic and inorganic growth. Driven by its core values, Piramal Group steadfastly pursues inclusive growth, while adhering to ethical and values-driven practices. Equal employment opportunity Piramal Group is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, ethnicity, religion, color, national origin, gender (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetics, or other applicable legally protected characteristics. We base our employment decisions on merit considering qualifications, skills, performance, and achievements. We endeavor to ensure that all applicants and employees receive equal opportunity in personnel matters, including recruitment, selection, training, placement, promotion, demotion, compensation and benefits, transfers, terminations, and working conditions, including reasonable accommodation for qualified individuals with disabilities as well as individuals with needs related to their religious observance or practice. About The Team Piramal Pharma Solutions (PPS) is a Contract Development and Manufacturing Organization (CDMO) offering end-to-end development and manufacturing solutions across the drug life cycle. We serve our customers through a globally integrated network of facilities in North America, Europe, and Asia. This enables us to offer a comprehensive range of services including drug discovery solutions, process & pharmaceutical development services, clinical trial supplies, commercial supply of APIs, and finished dosage forms. We also offer specialized services such as the development and manufacture of highly potent APIs, antibody-drug conjugations, sterile fill/finish, peptide products & services, and potent solid oral drug products. PPS also offers development and manufacturing services for biologics including vaccines, gene therapies, and monoclonal antibodies, made possible through Piramal Pharma Limited’s investment in Yapan Bio Private Limited. Our track record as a trusted service provider with experience across varied technologies makes us a partner of choice for innovators and generic companies worldwide. Job Info Job Identification 8901 Job Category R & D Posting Date 06/24/2025, 12:04 PM Degree Level Master's Degree Job Schedule Full time Locations Piramal Enterprises Limited. Factory: Digwal, Medak, Telangana, 502321, IN

Job Title: Voice Processing Specialist Location: Remote /Jaipur Job Type: Full-time / Contract Experience: 3+ years expertise in voice cloning, transformation, and synthesis technologies Job Summary We are seeking a talented and motivated Voice Processing Specialist to join our team and lead the development of innovative voice technologies. The ideal candidate will have a deep understanding of speech synthesis, voice cloning, and transformation techniques. You will play a critical role in designing, implementing, and deploying state-of-the-art voice models that enhance naturalness, personalization, and flexibility of speech in AI-powered applications. This role is perfect for someone passionate about advancing human-computer voice interaction and creating lifelike, adaptive voice systems. Key Responsibilities Design, develop, and optimize advanced deep learning models for voice cloning, text-to-speech (TTS), voice conversion, and real-time voice transformation. Implement speaker embedding and voice identity preservation techniques to support accurate and high-fidelity voice replication. Work with large-scale and diverse audio datasets, including preprocessing, segmentation, normalization, and data augmentation to improve model generalization and robustness. Collaborate closely with data scientists, ML engineers, and product teams to integrate developed voice models into production pipelines. Fine-tune neural vocoders and synthesis architectures for better voice naturalness and emotional range. Stay current with the latest advancements in speech processing, AI voice synthesis, and deep generative models through academic literature and open-source projects. Contribute to the development of tools and APIs for deploying models on cloud and edge environments with high efficiency and low latency. Required Skills Strong understanding of speech signal processing, speech synthesis, and automatic speech recognition (ASR) systems. Hands-on experience with voice cloning frameworks such as Descript Overdub, Coqui TTS, SV2TTS, Tacotron, FastSpeech, or similar. Proficiency in Python and deep learning frameworks like PyTorch or TensorFlow. Experience working with speech libraries and toolkits such as ESPnet, Kaldi, Librosa, or SpeechBrain. In-depth knowledge of mel spectrograms, vocoder architectures (e.g., WaveNet, HiFi-GAN, WaveGlow), and their role in speech synthesis. Familiarity with REST APIs, model deployment, and cloud-based inference systems using platforms like AWS, Azure, or GCP. Ability to optimize models for performance in real-time or low-latency environments. Preferred Qualifications Experience in real-time voice transformation, including pitch shifting, timing modification, or emotion modulation. Exposure to emotion-aware speech synthesis, multilingual voice models, or prosody modeling. Design, develop, and optimize advanced deep learning models for voice cloning, text-to-speech (TTS), voice conversion, and real-time voice transformation Background in audio DSP (Digital Signal Processing) and speech analysis techniques. Previous contributions to open-source speech AI projects or publications in relevant domains. Why Join Us You will be part of a fast-moving, collaborative team working at the forefront of voice AI innovation. This role offers the opportunity to make a significant impact on products that reach millions of users, helping to shape the future of interactive voice experiences. Skills: automatic speech recognition (asr),vocoder architectures,voice cloning,voice processing,data,real-time voice transformation,speech synthesis,pytorch,tensorflow,voice conversion,speech signal processing,audio dsp,rest apis,python,cloud deployment,transformation,mel spectrograms,deep learning

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Design for Testability (DFT) Good to have skills : NAMinimum 7.5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your day will involve overseeing the application development process, coordinating with team members, and ensuring project milestones are met. Roles & Responsibilities:Bachelors degree in computer science, Electronics Engineering or related fields and 6+ years of related professional experience.Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at-least couple of DesignsCore DFT skills considered crucial for this position should include some of the following Scan compression and insertion, Memory BIST, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate-level verification, silicon debugUnderstanding of DFT Flows and Methodologies and Experience with Cadence/Mentor/Synopsys Tool set (Genus,Modus,NCSim / DC,Tessent,Spyglass/Tmax)Experience coding in Verilog RTL, and scripting language like TCL, and/or PerlProficient in Unix/Linux environmentsStrong fundamentals in Digital Circuit Design and Logic Design are required. Professional & Technical Skills: - Must To Have Skills: Proficiency in Design for Testability (DFT)- Strong understanding of software development methodologies- Experience in leading and managing software development projects- Knowledge of technologies and tools used in software development- Excellent communication and interpersonal skills Additional Information:- The candidate should have a minimum of 5 years of experience in Design for Testability (DFT)- This position is based at our Chennai office- A 15 years full time education is required Qualification 15 years full time education