2285 Synthesis Jobs - Page 46

Position Overview: The Lead, Data Analyst & Evaluator shall be part of RM&E Unit will be based at New Delhi, India Country Office (INCO). The Lead, Data Analyst & Evaluator will report to the Manager, INCO RM&E. He/she will play a key role in supporting strengthening government-led monitoring and evaluation systems. The position is responsible for providing strategic and technical support to the state-level RM&E team members in strengthening data systems, assessments, and evidence-informed decision-making. Duties and Responsibilities: Provide strategic guidance to the state RM&E team in strengthening government-led monitoring systems, ensuring alignment with both organizational frameworks and evolving state priorities. Lead the refinement of program log frames, indicators, and results frameworks, ensuring coherence with state-level implementation strategies and broader organizational goals. Review and offer technical oversight on the design and implementation of government-led assessments, including support in tool development, sampling methodologies, and analytical frameworks. Review and provide quality assurance for monitoring tools, data sets, dashboards, and reports generated by the state RM&E team, ensuring relevance, accuracy, and utility for decision-making. Mentor and build the technical and analytical capacities of state RM&E team members, promoting a culture of continuous learning, critical reflection, and high-quality delivery. Lead efforts to ensure data quality through regular checks, validation exercises, and field support visits. Support the enhancement of existing government digital monitoring systems, dashboards, and real-time data visualization tools. Guide the planning and facilitation of review meetings, reflection sessions, and evidence-informed planning workshops. Closely collaborate with state program, operations, and technical teams to ensure that monitoring and evaluation efforts are grounded in implementation realities. Represent the RM&E function in strategic planning, review meetings, and support coordination with state- and district-level government counterparts, donors, and technical partners. Lead the consolidation, synthesis, and presentation of key RM&E findings to internal leadership, donors, and government partners, highlighting programmatic learnings and policy implications. Demonstrated ability to work both independently and in teams. Develop network with Research organizations and Government and support Government to meet their research and evaluation needs. Undertake additional responsibilities assigned by the Manager-RM&E, contributing to cross-functional initiatives and strategic priorities of the organization. Qualifications: Required: Postgraduate degree in Economics, Public Policy, Education, Development Studies, Statistics or related field. A minimum of eight years (08) of relevant experience in monitoring & evaluation, government system strengthening, and/or program implementation. Prior experience in Foundational Literacy and Numeracy (FLN) programs is highly desirable. Strong conceptual understanding and hands-on experience in data analysis, systems thinking, monitoring frameworks, and assessment design. Proven experience working with government departments, especially in the education sector, with a strong understanding of public education systems. Proficiency in tools such as MS Excel, Power BI, Survey CTO; experience with statistical analysis tools like STATA, is an added advantage. Ability to manage complex data systems, draw insights from evidence, and translate findings into actionable recommendations for program and policy decisions. Strong writing, articulation, and documentation skills with the ability to produce high-quality reports, presentations, briefs, and knowledge products for diverse stakeholders. Ability to multitask effectively, manage multiple priorities and meet deadlines in a fast-paced environment. Strong verbal communication and presentation skills, with the ability to effectively convey complex information to both technical and non-technical audiences. Ability and desire to travel to field locations. Prior experience in a fast-paced, growth-oriented global or regional organization Proven track record of juggling multiple priorities simultaneously and taking initiatives. Compensation: Room to Read offers a competitive salary with excellent benefits. Benefits include thirteenth month bonus, health insurance and a retirement plan. The non-monetary compensation includes a unique opportunity to be part of an innovative, meaningful, and rapidly growing organization that is changing transforming the lives of millions of children in developing countries on literacy and gender equality in education. Room to Read is a child-safe organization; all personnel are expected to adhere to Room to Read’s Child Protection Policy and Child Protection Code of Conduct. Due to the high volume of applicant responses, not all applicants may receive a response from Room to Read. Room to Read is an equal opportunity employer committed to identifying and developing the skills and leadership of people from diverse backgrounds. We always encourage women to apply.

Increasing digitalization and flexibility of production processes presents outstanding potential. In Digital Industries, we enable our customers to unlock their full potential and drive digital transformation with a unique portfolio of automation and digitalization technologies. From hardware to software to services, we’ve got quite a lot to offer. How about you? Looking for Siemens EDA ambassadors We are passionate about innovations that mean real progress, and we are curious about technologies that still need to be developed. Do you want to use curiosity, passion, and creativity to make the lives of millions of people easier and better? Join us – whichever path you take, we’re looking forward to seeing your point of view! As an integral part of the R&D team, you will contribute to Siemens’ success by crafting state of the art power analysis and optimization solutions. This is your role Analyzer team is working on the development of front end (Analyzer and Elaborator) of different Mentor Compilers. This module takes care of various HDL languages like Verilog, System Verilog and VHDL. As a member of the team, one will be working primarily on C++ and flex/bison and will be responsible for the design, development modify, and implementation of various pieces of the overall software with focus on surpassing customer expectations, on achieving high quality and timely delivery. Responsible for ensuring the overall functional quality of the released product on all required platforms and mechanism. Ability to understand complex products, solutions, and problems. Builds, documents, and executes software designs which may involve complicated workflows or multiple product areas. We are not looking for superheroes, just super minds We are seeking a Graduate / Post Graduate (Bachelors/Masters) in EEE) / ECE/Computer Science (CS) from top reputed Engineering colleges with significant experience in software development with 1-4 Years of experience. We value sound understanding of C/C++ languages, design patterns along with data structure and algorithms will be key to development of software. Experience in parallel algorithms, job distribution. Experience in development of Front End EDA software is a plus! Proficiency in HDL languages – Verilog/VHDL/System Verilog - low power aware synthesis and power formats - UPF/CPF – will supplemental. We are looking for knowledge of flex/bison and understanding of gate level digital logic design. Good analytical, abstraction and interpersonal skills will help in crafting bigger and balanced solutions for complex systems. Ability to work individually and as a team player will help in crafting good solutions and should be able to guide other towards project completion. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status.

Role & responsibilities Knowledge about chemical reaction and chemical compounds. Awareness about R&D lab Instruments and Glassware. Setting up lab experiment assembly like reaction, distillation, vacuum distillation, separation, etc. Ensuring experiments are carried out safely and carrying out risk assessments. Maintain complete records of experimental results and analysing data of experiments. Optimize reaction conditions and troubleshoot technical issues. Ensure consistency and repeatability of process to get acceptable yield and quality. Preferred candidate profile M.Sc. in Chemistry having 1-6 Years Experience in R&D Synthesis having Chemical and Pharmaceutical Industry having problem-solving and decision-making skills, Strong analytical and organizational skills . Additional Information: At Avid Organics, we believe that we can achieve our mission to enhance value creation for our stakeholders only through the quality and commitment of our people. We continuously strive to unleash the potential of each individual. We leverage human capital for competitiveness by nurturing knowledge, entrepreneurship, and creativity. These strengths help us compete successfully in a global business environment and exploit emerging opportunities. We reward the will to succeed and the desire to compete with the best in the world. Our employees are intellectually stimulated and given the freedom to make their own decisions, driving our growth through innovation and experimentation. Apply Now! :- hr@avidorganics.net Visit our website apply us at https://www.avidorganics.net

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Physical design for high-performance designs going into industry leading CPU and AI/ML architecture. The person coming into this role will be involved in all implementation aspects from synthesis to tapeout for various IPs on the chip. The work is done alongside a group of highly experienced engineers across various domains of the AI chip. This role is hybrid, based out of Bangalore. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Responsibilities Define PD requirements by working closely with the front-end team, understand the chip architecture and drive physical aspects early in the design cycle Physical design tasks including such as synthesis, PnR, timing closure, area improvement, floorplanning, clocking, I/O planning and power optimization Discussions with 3rd party IP providers, foundry partners and design services End to end tasks from flow development to sign-off Deploy innovative techniques for improving power, performance and area of the design, drive experiments with RTL, and evaluate synthesis, timing and power results Experience & Qualifications BS/MS/PhD in EE/ECE/CE/CS Hands-on experience with synthesis, block and chip level implementation with industry standard PnR flows and tools Strong experience in SOC/ASIC/GPU/CPU design flows on taped out designs, expertise in timing closure at block/chip levels and ECO flows Experience with back-end design tools such as Primetime, Innovus, RedHawk, etc. Knowledge of low-power design flows such as power gating, multi-Vt and voltage scaling Strong programming skills in Tcl/Perl/Shell/Python Excellent understanding of logic design fundamentals and gate/transistor level implementation Exposure to DFT is an asset Prior experience working on high performance technology nodes and understanding of deep sub-micron design problems/solutions Strong problem solving and debug skills across various levels of design hierarchies Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government. As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and supporting documentation will be required and considered as a condition of employment. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.

Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values ; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await! Job Description: You will be working with our DFT team from Hyderabad/Work from Home as required to develop DFT tests. These tests are intended to catch manufacturing defects in targeted IPs inside FPGA/SoC. In this role you will have an opportunity to understand in depth FPGA/SoC silicon architectures, ATPG, MBIST Verification at full chip level, DFT/Testability hooks in Silicon, methods and principles to develop ATPG/Functional test vectors, simulate, debug and generate patterns for production tests. You will work closely with Architects, Design engineers, Verification engineers and Software engineers across the globe to ensure FPGA division deploys new products with the highest quality and shortest time to market. Skills will be developed to work on multiple projects supporting key functions within the organization. Good communication and presentation skills are required. Requirements/Qualifications: Understanding basics of DFT structures (OCC, SSN, SIB, WBRs, compression engine), ATPG(Intest/Extest) , MBIST, Boundary Scan (IEEE 1149.1) Tap Controller, Generating, verifying and debugging test patterns at block and chip-level retargeting to test the designs and firmware for new FPGA families. Improving, extending and porting existing manufacturing test designs to all FPGA family members. Test specification, plan, and documentation Hands on experience with industry standard ATPG tools, MBIST, pattern simulation and debugging skills at block and chip-level. Hands-on experience with Verilog behavioral RTL and Gate level netlist. Comfortable with Unix, Perl and/or Shell scripting and familiar with Revision Control (CVS, SVN, …) Strong analytical and problem-solving skills Excellent communication, documentation and presentation skills. Must have strong self-learning ability and enjoy working in teams spread across globe. Good programming skill/Firmware development skills with C, C++/assembly will be a big plus. Exposure to ASIC/FPGA design flow and methodology is a plus (HDL, synthesis, static timing analysis, constraining, Place & Route) BS or MS in EE with 5 to 6 years of experience of working in DFT Travel Time: 0% - 25% To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

Date: 25 Jun 2025 Location: Bangalore, KA, IN, 560099 Custom Field 1: Discovery Services Attend training on environment, health, and safety (EHS) measures. Follow environment, health, and safety (EHS) requirements always in the workplace ensuring individual and lab/plant safety Perform synthetic chemistry reactions, reaction workups, purification of the compounds by column chromatography, crystallization, re-crystallization techniques, preparative TLC and operating lab equipments. Ensure that the samples generated during synthesis are given for analysis and record subsequent results obtained and update the supervisor / group leader on the progress of synthesis and ensure samples are packed appropriately for shipment. Record the observations of experiment/reaction, results, utilization of resources and other activities related to the reaction in the laboratory or e-notebook following guidelines and in timely manner and ensure that the same is handled safely and confidentially. Ensure that the instrument / equipment is calibrated, undergone preventive maintenance and are kept clean before use and in case of any breakdown, report to maintenance immediately. Ensure that they know the MSDS of the chemicals they are handling and aware of emergency response procedures in case of accidental spillage, leakage or fire and ensure proper waste segregation as per EHS norms.

Let’s be #BrilliantTogether ISS Market Intelligence is growing! We are actively looking for an Research Lead - Financial Services to Join the Mumbai Team (Goregaon East). Overview: ISS Market Intelligence Research forms part of the Market Intelligence (MI) division of ISS STOXX. ISS MI provides critical data and insights to global asset managers, insurance companies and distributors, to help make informed, strategic decisions to manage and grow their business. Through its combination of proprietary and integrated datasets, in-depth global research and trusted executive engagement, ISS MI delivers solutions for market sizing, competitor benchmarking, product strategy and opportunity identification across a wide range of financial products including funds, annuities, insurance, mortgages, and other instruments. The ISS MI suite of solutions encompasses the industry-leading data platforms: Simfund, BrightScope, Local Market Share, and Financial Clarity; as well a full collection of global research and analytics services, including Investor Economics, Market Metrics, and Plan for Life. The mission of ISS MI Research team is to empower our clients to succeed and grow in an intensely competitive marketplace. We achieve this by harnessing the power of MI’s data and intellectual capital to create unique market insights and competitive intelligence to help our clients make well-informed decisions. Building on our deep tradition of more than 40 years of observing the asset and wealth management businesses, our Research team generates thought leadership content for a variety of ongoing and ad hoc research publications, consumed by ISS MI clients around the world. Our Mumbai Research Team ISS MI Research is expanding its research team in Mumbai located within our existing ISS premises. The team forms an integral part of our global, as well as country-specific—US, Canadian and Australian—research operations, with exciting opportunities to contribute to growing our global research and analytical insights capital around the world. The position of Research Lead - Financial Services, represents an exciting opportunity to shape and make a significant contribution to the global Product & Distribution research teams of ISS MI. Responsibilities: The position is suited to highly motivated professionals able to deal with the pressures of managing financial services research properties primarily focused on, but not limited to, wealth management and life insurance. The Ongoing Research Responsibilities Of The Position Feed Into a Wider Range Of Regular Subscription-based Research Publications As Well As Making The Incumbent a Key Support For One-time Consulting And Research Projects In Their Areas Of Domain Expertise And Coverage. These Responsibilities Involve: Managing the contribution of our resident analysts and associates in Mumbai, as well as in other MI geographies, as well as ensuring the effective collaboration with North American and EMEA teams either leading or involved in supporting research function In the US, Canada, Australia and EMEA. Ultimate responsibility for maintaining, refining and introducing new data sets and metrics in the research coverage area. Engaging with ISS MI's many research participants to both build knowledge and expertise and Managing critical client servicing efforts across a broad spectrum of ISS MI subscribers. The incumbent will have ultimate responsibility for the timely delivery of the ongoing research publications, as well as providing direction, supervision and mentoring of research team members. Successful candidate will have an opportunity to conceptualize and lead teams to create original research and new data sets for ISS MI. Additionally, managing long-term and emerging relationships developed with the many businesses that are engaged with ISS MI as clients, prospects and research participants, is a key responsibility. Specifically, at this level within ISS MI, the incumbent will be expected to: Have an understanding of personal financial wealth, the wealth market product set (including banking and life insurance) and wealth distribution models in North America and Asia. Familiarity with the Australian and European wealth markets a definite plus. Conceptualize, propose and execute research designed to inform clients and the industry on emerging trends in the area of domain expertise. Engage with industry participants, establish and maintain key relationships at senior levels and ensure the research team is able to arrange and run confidential research interviews and ongoing discussions with all key contacts. Develop and provide comprehensive and supported insights from the research and communicate them to internal and external audiences in verbal, written and digital presentation formats. Manage, support and mentor research team members’ contributions in respect to those communication efforts. Coordinate/manage analytics and thought leadership support for research and consulting engagements in the area of research focus. Demonstrate care, precision, diligence and thoughtfulness in the management and execution of research analytics, report production and verification processes. Coordinate team members’ workflow, define and monitor deliverables, and take responsibility for delivering research and reports to production deadlines. Manage, and support the recruitment of analytical staff and lead the development and mentoring of analysts and associates on the incumbent's own team and beyond. Manage the relationship between the Research team and Data Operations and Development teams to ensure the integrity and quality of data onboarding, database mining and collaborate on specific projects and deliverables. ideate and propose new products, data sets and data refinements to the expansive data capital of ISS MI. Pro-actively share knowledge and understanding of industry developments across ISS MI, on a formal and informal basis Qualification: An Post graduate degree from a well-recognized university in economics, finance, commerce, business administration. Other disciplines such as mathematics, statistics or social sciences will be considered in combination with experience. A minimum 10-years’ experience in the retail financial services or wealth management industries including, but not limited to, specific distribution related businesses, asset management companies or life insurers. Professional experience with a global or a North American firm, and experience in collaboration as part of a global team a definite plus. Passion for developing and growing domain expertise and for disruptive thinking. Very strong conceptualization, synthesis, communication and writing skills Ability to work under pressure to meet deadlines and conflicting demands. Strong interpersonal and people management skills—experience managing a team a definite asset. Superior organizational skills necessary to manage analysis of a diverse array of business line data. Excellent problem-solving, conflict resolution, negotiation and decision-making skills Must be proficient in standard office software, (MS Office Excel, Word, PowerPoint, Access). Application Instructions: Your application must include (i) a resume; (ii) a cover letter stating your fit in comparison to the required qualifications above. #MIDSENIOR #MI What You Can Expect From Us At ISS STOXX, our people are our driving force. We are committed to building a culture that values diverse skills, perspectives, and experiences. We hire the best talent in our industry and empower them with the resources, support, and opportunities to grow—professionally and personally. Together, we foster an environment that fuels creativity, drives innovation, and shapes our future success. Let’s empower, collaborate, and inspire. Let’s be #BrilliantTogether. About ISS STOXX ISS STOXX GmbH is a leading provider of research and technology solutions for the financial market. Established in 1985, we offer top-notch benchmark and custom indices globally, helping clients identify investment opportunities and manage portfolio risks. Our services cover corporate governance, sustainability, cyber risk, and fund intelligence. Majority-owned by Deutsche Börse Group, ISS STOXX has over 3,400 professionals in 33 locations worldwide, serving around 6,400 clients, including institutional investors and companies focused on ESG, cyber, and governance risk. Clients trust our expertise to make informed decisions for their stakeholders' benefit. ISS Market Intelligence (ISS MI) is a leading provider of data, insights, and market engagement solutions to the global financial services industry. ISS MI empowers asset and wealth management firms, insurance companies, distributors, service providers, and technology firms to assess their target markets, identify and analyze the best opportunities within those markets, and execute on comprehensive go-to-market initiatives to grow their business. Clients benefit from our increasingly connected global platform that leverages a combination of proprietary data, powerful analytics, timely and relevant insights, in-depth research, as well as an extensive suite of industry-leading media brands that deliver unmatched market connectivity through news and editorial content, events, training, ratings, and awards. Visit our website: https://www.issgovernance.com View additional open roles: https://www.issgovernance.com/join-the-iss-team/ Institutional Shareholder Services (“ISS”) is committed to fostering, cultivating, and preserving a culture of diversity and inclusion. It is our policy to prohibit discrimination or harassment against any applicant or employee on the basis of race, color, ethnicity, creed, religion, sex, age, height, weight, citizenship status, national origin, social origin, sexual orientation, gender identity or gender expression, pregnancy status, marital status, familial status, mental or physical disability, veteran status, military service or status, genetic information, or any other characteristic protected by law (referred to as “protected status”). All activities including, but not limited to, recruiting and hiring, recruitment advertising, promotions, performance appraisals, training, job assignments, compensation, demotions, transfers, terminations (including layoffs), benefits, and other terms, conditions, and privileges of employment, are and will be administered on a non-discriminatory basis, consistent with all applicable federal, state, and local requirements.

Lead the architecture and RTL design of complex digital blocks and subsystems for ASICs or SoCs Develop RTL using Verilog/SystemVerilog to meet functional and performance specifications Review micro-architecture and provide design solutions optimized for power, performance, and area Work closely with the verification team to ensure thorough test coverage and efficient debugging Collaborate with synthesis, STA, and physical design teams for design closure

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary 12+ years of experience in SoC design Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. 12+ years of experience with a Bachelor's/ Master’s degree in Electrical/ Electronics engineering Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3064468

Position : Chief Manager/DGM - Vendor Development/Sourcing We're actively seeking a Chief Manager/DGM - Vendor Development/Sourcing to spearhead the commercialization of our innovative solutions. This is a critical role where you'll drive the transformation of scientific breakthroughs into commercial success. You'll be pivotal in establishing strong vendor partnerships and managing the entire commercialization journey – from R&D demonstration through to large-scale deployment. If you have a deep understanding of scaling complex technologies and a knack for driving market adoption, we encourage you to apply. What We're Looking For: Experience: You should have 15 - 20 years of experience in a similar capacity , demonstrating progressive leadership in vendor development and sourcing within a commercialization context. Specialized Expertise: Your work experience must be specifically in the commercialization of R&D technologies, catalysts, and products within the Petroleum, Oil & Gas sector. Scale-Up Mastery: We need someone with a proven track record in establishing and optimizing scale-up synthesis protocols. Market & Business Development Acumen: You must have demonstrated success in marketing, promotion, and business development for technical products and technologies. Production Exposure (Highly Preferred): Candidates with hands-on exposure to production environments in chemicals, catalysts, or petrochemicals will be given strong preference. Extensive Relevant Experience: We highly value candidates who bring a wealth of directly relevant experience to this specialized role. Your Key Responsibilities Will Include: Strategic Vendor Development: Identifying, developing, and nurturing crucial vendor relationships essential for the demonstration, scale-up, and commercialization of our R&D technologies and products. Scale-Up & Manufacturing Leadership: Leading and managing all facets of scale-up synthesis, outsourcing, and manufacturing processes with external vendors. Protocol Definition & Implementation: Establishing and meticulously defining detailed synthesis and operational protocols to ensure consistency, quality, and efficiency. Strategic Sourcing: Efficiently sourcing critical raw materials, specialized chemicals, and necessary equipment to support both R&D and commercialization efforts. Logistics & Documentation: Overseeing all required logistics and ensuring comprehensive documentation for smooth operations and regulatory compliance. In-House Facility Management: Managing the effective operation and optimization of our in-house scale-up facility. Product Validation: Implementing and supervising rigorous product testing procedures to ensure performance, reliability, and market readiness. Market Promotion: Actively promoting and marketing our R&D technologies and products to target customers and key stakeholders. Cross-Functional Liaison: Serving as the essential communication bridge between our R&D scientists and external customers/end-users, providing vital support during project execution and post-commissioning services.

Desired Profile : You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. Academic Credentials : MS or BS in Computer Engineering/ Computer Science with 5+ years working experience in ASIC RTL design. Key Responsibilities : 1. Develop micro-architecture and design for high-speed IO controller blocks based on architectural requirement 2. Conduct design reviews of designs in technical presentations to peers and management. 3. Develop RTL code for high-speed IO controller blocks in Verilog HDL and make sure functional correct and reusable for different configuration. 4. Oversees Synthesis and netlist delivery that meets timing, area and power bounding box. Assist physical design team on the floor-planning and timing closure. 5. Work with Design Verification team to ensure quality for architecture definition and design implementation. 6. Provide guidance and leadership to the team members. Preferred Experience : 1. Strong knowledge in computer architecture and interconnects. 2. Strong experience in high speed IO controller design (e.g. USB, PCIe, SATA, Thunderbolt). USB and/or Thunderbolt a strong plus. 3. Experience in full ASIC design cycle: requirements definition, architectural and micro-architectural specification, RTL, design verification, floor-planning, synthesis, timing closure, post-silicon validation. 4. Expert on Verilog RTL design and has experience of large digital ASIC project. 5. Familiar with front-end EDA tools and flows. 6. Familiar with Unix/Linux and scripts (tcl, perl, ruby and etc.) 7. Preferred candidates with valid work permit (Green Card / US Citizen / H1B)

About the company: We are an international healthcare consultancy providing value evidence strategy, generation, synthesis, and communication services and products to Life Sciences companies. Delivering these software products empowered by technological innovations has enabled us to become a trusted partner with our clients across the development and commercialization life cycle. We revolutionize the way Life Sciences companies make informed decisions and engage with key stakeholders through our cutting-edge software products. Our products integrate traditional and innovative analytical methods with a wide array of real-world data, encompassing genomic, medical records, claims, and patient-reported information. This powerful combination, facilitated by our software, enables Life Sciences companies to enhance their internal decision-making processes and effectively communicate with regulators, health technology assessment authorities, payers, the medical community, and patient organizations. Role Overview We’re hiring a QA Engineer with 4–6 years of experience to join our remote Software Engineering team. You’ll be responsible for writing and executing test cases, finding and documenting bugs, and contributing to both manual and automated testing. We work in Agile teams, and you’ll collaborate closely with developers, analysts, and product managers to ensure our software meets quality standards. If you have a solid foundation in QA, some hands-on automation experience, and clear communication skills—we’d love to talk. What we are looking for Essential Skills: QA & Testing Fundamentals Solid understanding of Software Development Life Cycle (SDLC) and Software Testing Life Cycle (STLC) Experience with various testing types: functional, regression, smoke, sanity, integration, and user acceptance testing Knowledge of test case design techniques like boundary value analysis, equivalence partitioning, and decision tables Comfortable navigating defect lifecycles and working with tools like JIRA or Bugzilla Manual Testing Excellence Writing clear, comprehensive test cases comes naturally to you Experience with exploratory testing and problem discovery Cross-browser and cross-device testing experience Familiarity with test case management tools Automation Skills Hands-on experience with at least one test automation tool, particularly Selenium WebDriver Comfortable working in Java, Python, or JavaScript Ability to write automation scripts independently Understanding of Page Object Model (POM) design pattern Communication & Collaboration Clear communication skills, both written and verbal Comfortable working alongside developers, business analysts, and project managers Strong analytical thinking and creative problem-solving approach Agile Experience Experience working within Agile or Scrum teams Familiarity with sprint planning, daily standups, and retrospectives Understanding of how testing fits into iterative development cycles Nice to Have: AI/ML in Testing Experience with AI-powered testing tools like Testim, Mabl, Katalon, or GitHub Copilot Understanding of how AI helps with flaky test detection or test case generation Advanced Automation Exposure to modern frameworks like Cypress, Playwright, or Robot Framework Knowledge of BDD tools such as Cucumber or SpecFlow Experience with version control systems like Git, GitHub, or GitLab Understanding of CI/CD pipelines through tools like Jenkins or GitLab CI

Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await! Job Description You will be working with our DFT team from Hyderabad/Work from Home as required to develop DFT tests. These tests are intended to catch manufacturing defects in targeted IPs inside FPGA/SoC. In this role you will have an opportunity to understand in depth FPGA/SoC silicon architectures, ATPG, MBIST Verification at full chip level, DFT/Testability hooks in Silicon, methods and principles to develop ATPG/Functional test vectors, simulate, debug and generate patterns for production tests. You will work closely with Architects, Design engineers, Verification engineers and Software engineers across the globe to ensure FPGA division deploys new products with the highest quality and shortest time to market. Skills will be developed to work on multiple projects supporting key functions within the organization. Good communication and presentation skills are required. Requirements/Qualifications Understanding basics of DFT structures (OCC, SSN, SIB, WBRs, compression engine), ATPG(Intest/Extest) , MBIST, Boundary Scan (IEEE 1149.1) Tap Controller, Generating, verifying and debugging test patterns at block and chip-level retargeting to test the designs and firmware for new FPGA families. Improving, extending and porting existing manufacturing test designs to all FPGA family members. Test specification, plan, and documentation Hands on experience with industry standard ATPG tools, MBIST, pattern simulation and debugging skills at block and chip-level. Hands-on experience with Verilog behavioral RTL and Gate level netlist. Comfortable with Unix, Perl and/or Shell scripting and familiar with Revision Control (CVS, SVN, …) Strong analytical and problem-solving skills Excellent communication, documentation and presentation skills. Must have strong self-learning ability and enjoy working in teams spread across globe. Good programming skill/Firmware development skills with C, C++/assembly will be a big plus. Exposure to ASIC/FPGA design flow and methodology is a plus (HDL, synthesis, static timing analysis, constraining, Place & Route) BS or MS in EE with 5 to 6 years of experience of working in DFT Travel Time 0% - 25% To all recruitment agencies : Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

Design key digital blocks such as data path IPs(DSP functions, accelrators) in Verilog/ System Verilog with built-in configurability to allow Power/ Performance/ Area tradeoffs Develop strong understanding of ARM processor cores & subsystems (M series associated infrastructure such as caches, interconnect fabric, DMA, MMU, Coresight Debug & Trace, TZC, SMPU, SPU) and their integration requirements Experience of AFE based projects is an add on. Package Digital IP for seamless integration into design flow at different stages - RTL/ constraints/ CDC waivers, timing wavers, DFT DRCs and waivers, software programming sequence etc. Consolidate & curate digital IP for SPI/ I2C/ UART/ JTAG and other slow serial interfaces & peripherals Develop User Guides for RTL Integration, Synthesis, DFT, PnR, Programming Sequence, characterization etc Minimum Qualifications Minimum B.E. / B.Tech degree in Electrical/Electronics/Computer science 4 - 8 years of digital logic design and hands-on RTL coding experience using Verilog and SystemVerilog Strong understanding of control path and data-path digital design concepts with an eye for realizing correct by construction solutions Experience with specifying Design Verification (DV) requirements such as test plans, coverage metrics, and evaluate DV quality so as to realize robust design quality Knowledge of Lint, CDC, formal equivalence, DFT concepts, power analysis Experience with developing timing constraints and ability to carry out logic synthesis and Static timing analysis Good interpersonal, teamwork and communication skills to logically & effectively drive discussions with teams spread geographically Understanding of standard on-chip interfaces such as APB/AHB/AXI/ Stream protocols is a strong plus Knowledge of Processor/SoC architecture and/or DSP fundamentals is a strong plus Experience with end-to-end ASIC/ SoC product development & productization is very desirable Experience in IP integration (memories, IO s, embedded processors, hard macros, Analog IP) Knowledge of Microelectronics concepts Scripting skills in Python, Tcl, C etc Ability to collaborate and work directly with the tool vendors to resolve tools bugs, as well as implement the required improvements Great communication and teamwork skills

Architect and Designkey digital blocks such as accelerators/ datapath IP in Verilog/ System Verilog with built-in configurability to allow Power/ Performance/ Area tradeoffs Develop strong understanding of heterogenous processor cores subsystems (A55/ M55/ M4/ U55/ RISC-V/ DSP core, and associated infrastructure such as caches, interconnect fabric, GIC, DMA, MMU, Coresight Debug Trace, TZC, SMPU, SPU) and their integration requirements Consolidate curate digital IP for SPI/ I2C/ UART/ JTAG and other slow serial interfaces peripherals Evaluate 3rd party IPs on Power/ Performance/ Area (PPA) and other key qualitative aspects such as design quality, Design For Testability, robustness of Design Verification (DV) practice, ease of integration and make recommendations Build deep expertise on complex interfaces, peripherals protocols such as DDR, Ethernet, eMMC/ SD, MIPI, Display Port, HDMI, PCIe, high speed D2D Package Digital IP for seamless integration into design flow at different stages - RTL/ constraints/ CDC waivers, timing wavers, DFT DRCs and waivers, software programming sequence etc Develop and maintain catalog of digital IPs to enable ease of information sharing to customers across different BUs Develop User Guides for RTL Integration, Synthesis, DFT, PnR, Programming Sequence, characterization etc Establish evaluation flows for home-grown 3rd party IPs for consistent benchmarking of evaluation Position Requirements : Minimum B.E. /B.Tech degree in Electrical/Electronics/Computer science 5 -12+ years of digital logic design and hands-on RTL coding experience using Verilog and SystemVerilog Strong understanding of control path and data-path digital design concepts with an eye for realizing correct by construction solutions Experience with specifying Design Verification (DV) requirements such as test plans, coverage metrics, and evaluate DV quality so as to realize robust design quality Knowledge of Lint, CDC, formal equivalence, DFT concepts, power analysis Experience with developing timing constraints and ability to carry out logic synthesis and Static timing analysis Ability to technically mentor a few junior engineers Good interpersonal, teamwork and communication skills to logically effectively drive discussions with teams spread geographically Understanding of standard on-chip interfaces such as APB/AHB/AXI/ Stream protocols is a strong plus Knowledge of Processor/SoC architecture and/or DSP fundamentals is a strong plus Experience with end-to-end ASIC/ SoC product development productization is very desirable

Write high-level architecture specifications. Design and implement low power techniques including RTL and UPF design Lead PPA analysis and power modeling to determine design tradeoffs Perform synthesis and timing what-if analysis Develop and automate low power design flows in collaboration with cross-functional teams Minimum Qualifications Experience: M.Sc. Degree in Electrical Engineering, Computer Science, or Computer Engineering, with 10+ years of experience Experience in low power design and methodology in advanced technology nodes Excellent technical and analytical background with problem-solving skills Great team worker with multi-discipline, multi-cultural and multi-site environments Strong scripting and flow automation skills (Shell, TCL and Python) Strong RTL development experience in HDL programming languages (Verilog / SystemVerilog) Experience in Digital Design Flow including synthesis and static timing analysis In-depth understanding of low power design techniques such as power gating, clock gating, state retention, near-threshold computing, etc Excellent written and verbal communication Preferred Qualifications Experience: PhD in Electrical and Computer Engineering Experience in Cadence Suite (Virtuoso ADE Spectre) Experience in System-C and Platform Architect Experience in PDN or IR analysis Experience in SPICE simulation

Translate requirements to design specification by working closely with system architects Translate the design specification to optimal digital micro-architecture RTL coding using Verilog and System Verilog Building reusable sub-systems and systems, and drive automation with hands-on contribution during the integration of IP Manage the complexity of Safety, Security and Low-power as overlays on vanilla sub-system architectures Continuously improve the development and support model employed on Digital Processing sub-systems to ensure a high level of scalability and efficiency in product engagements Support simulation, DFT and silicon verification and validation of sub-systems, test and evaluation of ASIC products and FPGA development systems Meet power, performance and area goals by micro-architecture optimization Work closely with DV team to develop test-plans Front end implementation - Lint/CDC , synthesis, Timing constraint development Work closely with DFT and PD teams for signoff Support Silicon validation Mentor junior design engineers Minimum Qualifications: BE/BS/Mtech/M.E degree in Electrical/Electronics/Computer science from a reputed institute 10 years of relevant experience Strong engineering background in embedded system design, including ASIC microarchitecture, computer architecture, SoC architecture, and custom or standard DSP or hardware accelerator microarchitecture Strong hands-on RTL coding experience and debugging skills Digital Subsystem, clocking and full chip integration experience Expertise in timing constraints development and critical path timing closure Experience with silicon and software product development and understanding the product development lifecycle Knowledge of industry standard bus protocols such as AHB, APB, AXI Experience in digital signal processing and Matlab modeling is highly desirable Excellent verbal and written communication skills to work effectively with teams spread geographically Experience in mentoring junior engineers

Role : Physical Design Experience : 2 - 20 yrs. Strong background of ASIC Physical Design : Floor planning, P&R, Extraction, IR Drop Analysis, Static Timing and Signal Integrity.. Hands-on experience on technology nodes like 7nm, 14nm, 10nm.. Good knowledge of EDA tools from Synopsys , Cadence and Mentor. Hands-on experience in floor planning, placement optimizations, CTS and routing.. Hands-on experience in cadence or Synopsys tool (Encounter, ICC, PT/PTSI, TEMPUS, DC, RC, VOLTAS). Skills : Static timing analysis, Application Specific Integrated Circuit (ASIC), Floorplan Manager, Extraction, Synopsys and Physical Design. We are looking for a highly skilled Physical Design Engineer with a strong background in ASIC physical design. The ideal candidate should have hands-on experience in advanced technology nodes (7nm, 10nm, 14nm), and deep expertise in P&R, STA, IR drop analysis, and EDA tools such as Synopsys, Cadence, and Mentor. You will be responsible for all aspects of physical design implementation from RTL to GDSII. Key Responsibilities Execute complete RTL-to-GDSII physical design flow for complex ASICs. Perform floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification. Conduct timing closure using Static Timing Analysis (STA) with tools like PrimeTime (PT/PTSI) or Tempus. Perform IR drop and EM analysis, including extraction and signal integrity verification. Optimize physical designs for power, performance, and area (PPA). Run physical verification checks such as LVS, DRC, and Antenna. Collaborate with logic designers, verification, DFT, and packaging teams to drive design convergence. Debug and resolve physical design issues during implementation and tape-out phases. Utilize scripting (TCL, Perl, Python, etc.) to automate flows and improve efficiency. Key Skills Required Solid background in ASIC physical design, including floorplanning, P&R, extraction, STA, IR/EM analysis, and signal integrity. Hands-on experience with advanced process nodes like 7nm, 10nm, and 14nm. Proficiency In EDA Tools, Such As Synopsys : ICC, DC, PrimeTime (PT/PTSI) Cadence : Innovus, Tempus Mentor : Calibre Experience with floorplan managers, placement optimization, CTS, and final routing. Familiarity with parasitic extraction and delay modeling. Proficient in scripting using TCL, Perl, Python, or Shell for tool automation and flow management. Bachelor's or Master's degree in Electronics Engineering, VLSI, or related field. Knowledge of DFT, DFM, and low-power design techniques. Experience working on full-chip or block-level implementation. Experience with multi-voltage and multi-corner designs. Exposure to 3D-IC, chiplet-based architecture, or advanced packaging flows. Knowledge of RTL synthesis and constraints development. (ref:hirist.tech)

Job Description Jubilant Bhartia Group Jubilant Bhartia Group is a global conglomerate founded by Mr. Shyam S Bhartia and Mr. Hari S Bhartia with strong presence in diverse sectors like Pharmaceuticals, Contract Research and Development Services, Proprietary Novel Drugs, Life Science Ingredients, Agri Products, Performance Polymers, Food Service (QSR), Food, Auto, Consulting in Aerospace and Oilfield Services. Jubilant Bhartia Group has four flagships Companies- Jubilant Pharmova Limited, Jubilant Ingrevia Limited, Jubilant FoodWorks Limited and Jubilant Industries Limited. Currently the group has a global workforce of around 43,000 employees. About Jubilant Ingrevia Limited JubilantIngreviaisnowamemberoftheeliteGlobalLighthouseNetwork(GLN) oftheWorldEconomicForum(WEF) Jubilant Ingrevia history goes back to 1978 with the incorporation of VAM Organics Limited, which later became Jubilant Organosys and then Jubilant Life Sciences and now demerged to an independent entity as Jubilant Ingrevia Limited, which is listed in both the stock exchanges of India. Over the years, company has developed global capacities and leadership in chosen business segments. Ingrevia is born out of a union of ‘Ingredients’ and ‘Life’ (‘Vie’ in French). Jubilant Ingrevia Limited is committed to offering high-quality and innovative life science ingredients to enrich all forms of life. Jubilant Ingrevia, a global integrated Life Science products and Innovative Solutions provider serving, Pharmaceutical, Nutrition, Agrochemical, Consumer and Industrial customers with our customised products and solutions that are innovative, cost-effective and conforming to excellent quality standards. Jubilant Ingrevia Limited offers a broad portfolio of high-quality ingredients that find application in a wide range of industries. Jubilant Ingrevia’s portfolio also extends to custom development and manufacturing for pharmaceutical and agrochemical customers on an exclusive basis. Ourbusinessissplitacross3businessverticals,withgloballeadership acrossourkeyproductlines. Speciality Chemicals: The Specialty Chemical business of Jubilant Ingrevia manufactures Pyridine, Picolines and its forward integration derivatives, which finds application in agrochemicals, pharmaceuticals, dyes, solvents, metal finishes, fine chemicals, semiconductors etc. We have also launched new platform of Diketene & its value-added derivatives for multiple industry use. We are an established ‘partner of choice’ in CDMO, with more investment plans in GMP & Non-GMP multi-product facilities for Pharma, Agro and Semi-conductor customers. Chemical Intermediates: The Chemical Intermediates business has acetic anhydride and value added anhydrides and aldehydes catering to various industries. Nutrition & Health Solutions: The Nutrition & Heath Solutions business unit offers B3 & Picolinates (Chromium & Zinc) which are fully backward integrated. Our ingredients find application in animal nutrition, human nutrition, personal care, etc. We provide high-quality feed & food additives having application in poultry, dairy, aqua & pet food industry. In Human Nutrition & Health Solutions, we offer food ingredients & premix solutions to nutrition. Jubilant Ingrevia Limited is supported by five state-of-the-art manufacturing facilities in India. We practice world-class manufacturing processes in our day-to-day operations, assuring our customers with unmatched quality and timely delivery of products through innovations and cutting-edge technology. Transforming Manufacturing for Operational Excellence & Sustainability with “zero tolerance to any non-compliance” is the core focus of Jubilant Ingrevia Manufacturing. We have 5 world-class manufacturing facilities i.e. One in UP at Gajraula, Two in Gujarat at Bharuch and Savli, Two in Maharashtra at Nira and Ambernath. Environment Sustainability The company is committed to environmental sustainability and supports green chemistry by prioritising the use of bio inputs in manufacturing. Jubilant is one of the world’s largest producers of Acetaldehyde from the bio route. Find out more about us at www.jubilantingrevia.com The Position Organization - Jubilant Ingrevia Limited Designation & Level: - Research Scientist- Chemical Research. L1 Location - Greater Noida Reporting Manager - Sr. Group Leader- Chemical Research Matrix Manager: - Group Leader-CDMO Key Responsibilities Technical Expertise Proficient in literature search, route scouting, RM consumption norms, and chemistry with lab-to-plant process experience. Planning & Coordination Organize daily tasks, manage cross-functional collaboration, and ensure smooth project execution. Milestone Management Track project milestones, adjust plans as needed to meet deadlines. Technical Engagement Drive daily technical discussions, troubleshoot, and promote innovation. Stay current with regulatory guidelines. Regulatory Compliance Address regulatory deficiencies promptly and ensure all activities meet compliance standards. Manufacturing Support Engage in developmental manufacturing to integrate new processes effectively. Communication Deliver weekly technical presentations to update stakeholders on progress and challenges The Person Qualifications & Experience: M. Sc / PhD with 5 to 7 Years of Industrial Experience Proven experience in the development of Pharma and Agro intermediate molecules. Strong background in chemistry understanding and multi-step synthesis Familiarity with GLP, sample preparation, impurity isolation, and characterization. Experience in literature search, route scouting, and process development. Skilled in handling complex chemistries and pressure reactions. Excellent communication and coordination skills What’s on Offer: Opportunity to work with a leading company in the chemicals sector. Career growth opportunities in a rapidly evolving industry Jubilant is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, colour, gender identity or expression, genetic information, marital status, medical condition, national origin, political affiliation, race, ethnicity, religion or any other characteristic protected by applicable local laws, regulations and ordinances. To know more about us, please visit our LinkedIn page: https://www.linkedin.com/company/jubilant-bhartia-group/

Who We Are Boston Consulting Group partners with leaders in business and society to tackle their most important challenges and capture their greatest opportunities. BCG was the pioneer in business strategy when it was founded in 1963. Today, we help clients with total transformation-inspiring complex change, enabling organizations to grow, building competitive advantage, and driving bottom-line impact. To succeed, organizations must blend digital and human capabilities. Our diverse, global teams bring deep industry and functional expertise and a range of perspectives to spark change. BCG delivers solutions through leading-edge management consulting along with technology and design, corporate and digital ventures—and business purpose. We work in a uniquely collaborative model across the firm and throughout all levels of the client organization, generating results that allow our clients to thrive. What You'll Do As a Product Analyst for the Virtual Meeting Experience (VMX) squad, you will play a vital role in helping BCG deliver seamless, secure, and high-performance virtual meetings and whiteboarding experiences for our global workforce. You’ll work across a portfolio that includes Zoom, Microsoft Teams (meetings), Miro, Zoom Whiteboard, Microsoft Whiteboard, and Webex. In this role, you will work directly with the Product Owner, collaborating on discovery, backlog management, sprint readiness, user feedback synthesis, and adoption insights. Your efforts will help shape how BCG teams connect, collaborate, and share ideas, whether in one of our global offices, work from home or on the go. Key Responsibilities Include Support backlog grooming and sprint readiness, including writing and refining user stories, validating requirements, and ensuring readiness for development. Help manage and synthesize user feedback, insights, and adoption data to inform prioritization and product decisions. Track and report on metrics related to platform usage, performance, accessibility, and customer satisfaction. Assist in competitive benchmarking and market scans, especially in the emerging GenAI collaboration tool landscape. Coordinate user acceptance testing and help troubleshoot and escalate bugs or usability issues. Collaborate with cross-functional teams including engineering, data analytics, change & comms, and security to support smooth releases and user enablement. Support the creation of training materials, how-to guides, and onboarding documentation to increase awareness and drive adoption. What You'll Bring 1–3 years of experience in a product analyst, business analyst, or junior product role in a digital or collaboration tools environment. Exposure to or interest in tools like Zoom, Microsoft Teams, Miro, and other virtual collaboration tools. Basic familiarity with Agile ways of working and experience with Jira or similar backlog management tools preferred. Strong analytical skills and the ability to organize and interpret data related to platform adoption, user behavior, or system performance. Excellent written and verbal communication skills, with the ability to translate complex technical issues into user-friendly language. Curiosity for emerging collaboration trends, including GenAI and hybrid meeting innovations. A proactive, team-oriented attitude with a willingness to learn and grow within a high-impact, fast-paced team environment. Bachelor's degree in a related field (e.g., business, IT, communications, or digital media) preferred. Who You'll Work With Your squad teammates including the VMX Product Owner and engineering partners Cross-functional teams including User Experience, Change & Communications, Security, Enterprise Architecture, and Data Analytics Stakeholders across regions to capture needs and help support consistent experiences globally Users across BCG to gather feedback and champion meeting experience improvements Additional info YOU’RE GOOD AT Supporting Agile product delivery by collaborating with product owners and team members in sprint planning, refinement, and retrospectives. Gathering and synthesizing user feedback to help shape experience improvements and new feature evaluations. Maintaining clear, structured documentation for backlog items, user stories, and feature requirements. Proactively identifying gaps and areas for improvement across tools and user journeys, and sharing recommendations with the squad. Communicating clearly with technical and non-technical audiences, ensuring alignment and shared understanding across stakeholders. Staying organized across multiple streams of work in a fast-moving, highly collaborative product environment. Boston Consulting Group is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, age, religion, sex, sexual orientation, gender identity / expression, national origin, disability, protected veteran status, or any other characteristic protected under national, provincial, or local law, where applicable, and those with criminal histories will be considered in a manner consistent with applicable state and local laws. BCG is an E - Verify Employer. Click here for more information on E-Verify.

Tired of being a roadmap custodian? Ready to be a product visionary instead? As a seasoned product leader who's navigated the zero-to-launch journey, you understand that true product excellence is an ongoing pursuit—not a checkbox exercise. At Trilogy, we've reimagined product management. Forget managing endless backlogs or completing template specs. Here, you'll own a singular, meaningful business outcome. Your mission? Make it happen. With AI as your ally and user feedback as your compass, you'll translate deep domain knowledge into actionable insights, driving rapid product iterations until your target metrics sing. Join a team that values impact over process theater. We're building a culture where decisions flow from user data, quick feedback cycles, and razor-sharp insights—not meetings about meetings. If you're ready to transcend traditional product management and create something that genuinely moves the needle, we want to talk. This is product leadership as it was meant to be. What You Will Be Doing Craft and evolve BrainLifts—structured repositories of expert knowledge that enhance AI capabilities, inform strategic decisions, and demonstrate your domain mastery Deliver weekly product enhancements driven by data insights, continuously steering toward defined success metrics Cultivate comprehensive domain expertise, enabling high-caliber decision-making, precision-tailored outputs, and authoritative communication across the organization What You Won’t Be Doing Orchestrating month-long feature development cycles—we embrace a weekly ship cadence to maintain momentum Creating verbose product requirement documents, maintaining endless backlogs, or over-specifying every UI element and edge case Delving into technical implementation details or architectural design—focus on outcomes, not code Basic Requirements Principal Product Manager key responsibilities 4+ years in product leadership positions where you personally crafted product vision, established strategic roadmaps, owned core problem-solution hypotheses, and refined products based on metrics or customer insights Proven track record of successfully launching at least one complete software product (beyond features or modules) that reached external users in real-world scenarios Substantial enterprise software product management experience Genuine passion for integrating AI tools into your workflow (research, analysis, synthesis, strategy formulation) About Trilogy Hundreds of software businesses run on the Trilogy Business Platform. For three decades, Trilogy has been known for 3 things: Relentlessly seeking top talent, Innovating new technology, and incubating new businesses. Our technological innovation is spearheaded by a passion for simple customer-facing designs. Our incubation of new businesses ranges from entirely new moon-shot ideas to rearchitecting existing projects for today's modern cloud-based stack. Trilogy is a place where you can be surrounded with great people, be proud of doing great work, and grow your career by leaps and bounds. There is so much to cover for this exciting role, and space here is limited. Hit the Apply button if you found this interesting and want to learn more. We look forward to meeting you! Working with us This is a full-time (40 hours per week), long-term position. The position is immediately available and requires entering into an independent contractor agreement with Crossover as a Contractor of Record. The compensation level for this role is $100 USD/hour, which equates to $200,000 USD/year assuming 40 hours per week and 50 weeks per year. The payment period is weekly. Consult www.crossover.com/help-and-faqs for more details on this topic. Crossover Job Code: LJ-5623-IN-Gurgaon-PrincipalProdu

Role & responsibilities: Core Purpose of the Role: Personnel handling this profile will be responsible for performing reactions as per the requirement of the project. They are also responsible for documenting the observations in relevant note books. They are to follow instructions from the supervisor and work in a group (or individually) to accomplish the tasks in a timely and efficient manner Role Accountabilities: Perform synthetic chemistry reactions, reaction workups, purification of the compounds by column chromatography, crystallization, re-crystallization techniques, preparative TLC and operating lab equipments Ensure that the samples generated during synthesis are given for analysis and record subsequent results obtained and update the supervisor / group leader on the progress of synthesis and ensure samples are packed appropriately for shipment Record the observations of experiment/reaction, results, utilization of resources and other activities related to the reaction in the laboratory or e-notebook following guidelines and in timely manner and ensure that the same is handled safely and confidentially. Ensure that the instrument / equipment is calibrated, undergone preventive maintenance and are kept clean before use and in case of any breakdown, report to maintenance immediately Ensure that they know the MSDS of the chemicals they are handling and aware of emergency response procedures in case of accidental spillage, leakage or fire and ensure proper waste segregation as per EHS norms Always follow EHS and quality system requirements in the workplace ensuring individual safety and lab safety Attend all mandatory trainings and update training records as and when trainings are completed Always ensure confidentiality Preferred candidate profile

Strategic Efficient contribution to the overall success of Product Innovation by driving innovation and team performance according to objectives and targets being set by HoF of Process Research. Fulfilling requirements as set by Group Leader and Team Leader within specific Research Projects Ensuring the security of intellectual property for Product Innovation (patent applications) Operational Keep self updated on new developments and techniques in synthetic chemistry and process research Continuous documentation and reporting of all research results obtained within the area of responsibility as defined in the SOP / guideline Carrying out experiments with knowledge of SDS of starting materials and reagents used. Seek functional support actively from Senior RS/Team Leader Carrying out literature search by use of available tools (Reaxys/SciFinder/Patents etc.) Carrying out synthetic experiments safely, efficiently, capturing all the experimental procedures and data Updating the GL/TL on the functional progress/issues of the project on a regular basis Constructive and active participation in all technical and functional meetings of the Team Responsible for individual safety and housekeeping of the lab People Actively imbibing the values and philosophy of PI Industries Support Team members by providing peer feedback Foster an environment of knowledge sharing within the Team Email ID - Deepanshu.bhatt1@piind.com Mobile- 8696900583

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Knowledge in Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Good knowledge of Tcl/Perl Scripting Strong problem-solving skills and good communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 1-3 yrs years of experience in Physical Design/Implementation

Job Area: Engineering Group, Engineering Group > Machine Learning Engineering General Summary: Job Overview: Qualcomm is a company of inventors that unlocked 5G - ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. We are investing in several supporting technologies including 4G, 5G, Edge Computing, and Deep Learning.The Qualcomm AI team is developing hardware and software for Machine Learning solutions spanning the data center, edge, infrastructure, automotive markets and beyond. We are seeking ambitious, bright and innovative engineers with experience in Machine learning frameworks, compiler technology, vectorization and optimization, and machine learning toolchains.Job activities span the whole product life cycle from early design to commercial deployment. The environment is fast-paced and requires cross-functional interaction on a daily basis so good communication, planning and execution skills are a must. We are looking to staff engineers at multiple levels in systems & software, integration and test. Details of one of the roles we are looking to staff are listed below. Responsibilities: Research, design, develop, enhance, and implement the different components of machine learning framework, compilers based on performance and code-size needs of the customer workloads and benchmarks. Analyze software requirements, determine the feasibility of design within the given constraints, consult with architecture and HW engineers, and implement software solutions best suited for Qualcomm's SOCs. Analyze and identify system level integration issues, interface with the software development, integration and test teams. Minimum Qualifications Bachelor's degree in Engineering, Information Systems, Computer Science, or related field. 8+ years Systems Engineering or related work experience. Preferred Qualifications Has internal working knowledge of Machine learning frameworks like Pytorch, Tensorflow. Has experience in model level optimization using techniques like torch compile. LLVM or any industrial strength compiler development experience is a plus. Knowledge of the structure and function of the compiler internals. Hands on experience writing SIMD and/or multi-threaded high-performance code is a plus. Hands-on experience implementing DSP Kernels a plus Hands-on Experience in C/C++, Python development (5+ years) Hands-on Experience with Object Orientated Design, TDD development solutions such as GoogleTest etc. (4+ years) Experience with Source Code and Configuration management tools, git knowledge is required Willingness to work in a cohesive software development environment with ability to work on low level implementation (code & test) and interfacing with hardware and simulators Experience in neural network architectures + ML compiler workload synthesis, a plus Prior working experience of hardware accelerators and hardware software co-design Experience in using C++ 14/17 (advanced features) Experience at both the firmware (RTOS) and system level (Linux) in SOC Experience of profiling software and optimization techniques Passion to drive to develop leading-edge "deep learning" framework and algorithms working on mobile and embedded platforms. Minimum Qualifications: Bachelor's degree in Computer Science, Engineering, Information Systems, or related field and 4+ years of Hardware Engineering, Software Engineering, Systems Engineering, or related work experience. OR Master's degree in Computer Science, Engineering, Information Systems, or related field and 3+ years of Hardware Engineering, Software Engineering, Systems Engineering, or related work experience. OR PhD in Computer Science, Engineering, Information Systems, or related field and 2+ years of Hardware Engineering, Software Engineering, Systems Engineering, or related work experience.