Roles and Responsibilities Responsible for the availability of raw materials as per lab requirements To analyze quality results and discuss the experimentation plan with Research Incharge. Understand the safety aspects of all reactions and chemicals to be used Ensure the setup ( reaction assembly, distillation, filtration, reaction work-up, crystallization) as planned Carry out reaction process as per the provided plan, get the analysis done of raw material , in process reaction intermediate and product Record all observations and give suggestions for improvement Ensure proper housekeeping of the lab Maintain highest safety practices while working by using required PPEs (Personal protective equipment) Maintain the log sheets of all the experiments regularly with critical observations and feed the data into Electronic Lab Notebook (ELN) Stack of all the chemicals & glassware as per 5S (sort, set-in-order, shine, standardize, sustain) After reaction completion, decontaminate the glass apparatus and give for further cleaning. Segregate effluents as per the lab system Desired Candidate Profile Minimum M.Sc. Organic Chemistry or equivalent 2-7 Years of experience is required 1year Stability in current company Only from Chemical Company

Who we are Kinara is a Bay Area-based venture backed company Our architecture is based on research done at Stanford University by Rehan Hameed and Wajahat Qadeer under the guidance of legendary Prof Mark Horowitz (http://www-vlsi stanford edu/~horowitz/) and Prof Christos Kozyrakis http://csl stanford edu/~christos/) What we do Our game-changing AI solutions revolutionize what people and businesses can achieve Ara inference processors combined with our SDK deliver unrivaled deep learning performance at the edge to accelerate and optimize real-time decision making where every millisecond is critical, and power efficiency is a must Kinara solutions embed high-performance AI into edge devices to create a smarter, safer, and more enjoyable world Edge AI is on the brink of a boom, and Kinara is looking forward to playing a significant role in it About The Role We are seeking a talented Implementation Engineer to join our dynamic team The successful candidate will be responsible for leading and executing Synthesis and STA for complex AI SOC with multi-mode and multi power domain design, ensuring the quality and reliability of our products This is what you are responsible for Synthesis and STA (static timing analysis) Ability to optimize designs for best in class in low power and high performance with logically equivalent RTL Professional experience with ECO implementation, both functional and timing closure Experience with multi-clock, multi-power domain designs and multi-mode timing constraints Familiarity with DFT insertion Familiarity with simulation, debugging tools, and working closely with Design teams Ability to collaborate with different functional teams like RTL Design, DFT and Physical design Showcase your deep understanding of the following physical design concepts/constraints: floor-planning, placement, congestion, and setup/hold timing closure Necessary Qualifications Bachelors or Masters degree in Electronics, Computer Science Engineering, or a related field Minimum of 5 to 7 years of experience in Implementation flows/ Synthesis and STA Experience with Cadence, Synopsys and Mentor tools Experience with Verilog and VHDL Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks (UPF/CPF/CLP) Formal verification for RTL 2 gates and gates2gates Conformal ECO for doing complex functional ECOs Low power synthesis on smaller blocks and subsystems using DC/Genus Physical Aware synthesis Writing Timing Constraints sub-blocks and Top level Flow Automation and Scripting using TCL and Python or Perl Work culture We at Kinara have an environment that fosters innovation Our team has technology experts who understand the big picture and mentors who coach passionate professionals to work on the most exciting challenges We share responsibilities in everything we do, where every point of view is valued Join us! Now tell us your story We are looking forward to reviewing your application Make your mark!

* Select/modify flow reactors. *Plan lab work and characterize RS/WS. *Scale-up processes and prepare RM specifications. *Conduct stability studies and impurity analysis. *Prepare development reports and manage technology transfer. *Perform risk analysis and oversee shift manpower. *Handle RM requisitions and coordinate with R&D and analytical teams. *Ensure safety in all procedures and prepare process documentation.

Key Responsibilities: Floor planning: Develop and optimize floorplans for ASIC designs, ensuring optimal placement of cores, macros, and I/O cells while considering performance and manufacturability. Place & Route (P&R): Perform place-and-route tasks, optimizing for timing, power, and area, ensuring congestion-free routing and maximizing PPA (Performance, Power, Area). Static Timing Analysis (STA): Carry out static timing analysis to identify violations and work on techniques for timing closure such as resizing, retiming, or re-optimization. Power Analysis & Optimization: Perform power analysis, targeting low-power designs using techniques such as clock gating, power gating, and low-power state optimization. Signal Integrity & Noise Analysis: Perform signal integrity analysis to avoid noise and crosstalk in the design. Design Rule Check (DRC) and Layout vs. Schematic (LVS): Run DRC and LVS checks to ensure the layout adheres to manufacturing rules and matches the schematic. RC Extraction: Perform parasitic extraction and analyze RC effects to ensure the design functions at the required operating frequencies. Verification: Participate in the final sign-off processes for physical design and support tape-out efforts, ensuring all design specifications are met. Collaboration: Work closely with design, verification, and CAD teams to troubleshoot and resolve any design-related issues. Documentation: Maintain clear documentation throughout the physical design flow for ease of understanding and for future reference. Qualifications: Education: Bachelors/Masters degree in Electronics/Electrical Engineering or a relevant degree. Experience: Minimum 4-14 years of experience in ASIC physical design. Proficiency in place and route (P&R), static timing analysis (STA), power analysis , and DRC/LVS checks. Experience with tools like Cadence,Innovus , Synopsys IC Compiler , or Mentor Graphics for physical design. Knowledge of advanced process nodes (e.g., 7nm, 5nm) is a plus. Technical Skills: Proficiency in digital design concepts and semiconductor process flows. Strong knowledge of timing optimization techniques and power optimization strategies. Familiarity with parasitic extraction and signal integrity analysis. Ability to script in languages like Tcl , Python , or Perl to automat tasks. Preferred Skills: Experience with 3D IC design or FinFET technologies. Familiarity with full-chip tape-out procedures. Exposure to machine learning techniques in physical design optimization will be added advantage. Perks and benefits According to company norms

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. We are seeking engineers with experience in system and device level functional safety concepts and implementations. This position will be a hands-on role in analyzing Functional Safety concepts and requirements in existing and next generation ADAS/Autonomy systems offered by Qualcomm, while optimizing and exercising the full capability of the Qualcomm Snapdragon platform. Responsibilities shall include the following: Developing a system level safety concepts and requirements for ADAS and IVI use cases with customer implementations in mind and to integrate Qualcomm"™s hardware in leading Automotive OEM and Tier 1 safety critical systems. Work in collaboration with 3rd party, Customer, and Automotive Stack suppliers, Hardware component suppliers (PMIC, DRAM, Sensor, etc) to ensure all aligned customer system level requirements are met Work with IP and SoC teams on the implementation of Technical Safety Concepts (TSCs) on Qualcomm"™s Snapdragon automotive hardware. Work with various technology teams on architectural features that would enable targeted safety levels (ASIL B to ASIL D, depending upon the technology team and system level requirements) to meet customer targets Conducting safety analyses, both quantitative and qualitative, fault campaigns on automotive hardware designs and identify areas of improvement. Responsibilities will include leading functional safety related activities for SoC development and ensure ISO 26262 compliance with respect to SoC architecture, development processes and work products. Work closely with SoC Design and IP teams, Software team, Quality teams, the functional safety manager(s) as well as customers to ensure the functional safety process is executed and documented. Working with vendors and partners to ensure functional safety requirements are fulfilled by the components that they provide Work with internal and external functional safety assessors to ensure compliance with ISO 26262 Create functional safety collateral for customers viz. Functional Safety Manual, Safety Analyses Reports, dedicated application notes etc. Supporting customer assessments of our safety features and recommending HW and SW based solutions that meet overall system targets. Working closely with customers and supporting them on various functional safety related aspects Minimum Qualifications Bachelor"™s degree in engineering, Information Systems, Computer Science, or related field. 8+ years Systems Engineering, SoC Integration, Verification, or related work experience. Collaborative work experience with good communication skills involving customers, vendors, and internal development teams. Structured problem-solving capability and ability to work with teams on root cause analyses. Preferred Qualifications 5+ years Automotive experience and familiarity with Safety work products, experience with Functional Safety Hardware and/or Software development in semiconductor industry meeting IS0 26262/ IEC 61508 standards. Prior automotive experience in ADAS and self-driving systems preferred. System level Functional safety analysis experience on Hardware/Software components integration preferred SoC/IP integration or verification with good understanding of SoC Architecture and IP design experience preferred Requirements Management Tools and establishing traceability for functional safety requirements e.g. DOORS, etc. Familiarity with Failure Modes and Effect Analysis (FMEA) and Fault Tree Analysis (FTA) is required experience using tools to perform FMEA, FTA preferred Familiarity with hardware failure rate calculation (FMEDA) experience using Siemens 29500 and/or IEC 62380 preferred Relevant Safety Certification is desired e.g. CFSE, CFSP

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Function :Camera Design Lead/Staff Candidate will be responsible for design/developing next generation SoCs sub systems for mobile phone camera . Candidate will be working on ASIC based on the latest technology nodes. This role will require the candidate to understand and work on all aspects of VLSI development cycle like architecture, micro architecture, Synthesis/PD interaction and design convergence. Skills/Experience Solid experience in digital front end design for ASICsSolid Expertise in RTL microarchitecture and design coding in Verilog/SV for complex designs with multiple clock and power domainsExpertise with various bus protocols like AHB, AXI and NOC designs Experience in low power design methodology and clock domain crossing designsUnderstanding of full RTL to GDS flow to interact with DFT and PD teams Experience in Tools like Spyglass Lint/CDC checks and waiver creationExperience in formal verification with Cadence LEC Experience in mobile Multimedia/Camera design is a plus DSP /ISP knowledge is a plus. Working knowledge of timing closure is a plusExpertise in Perl, TCL language is a plusExpertise in post-Si debug is a plus Good documentation skillsAbility to create unit level test plan General Should possess good communication skills to ensure effective interaction with Engineering Management and mentor group members. Should be self-motivated and good team working attitude and need to function with little direct guidance or supervision Responsibilities Digital design and development (RTL) working in close collaboration with Multi-site leadsDeveloping the micro architecture and implementing the design using Verilog/SV. Integrate and deliver complex subsystem to SoCDesign and implement defined tasks independently. Work in close coordination with Systems, Verification, SoC team , SW team, PD & DFT teams to get the goals completed.Analyze reports/waivers or run various tools :Spyglass, 0-in, DC-Compiler, Prime time, synthesis, simulation etc Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. As a Physical Design Timing Engineer, you will work with microarchitecture, RTL design, CAD, block level and top level physical design teams to run, analyze timing and drive timing closure. Roles and Responsibilities Work with design and DFT teams to understand, implement and validate constraints. Run SOC timing runs at all hierarchies Analyze timing and work with RTL/DFT teams to facilitate logic changes required. Feedback to block level and top level physical design engineers on key fixes required for timing closure. Work with CAD team to implement timing infrastructure. Create ECOs from timing runs to help timing closure. Document and help with timing methodology definition Preferred qualifications MS degree in Electrical Engineering; 10 years of practical experience Experience in timing flows with industry standard tools. Experience in all aspects of timing closure for multi-clock domain designs. Experience in deep submicron process technology nodes is strongly preferred. Experience with STA on large SOC with multi-scenario timing closure. Experience with Timing ECO techniques and implementation. Knowledge of library cells and optimizations. Familiar with circuit modeling, transistor fundamentals and worst case corner selection. Solid understanding industry standard tools for synthesis, place & route and tapeout flows. Good communication skills to work with different teams to accurately describe issues and follow them through for completion. Experience in STA and timing closure of high-performance SOC designs in sub-micron technologies. Knowledge of all aspects of timing including noise, cross-talk and others. Knowledge of basic SoC architecture and HDL languages like Verilog.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Preferred Qualifications 6-9 years of experience in SoC design Educational Requirements:6+ years of experience with a Bachelor"™s/ Master"™s degree in Electrical engineering

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Additional About The Role : Minimum Qualifications Bachelor's degree in Science, Engineering or closely related field Experience with digital design and RTL development, Experience with front end EDA tools such as Synopsys Next Generation tools, Conformal LEC, Synopsys Formality and Synopsys PrimeTime Preferred Qualifications Knowledge and experience of graphics design and development Proficient in Perl, TCL and shell scripting Excellent interpersonal and team skills yet able to work independently and able to problem solve complex, unique and detailed issues Be Familiar with The latest EDA tools for synthesis, formal verification, timing analysis and physical design

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains"“ LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux "“ Perl/TCL fundamentals/scripting Principal Duties and responsibilities: Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications: 5+ years Hardware Engineering experience or related work experience. 4+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Exp : 3 "“ 5 Yrs Position : Senior or Lead Expertise : Power fundamentals Good knowledge of PTPX Good knowledge of CLP Knowledge of design verification, RTL coding, synthesis, and physical design Protocol knowledge of , DDR, CHI, Cache, computer organization, bus protocol, Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Qualifications: Bachelor"™s or Master"™s degree from a top-tier institute. 2- 5 years of experience in physical design from product-based companies. Experience: Proven experience in managing complex subsystems and small teams. Proficiency in synthesis, place and route (PnR), and sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations. Job Requirements: Expertise in meeting demanding Power, Performance, and Area (PPA) requirements for complex subsystems/System on Chips (SoCs), place and route, and IP integration. Experience in low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating. Familiarity with ASIC design flows and physical design methodologies. Strong understanding of circuit design, device physics, and deep sub-micron technology. Experience working on multiple technology nodes in advanced processes. Proficiency in automation to drive improvements in PPA.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. 5 to 7 years of experience in static timing analysis, constraints and other physical implementation aspects. Solid understanding industry standard tools PT, Tempus, GENUS, Innovus, ICC etc. Solid grip on STA fixing aspects to solve extreme critical timing bottleneck paths. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains"“ LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux "“ Perl/TCL fundamentals/scripting Principal Duties and responsibilities: Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications: 4+ years Hardware Engineering experience or related work experience. 3+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: QCT's Bangalore Wireless R&D HW team is looking out for experienced HW design engineer to work on WRD IPs for Qualcomm"™s best in class Mobile chipsets. Location :Bangalore Roles and Responsibilities You will be contributing to flagship Wireless IP development covering WAN, WLAN, GNSS and Bluetooth technologies. You will be part of team defining and developing next generation Wireless R&D products. The candidate must have IP design experience preferably in wireless/DSP domain. The candidate must be strong in design micro-architecture & RTL coding (System Verilog or Verilog or VHDL). Other requirements are : Exposure to synthesis & STA Low power and high speed design awareness Knowledge on design flow, industry standard frond end tools flows ( lint, cdc, etc.) Knowledge of scripting and automation:Unix/Linux shell programming, Perl, Python, Makefile etc. Strong critical thinking, problem solving and debug skills Good communication and interpersonal skills. Flexible to work with multi-geo team Minimum qualification :Bachelors or Master"™s in Electrical/Electronics/Computers Science from reputed college/university. Years of experience :2 "“ 4years Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3 to 5 years of experience in static timing analysis, constraints and other physical implementation aspects. Solid understanding industry standard tools PT, Tempus, GENUS, Innovus, ICC etc. Solid grip on STA fixing aspects to solve extreme critical timing bottleneck paths. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Creating power spec for Qualcomm DSP IPs based on the design spec Power intent development using UPF for DSP IPs based on power spec Power intent validation at RTL level , Gate level (synthesis , PD ) using CLP Fixing power intent based on PA DV feedback for any issue related to power intent Debugging issues related to MV cell insertion during synthesis and modifying UPF accordingly Dynamic and Leakage power projection of DSP IPs during starting of the project Dynamic and Leakage power no. generation using PTPX and tracking the same at different stages of implementation flow Highlighting issues related to dynamic and leakage power mismatch compared to the target and working with Synthesis and PD teams to fix the issues Working with cross function teams (SOC, Sub System etc) for smooth handoff of power intent and Dynamic & leakage power no. at different stages of project execution Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must . Must have hands on experience with SoC design and integration for SoCs. Experience in Verilog/System-Verilog is a must . Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required . Hands on experience in Multi Clock designs, Asynchronous interface is a must . Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3-6 yrs of experience

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 1 to 3 years of experience in static timing analysis, constraints and other physical implementation aspects. Solid understanding industry standard tools PT, Tempus, GENUS, Innovus, ICC etc. Solid grip on STA fixing aspects to solve extreme critical timing bottleneck paths. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language

Dear Candidate, We are conducting walk-in drive on 05 Apr (Saturday) for the positions in our Discovery Chemistry department. Job Description : Position Name: Research Associate / Senior Research Associate Experience: 2 to 8 years Qualification : M.Sc Organic Chemistry / Medicinal Chemistry Work location: Hyderabad Walk-in Date: 05 April 2025 (Saturday) Time: 10:00 AM to 12.00 PM Venue:- Chemveda life Sciences Admin Building,1st Floor, Plot No. B-11/1, IDA Uppal, Hyderabad-500 072. Key Skills and Competencies: Experience in Organic Synthesis/Multi-step Synthesis Handling reactions from mg to KG scale. Sound Knowledge of isolation, separation & purification techniques. Experience in characterization and identification of Organic molecules using spectroscopy techniques like NMR, IR, LCMS, HPLC. Positive and confident individual with strong work ethics. Team player and good communication skills Interested candidates can attend walk-in drive or share their profiles to hr@chemvedals.com

Candidate must have experience Min. of 4 to 5 years of experience in chemical synthesis, process development. Experience in designing complex reactions, optimizing conditions, scaling up, & ensuring safety & involving organic synthesis, purification Required Candidate profile Experience in organic reaction mechanism, transformations & functional group chemistry. Proficient in optimizing reactions for scale-up with expertise in safety, catalytic processes & green chemistry.

Roles and Responsibilities Good experience in PD execution of multiple medium to High critical blocks/HMs from Netlist to GDSII Develop and qualify the methodology and implementation flow in advanced technologies like 14nm and below. Well versed with FC/Innovus tools and good understanding of place/cts/Route critical settings Develop expertise in ASIC Synthesis, Floor Planning, STA (Static Timing Analysis), and other relevant technologies. Good experience in Low power designs Conduct thorough analysis of designs to identify potential issues and implement solutions. Perform physical design activities including floor planning, PNR (Physical Netlist) creation, and timing closure using Innovus tools. Interested candidates can contact me at shubhanshi@incise.in

Researcher II Noida, Uttar Pradesh, India No longer accepting applications Date posted Mar 19, 2025 Job number 1814895 Work site Up to 100% work from home Travel 0-25 % Role type Individual Contributor Profession Research, Applied, & Data Sciences Discipline Research Sciences Employment type Full-Time Overview The PROSE team is advancing the state of the art in program synthesis and shipping these innovations through flagship Microsoft products that impact millions of users worldwide. These products include the world’s most popular spreadsheet software Excel, the industry-leading IDEs Visual Studio and Visual Studio Code, the power platform suite of products including Power BI, PowerApps, PowerAutomate, and other software tools including Azure Data Studio, Azure Data Monitor, Azure Data Factory, PowerShell, and SQL Server Management Studio. The application domains range from developer productivity, business user low-code/no-code scenarios to even programming education. To power these features PROSE has developed a powerful and flexible framework for program synthesis that leverages techniques from both logical reasoning and machine learning (including LLMs) and combines them in unique ways to synthesize programs automatically. This approach has been recognized with frequent papers at top-tier conferences and awards, including best paper and test-of-time awards. We invite researchers with machine learning, programming language, or software engineering research to apply for a full-time position on the PROSE team at Microsoft. The recent success of large language models (LLMs) creates an opportunity to take a qualitative step forward, to extend dramatically the reach of what users can do with Copilots. Our team provides a unique opportunity to work at the intersection of cutting-edge AI research and real-world impact, solving customer problems on a global scale. Researchers design and carry out the research underlying state-of-the-art systems and work together with world-class engineers to implement these systems in production. To learn more about our approach and culture see this award talk on the story behind one of the team’s early innovations: the Flash Fill feature in Excel. Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond. Qualifications Required Qualifications Bachelor+ in Computer Science or a relevant field and 4+ years related-research experience. Or Master+ Computer Science or a relevant field and 3+ years related-research experience. At least 2 publications in top-tier machine learning, programming language, software engineering or relevant venues (e.g. AAAI, NeurIPS, ICML, ICLR, EMNLP, NAACL, ACL, POPL, PLDI, OOPSLA, ICSE, FSE, and comparable). Ability to develop an original research agenda, demonstrated by leading at least one publication in a top-tier machine learning, programming language, software engineering or relevant venue. At least 2 years of prior research experience in machine learning, programming language, or software engineering. Preferred Qualifications Experience in training transformer-based models (including collecting and curating training data) as part of research projects in an industrial or academic setting. Experience working with large language models, including automated prompt tuning, fine-tuning, instruction-tuning and continued pre-training. Experience with reinforcement learning and its applications to training LLMs. Responsibilities Design and carry out innovative research with applications to code and data platforms (e.g., Excel). Work with engineers and PMs to deploy your research to customers. Collaborate with academic partners, mentor interns and longer-term research fellows. Publish in top-tier academic venues and interact with the broader academic community. Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.  Industry leading healthcare  Educational resources  Discounts on products and services  Savings and investments  Maternity and paternity leave  Generous time away  Giving programs  Opportunities to network and connect Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations. No longer accepting applications

Experience: 5 + - Should have worked hands-on Full chip DFT implementation, Scan, DRCs, ATPG generation & Simulations along with Pattern Porting/re-targeting and Coverage improvement -Experience with Scan, Compression, ATPG and simulations with Synopsys EDA tools. - Should have participated in successful tape-outs of SoC/ASIC chips at 3nm or below and achieved test targets. - Descent understanding of front-end SoC/ASIC design and implementation including Synthesis and STA. -Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process -Excellent problem solving and debugging skills. Proactive in nature - Excellent Customer interaction, Communication and Team work skills

Collaborate with the design team for the implementation of various hard IPs and the SoC top level. Lead the top-level implementation of SoC designs, including IO ring integration. Utilize Synopsys Fusion Compiler for physical and WLM synthesis. Perform timing analysis and resolve timing issues related to implementation. Conduct DFT insertion and ensure robust design for testability. Execute place and route flows using Cadence Innovus and Synopsys Fusion Compiler. Manage chip-level and block-level design implementation. Design and analyze IO rings. Implement FlipChip SoC designs, including RDL routing. Ensure timing and design signoff, including STA, LVS, and DRC. Utilize tools such as Synopsys Design Compiler, DFT Compiler, PrimeTime, Cadence Innovus, and Mentor Graphics Calibre for various implementation tasks. Interested candidates can share their resumes to shubhanshi@incise.in