About The Role Come join the Devices Development Group, one of Intel's leading SoC design teams. In this role you will be working as part of a pre-silicon validation team for future Intel SoCs and IPs. Your responsibilities will include but not be limited to: Validation of an IP or feature at the SoC level. Creating plans and tests for validating portions of a complex microarchitecture using written specs, RTL code and other tests as a guide. Learning the architecture and microarchitecture by debugging failures to the root cause. Developing and utilizing various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design. Participating in the debug of failures on silicon and developing new testing strategies to detect these failures on RTL models. Engaging with IP providers and customers to define, develop and deliver necessary infrastructure and address issues found during execution. Qualifications Educational Qualifications: Must have either a BS/Btech + 5 years' experience or MS/MTech + 3 years' experience in Computer Science, Computer Engineering or Electrical Engineering. Minimum 2 years' experience working on IP or SoC development, verification, or integration using System Verilog and UVM. Minimum 2 years' experience with writing validation plans and software to implement those validation plans. Minimum 2 years' experience with an object-oriented programming language. Minimum 2 years' experience with System Verilog and UVM. Minimum 1 years' experience with UNIX or Linux. Exposure to Graphics Verification and/or Security Verification is an advantage. Preferred Qualifications - Minimum 1 year experience with computer architecture.- Minimum 2 years' experience with validation or testing experience, especially in a silicon design team. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

About The Role Seize the opportunity to work with the team responsible for RTL logic design and microarchitecture of chipsets for PCs millions of people around the world will use. The Chipsets Logic Team, CLIPS is responsible for developing soft IPs, subsystems and gaskets for client and server chipsets.Candidate will be responsible for logic design and development, responsibilities including but not limited to: Develops the logic design, register transfer level (RTL) coding, and simulation for an IP design. Participates in the definition of microarchitecture features of the block being designed. Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for meet the design specification requirements. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Follows secure development practices to address the security threat model and security objects within the design. Supports SOC to integrate and validate the IP on need basis. Drives quality assurance compliance for smooth IPSoC handoff. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Qualifications : The candidate must possess a minimum of Bachelor Degree in Electronics Engineering, Computer Engineering, Computer Science or equivalent. The candidate should have successful track record of hardware development experience and demonstrated technical leadership skills. The candidate must have demonstrated the ability to solve highly complex technical problems with excellent communication skills. The candidate must also have demonstrated strong ethical standards. Must also be able to perform in a highly ambiguous and dynamic business environment. Hands on experience in IP RTL, Microarchitecture, TFM, synthesis, cdc, lint, spyglass, rdc. Skills : Relevant experience with skills in ASIC IP design flows, RTL coding and Globals (Clocking, Boot/Reset/Fabrics, DfD, Fuse, etc) Experience in subsystem design and IO protocols such as AMBA, USB, PCIe, UCIe, UFS, SATA, UART, SPI, I2C, I3C etc is a plus. Other technical requirements: 8-14 years of relevant pre-silicon logic design experience in ASIC domain. Experienced with various tools and methodologies including but not limited toSystem Verilog, Python/Perl/Shell scripting, Synopsys tools, RTL model build, design-for-test, design-for-verification. Experienced in EDA tools and flows such as Spyglass VCLINT, VCLP, VC-CDC, SG-DFT, Design Complier, Calibre, Fishtail, FEV, ATPG etc. Experienced in developing micro-architecture based on High Level Architecture specifications. Experienced in VLSI or Structural and Physical design flow and methodology. Experienced in Power-aware design and reviewing validation flows. Strong Chipset or CPU level understanding required on power consumption, power estimation and low power design methods. Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

About The Role Looking for enthusiastic, motivated and self-driven engineer in area of Power Analysis and Signoff who can take care of Understanding and Defining Chip Power & Performance Targets Analyzing FSDBs for various design power scenarios and extracting the right activity windows Running Power Estimation and Analysis at block level and roll-up total power for SoC Working with Architecture, Design and Implementation teams for power optimization Running LP checks at block and full chip level, analyzing the logs/reports and deliver quality results Work closely with the FE & BE teams for overall Power Convergence and Low-Power Sign-off of the design for Tape-out Qualifications BE/ME in Electrical Engineering with 8+ years of experience in Logic Design, Synthesis and Low Power Design/Implementation for complex multi-million gate SoCs Expertise in power analysis using PT-PX/Prime Power Experience in Verdi tool for FSDB analysis Experience in power analysis using Power Artist tool is a plus Experience in industry standard tools LP checks, PTPX for power estimation etc. Strong analytical and problem-solving skills Expertise in Tcl, Perl/Python is required Inside this Business Group Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

About The Role In this position, you will be responsible for managing and working on all aspects of STA and timing closure activities of Intel SoCs in lower technology nodes. Your tasks will include but not limited to: Design and Architecture understanding, Interaction with FE/DFT/Verification teams, Clocking, Constraints development, ACIO Timing, Understanding on synchronous and asynchronous paths, Clock domain crossing issues. Understanding and debugging extraction issues, deciding timing signoff modes and corners, Design margins, Hierarchical timing including IO budgeting for partitions. Drive the designs to timing closure, interacting/supporting synthesis and APR team during timing closure cycle, timing ECOs, Timing model build, Timing signoff and quality checks. You will also be part of debug/troubleshoots for a wide variety of tasks up to and including difficult/critical design issues and proactive intervention, as required. Qualifications EducationB.Tech. or M.Tech. in Electrical/Electronics Engineering with 10-14 years' of experience.PreferenceMaster's Degree in Electrical/Electronics Engineering with VLSI/microelectronics specialization, with 10+ years of experience in STA.Key Skills: In-depth knowledge and hands-on experience with the overall silicon implementation flows and methodologies such as STA, Synthesis, Clocking is required. Good understanding and exposure of overall Timing closure cycle in SoC. Good scripting skills in TCL/Perl/Shell. Expertise in STA signoff tools (PT/ETS). Skill in Synopsys tools (PT/DC) and exposure to ICC will be an added advantage. Solid understanding of the process and design interactions as they relate to target frequency and interaction with timing paths and resulting leakage and power trade-offs. Solid technical and good communication skills. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

API synthesis, Intermediates synthesis, Process development Purification; Extraction, cost reduction projects. Performing various synthetic organic reactions

Available locations - Pune , Mumbai, Hyderabad, Chennai, Kolkata, Gurugram, Bengaluru Role & responsibilities Job Description: Instructional Designer and Course Developer Position Overview: We are seeking a highly skilled and creative Instructional Designer and Course Developer to join our team. The ideal candidate will be responsible for designing, developing and evaluating engaging and effective learning experiences. This role requires a deep understanding of instructional design principles and proven skills and experience in digital learning/course authoring tools. Experience in developing business simulations with branched scenarios is a plus. Key Responsibilities: Instructional Design: Develop instructional materials, including course outlines, lesson plans, and assessments based on storyboards. Develop measurement/metrics to evaluate learning outcomes and learner progress through a variety of in-course interventions. Design engaging and interactive learning experiences using a variety of instructional methods (e.g., e-learning, blended learning). Course Development: Create high-quality course content, including multimedia elements such as videos, graphics, and interactive activities based on storyboard and scripts. Utilize authoring tools to develop e-learning modules. Ensure all course materials are aligned with standards, instructional goals and learning objectives. Project Management: Manage multiple projects simultaneously, ensuring timely delivery of high-quality instructional materials. Collaborate with subject matter experts (SMEs) to gather content and validate course accuracy. Coordinate with other team members, including graphic designers and technical developers, to produce cohesive learning experiences. Required Skills and Qualifications: Education: Bachelors/Masters degree in any field. Experience: Minimum of 3-5 years of experience in instructional design and course development. Proven track record of designing and developing effective training programs. Technical Skills: Proficiency with e-learning authoring tools (e.g., Articulate Storyline, Adobe Captivate, Camtasia, Synthesia or any AI-based tool etc). Familiarity with Learning Management Systems (LMS) and SCORM/AICC standards. Soft Skills: Excellent written and verbal communication skills. Strong analytical and problem-solving abilities. Ability to work independently and as part of a team. Attention to detail and commitment to producing high-quality work.

Title: Group Leader - Personal Care Level: Sr Manager Qualification: M.Sc in Organic Chemistry, Ph.D. is desirable. Experience: In API Industry for Cosmetics / Personal Care products as Raw Materials / Ingredients 15 years minimum to 22 years. 4-5 Team members will report to this role. Working : Alternate Saturday off. Industry: Fine Chemicals / Speciality / Surfactants Chemicals Mfg for Cosmetics / Personal Care Key Responsibilities include: Assessment of the given Molecule w.r.t. Literature Search , Route Proposition, Cost of Raw Material Contribution Calculation (RMC) Synthesis, execution planning & scheduling of Chemicals as your assigned project. Planning & execution of activities like Vendor Qualification, Generation of specifications for RMs & KRMs Liaising with Procurement to achieve milestones for lab development activity Ensure availability of all required resources for your Projects Lead & troubleshoot the validation of the developed processes in pilot & commercial plant scale.

About The Role Seize the opportunity to work with the team responsible for RTL logic design and microarchitecture of chipsets for PCs millions of people around the world will use. The Chipsets Logic Team, CLIPS is responsible for developing soft IPs, subsystems and gaskets for client and server chipsets.Candidate will be responsible for logic design and development, responsibilities including but not limited to: Develops the logic design, register transfer level (RTL) coding, and simulation for an IP design. Participates in the definition of microarchitecture features of the block being designed. Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for meet the design specification requirements. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Follows secure development practices to address the security threat model and security objects within the design. Supports SOC to integrate and validate the IP on need basis. Drives quality assurance compliance for smooth IPSoC handoff. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Qualifications : BE/ME/Btech/Mtech in computer science eng or electronics and Communications. The candidate must possess a minimum of Bachelor Degree in Electronics Engineering, Computer Engineering, Computer Science or equivalent. The candidate should have successful track record of hardware development experience and demonstrated technical leadership skills. The candidate must have demonstrated the ability to solve highly complex technical problems with excellent communication skills. The candidate must also have demonstrated strong ethical standards. Must also be able to perform in a highly ambiguous and dynamic business environment. Skills : Relevant experience with skills in ASIC IP design flows, RTL coding and Globals (Clocking, Boot/Reset/Fabrics, DfD, Fuse, etc) with experience in CDC, linting, spyglass, micro-architecture. Experience in subsystem design and IO protocols such as AMBA, USB, PCIe, UCIe, UFS, SATA, UART, SPI, I2C, I3C etc is a plus. Other technical requirements: 3 to 8 years of relevant pre-silicon logic design experience in ASIC domain. Experienced with various tools and methodologies including but not limited toSystem Verilog, Python/Perl/Shell scripting, Synopsys tools, RTL model build, design-for-test, design-for-verification. Experienced in EDA tools & flows such as Spyglass VCLINT, VCLP, VC-CDC, SG-DFT, Design Complier, Calibre, Fishtail, FEV, ATPG etc. Experienced in developing micro-architecture based on High Level Architecture specifications. Experienced in VLSI or Structural and Physical design flow and methodology. Experienced in Power-aware design and reviewing validation flows. Strong Chipset or CPU level understanding required on power consumption, power estimation and low power design methods. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intels offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.

Synthesis, purification,characterization of Nucleoside and Nucleotide to develop efficient processes for production,quality,safety,qulity.Use HPLC/NMR/Mass spectrometry.Analyze and interpret data to assess the purity, structure, and identity. Required Candidate profile Ph.D(Organic Chemistry). Process Development Chemist (API), Nucleic Acid Chemist, Peptide Chemist. Hands on experience in synthesis, purification, and characterization of nucleosides and nucleotides.

We are hiring for Senior Research Associate for our Discovery Chemistry Job Description: Position Name- Senior Research Associate Experience - 0 to 2 years Qualification - Ph.D. Organic Chemistry / Medicinal Chemistry Work location - Hyderabad Key Skills and Competencies: Experience in Organic Synthesis/Multi-step Synthesis Handling reactions from mg to KG scale. Sound Knowledge of isolation, separation & purification techniques. Experience in characterization and identification of Organic molecules using spectroscopy techniques like NMR, IR, LCMS, HPLC. Positive and confident individual with strong work ethics. Team player and good communication skills

Available locations - Pune , Mumbai, Hyderabad, Chennai, Kolkata, Gurugram, Bengaluru Role & responsibilities Job Description: Instructional Designer and Course Developer Position Overview: We are seeking a highly skilled and creative Instructional Designer and Course Developer to join our team. The ideal candidate will be responsible for designing, developing and evaluating engaging and effective learning experiences. This role requires a deep understanding of instructional design principles and proven skills and experience in digital learning/course authoring tools. Experience in developing business simulations with branched scenarios is a plus. Key Responsibilities: Instructional Design: Develop instructional materials, including course outlines, lesson plans, and assessments based on storyboards. Develop measurement/metrics to evaluate learning outcomes and learner progress through a variety of in-course interventions. Design engaging and interactive learning experiences using a variety of instructional methods (e.g., e-learning, blended learning). Course Development: Create high-quality course content, including multimedia elements such as videos, graphics, and interactive activities based on storyboard and scripts. Utilize authoring tools to develop e-learning modules. Ensure all course materials are aligned with standards, instructional goals and learning objectives. Project Management: Manage multiple projects simultaneously, ensuring timely delivery of high-quality instructional materials. Collaborate with subject matter experts (SMEs) to gather content and validate course accuracy. Coordinate with other team members, including graphic designers and technical developers, to produce cohesive learning experiences. Required Skills and Qualifications: Education: Bachelors/Masters degree in any field. Experience: Minimum of 3-5 years of experience in instructional design and course development. Proven track record of designing and developing effective training programs. Technical Skills: Proficiency with e-learning authoring tools (e.g., Articulate Storyline, Adobe Captivate, Camtasia, Synthesia or any AI-based tool etc). Familiarity with Learning Management Systems (LMS) and SCORM/AICC standards. Soft Skills: Excellent written and verbal communication skills. Strong analytical and problem-solving abilities. Ability to work independently and as part of a team. Attention to detail and commitment to producing high-quality work.

Being part of DCS group, candidate will be working on PCIe, CXL based Switches, Re-timers and flash controllers for data-centers. Responsibilites: Create Micro-Architecture Specification. Work with team members to design RTL and provide support to verification. Work on constraint development for CDC, RDC and synthesis. Review Test plans from Verification team. Support Emulation and Firmware team in bringup. Qualifications/Requirements Qualifications/Requirements Minimum B.Tech/M.Tech in Electronics or related field. 10+ years of experience in RTL Design and timing aspects of IC design, with leadership capability. Key Skills: Expertise in VLSI logic design, understanding architecture and design planning. Expertise in synthesis/debugging, and timing closure. Knowledge of protocols like PCIe, CXL, AXI, AHB, I3C etc. Proficiency in Tcl and Perl scripting. Power planning and implementation techniques. Proficiency in CDC, RDC and constraint development. Excellent debugging, analytical, and leadership skills. Strong communication skills and interpersonal abilities.

* Perform Sub system level floor planning, placement, and routing for high-performance microprocessor design. * Collaborate with cross-functional teams to achieve design goals. * Close the design to meet timing, power, and area requirements. * Implement engineering change orders (ECOs) to rectify functional bugs and timing issues. * Ensure the quality and efficiency of the RTL to GDS2 implementation process. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8+ years of industry experience Good knowledge and hands on experience in physical design , timing and methodology which include logic synthesis, placement, clock tree synthesis, routing , post route closure. Should be knowledgeable in physical verification ( LVS,DRC. etc) ,Noise analysis, Power analysis and electro migration . Good knowledge and hands on experience in static timing analysis (closing timing at chip level) good understanding of timing constraints . Should have experience in handling asynchronous timing, multiple corner timing closure. Preferred technical and professional experience Automation skills in PYTHON, PERL ,SKILL and/or TCL

About The Role In this role, you will be responsible for Timing methodology definition and closure of designs using industry standard tools for chiplet designs for custom and domain specific products. The chiplets will be leveraged to enable modular design and support multiple products. As part of this team, the candidate will work with leading edge technologies and solutions across multiple domains including SoC multi-die implementations (2.5 and 3D), power delivery, leading edge memory technologies, innovate thermal solutions, on die clocking, and fabrics. The team will also look at options to enhance product power/performance/area/cost thru improved tools and methodologies. The successful candidate would be expected to:Responsibilities1. Drive PV convergence/signoff, including static timing, ERC checks, ECO flows and power analysis2. Defining clock frequencies, PV guard-banding, signoff PV corners, ERC checks, Clock/Reset domain crossing design constraints3. Develop and recommend design methodologies to enable more efficient and faster design convergence4. Scripting in an interpreted language (TCL, py)5. Ability to work independently and at various levels of abstraction6. Strong analytical ability and problem solving skills7. Ability to work effectively with both internal and external teams/customers is expected.8. Strong written and verbal communication skills9. Ability to mentor other engineers and technically guide them."" Qualifications Minimum Qualifications:1. Bachelor/Master degree in CS, CE or EE or equivalent experience2. 10+ years of Physical design experience with a strong understanding of digital circuits and proficiency in static timing analysis (STA) tools like PrimeTime or Innovus.3. Experience with signoff corner selection, PV guard-banding, PV convergence, including static timing and power analysis4. Strong experience in SoC and ASIC design flows on taped out designs5. Expertise in timing closure at block/chip level and ECO flows6. Experience with scripting in an interpreted languagePreferred Qualifications:1. Experience with full chip integration, die-to-die and package integration level timing signoff 2. Hands-on experience with synthesis, block and chip level implementation with industry standard PnR flows and tools 3. Strong experience in CPU and GPU design flows on taped out designs4. Design tools and methods development 5. Capable of working in a high performing team to deliver the results required from the organization. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world. Other Locations IN, Hyderabad Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Msc in Chemistry, Synthetic R&D, Organic Chemistry, API industry, API Pharmaceuticals

About The Role You will be part of ACE India, in the P- Core design team driving Intel's latest CPU's in the latest process technology. In this position, you will be responsible for timing analysis and convergence of complex partitions. Your responsibilities will include but not limited to: 1. Responsible for timing execution and convergence including setup and hold for over 5GHz Freq and low-power digital designs. 2. Deep understanding of Static timing analysis concepts 3. Timing Convergence across all HVM targets 4. Closely work with SD, Integration and Floor plan teams Qualifications Qualifications You must possess a master's degree in electrical or Electronics Engineering with at least 8 or more years of experience in related field or a bachelor's degree with at least 10 years of experience. Technical Expertise in Static Timing Analysis is preferred. Should have minimum of 2 years experience in leading the Team of at least 3-4 people Preferred additional skills Experience of handle complex core design, high-speed designs Timing signoff flows/tools experience both/either Synopsys/Cadence tools Very good knowledge on Timing tools, flows and methodology Ability to handle new feature feasibility studies SD flow knowledge would be plus Familiarity with Verilog/VHDL Tcl, Perl, Python scripting Strong verbal and written communication skills Inside this Business Group The Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core „¢, and critical IPs that power Intel's leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies.

About The Role Come join Intel's highly regarded Devices Development Group, responsible for creating Client SOCs. We envision the future of computing and design for the next generation of laptop and desktop computers. We are looking for a SoC Physical Design Engineer, who is ready to research, design, develop, and test lead Intel designs as we reimagine how to build SoCs at Intel and in the semiconductor industry. Our bold purpose as a company is to create world-changing technology that enriches the lives of every person on earth and this role is instrumental in furthering our mission to shape the future of technology. Your responsibilities may include but not be limited to: Performing physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Physical Synthesis, Floor planning, Place and Route, Clock Tree Synthesis with Synopsys and/or Cadence EDA tools. Multiple Power Domain analysis and handling using standard Power Formats UPF or CPF. Verification and Signoff including Formal Equivalence Verification, Static Timing Analysis, Reliability Verification, Static and Dynamic power integrity, Layout Verification, Electrical rule checking, Noise analysis and Structural Design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Participating in the development and improvement of physical design methodologies and flow automation. Driving performance optimization, including co-optimization, work with process teams, to create best-in-class designs. The ideal candidate should exhibit behavioral traits that indicate: Self-motivator with strong problem-solving skills. Excellent interpersonal skills, including written, verbal, and presentation communications. Attention to detail and organizational skills. Ability to work as part of a team and collaborate in a high-paced atmosphere. Qualifications BS/BTech degree with 12 years of experience, or MS/MTech degree with 10 years of experience, in Electronics Computer Engineering, or a related field. Preferred Qualifications: At least 10+ years of experience in physical design using industry EDA tools. Experience in Python/Perl/TCL programming languages Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

About The Role About The Role :The world is transforming - and so is Intel. Here at Intel, we believe the world needs technology that can enrich the lives of every person on earth. We work every single day to design and manufacture silicon products that empower peoples digital lives. Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver solutions for products that impact customers lives? If so, Come join us to do something wonderful.Your responsibilities will include but not limited to: Oversees definition, design, verification, and documentation for SoC (System on a Chip) development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs all aspects of the SoC design flow from highlevel design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development. Qualifications You must possess the below minimum qualifications to be initially considered for this position Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidatesMinimum QualificationsCandidate will have a Bachelors degree in Computer Engineering/ Computer Science or Electrical Engineering with 6+ years of experience -OR- a Masters degree in Computer Engineering Computer Science or Electrical Engineering with 4+ years of experience with C and Object Oriented Software design including algorithms and data structures. Knowledge of Software development practices and quality standards. Experience with Unix Windows based SW development tools. Experience developing bus functional models for unit level verification or Verification IP development. Preferred Qualifications:- Proficiency in System C SystemVerilog UVM and ESL modeling methodologies Proficiency in HW design and verification methodologies Working knowledge of highspeed HW protocols eg PCIe DDR Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world.

About The Role Come join Intel's highly regarded Devices Development Group, responsible for creating Client SOCs. We envision the future of computing and design for the next generation of laptop and desktop computers. We are looking for a SoC Physical Design Engineer, who is ready to research, design, develop, and test lead Intel designs as we reimagine how to build SoCs at Intel and in the semiconductor industry. Our bold purpose as a company is to create world-changing technology that enriches the lives of every person on earth and this role is instrumental in furthering our mission to shape the future of technology. Your responsibilities may include but not be limited to: Performing physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Physical Synthesis, Floor planning, Place and Route, Clock Tree Synthesis with Synopsys and/or Cadence EDA tools. Multiple Power Domain analysis and handling using standard Power Formats UPF or CPF. Verification and Signoff including Formal Equivalence Verification, Static Timing Analysis, Reliability Verification, Static and Dynamic power integrity, Layout Verification, Electrical rule checking, Noise analysis and Structural Design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Participating in the development and improvement of physical design methodologies and flow automation. Driving performance optimization, including co-optimization, work with process teams, to create best-in-class designs. The ideal candidate should exhibit behavioral traits that indicate: Self-motivator with strong problem-solving skills. Excellent interpersonal skills, including written, verbal, and presentation communications. Attention to detail and organizational skills. Ability to work as part of a team and collaborate in a high-paced atmosphere. Qualifications BS/BTech degree with 8 years of experience, or MS/MTech degree with 6 years of experience, in Electronics Computer Engineering, or a related field. Preferred Qualifications: At least 8+ years of experience in physical design using industry EDA tools. Experience in Python/Perl/TCL programming languages Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Greetings From Dexcel Designs! We are inviting applications for FPGA Design and Verification Engineer Job Overview: We are seeking FPGA Design and Verification Engineers with 3-6 years of experience in RTL design, FPGA verification, and high-speed interface development . This role involves designing, implementing, and validating FPGA-based systems while working closely with cross-functional teams in hardware and embedded software development. Key Responsibilities: Develop and implement RTL designs for FPGA-based systems. Perform functional verification and validation of FPGA designs. Work on timing analysis, synthesis, and debugging of FPGA architectures. Collaborate with hardware, embedded software, and system architects to ensure seamless integration. Debug FPGA designs using industry-standard tools and methodologies . Technical Skills Required: Strong understanding of RTL design (Verilog/VHDL) and FPGA implementation. Experience with FPGA tools such as Vivado, Quartus, Synplify, ModelSim, and QuestaSim . Hands-on experience with at least one of the following high-speed interfaces : PCIe, SATA, USB, DisplayPort, JESD204B, SRIO MII/RMII/GMII/RGMII/SGMII/XAUI/RXAUI DDR/LPDDR/DDR2/DDR3, QDR memories Knowledge of FPGA debugging techniques, timing closure, and constraint handling . Preferred Skills: Experience in FPGA-based hardware design and testing . Exposure to SoC architectures and system-level integration . GFPGA Design and Verification Engineer ) and power integrity (PI) analysis .G

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 10121 Date posted 03/21/2025 Job description (VC Spyglass Lint Technology on VC Platform) Responsible for designing, developing, troubleshooting the core VC-Static engine, which is integral part of Lint Design and develop Lint standard and customized Lint checks using VC Platform technologies for analysis, synthesis and simulations. Will be working closely with other teams both locally and globally Design and development of state of the art EDA tools involving development in one or more of the following areas-: developing new and innovative algorithms in the area of electronic design automation. Skills Required 4 to 10 years of Software development experience Familiarity with ASIC design flow and the EDA tools and methodologies used therein. Fluent in C++ with work experience in data-structures and algorithms. Excellent algorithm analysis skills and a good knowledge of data structures. Good knowledge of Tcl and Perl-based development on Unix. Good knowledge of Verilog, SystemVerilog & VHDL HDL. Ability to develop new architecture Knowledge on GenAI is Value added Self-motivation, self- discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success Quality focus – one who believes in quality and wants to make a difference Experience of production code development on Unix/Linux platforms. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Responsibilities: Planning integrated circuit and processor design projects and stages. Collaborating on circuit engineering projects with the design team. Designing layouts for processors and controller architectures. Reviewing product requirements and logic diagrams. Developing prototypes, testing circuit designs, and optimizing output. Enabling easy routing, as well as reducing delays and resolving glitches. Developing codes, as well as maintaining layout automation features and macros in layout entry tools. Evaluating semiconductor devices and components, as well as performing modifications. Documenting physical design processes, such as circuit layouts and device specifications. Keeping informed of developments and innovation in physical design engineering. Position Requirements: VLSI with experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development. Candidate must have experience with ICC Innovus tool and he must have worked less than 7nm technology. RTL Design using Verilog is a must. System Verilog experience and experience with UVM based environment usage debugging is required. Prior experience in IP development teams would be an added advantage. BE B.Tech/ ME M.Tech - Electrical Electronics Physical Design 5 plus years - 12 years Design Verification - 5 plus years - 12 years DFT - 5 plus years - 12 years RTL - 5 plus years - 12 years STASynthesis - 5 plus years - 12 years

Role & responsibilities 1. Background in chemistry, preparation and application of typical water based resin/emulsions used in the field of preferably inks and coatings 2. Initiate and lead projects to develop and implement resins in SWs portfolio aiming at improving the performance, application properties and cost-efficiency of inks and coatings 3. Experience in applying different analytical methods required to chemically characterize polymers and their performance in typical ideally ink and coatings application Continuous scouting, evaluation and analysis of new technology trends by constant exchange with raw material producers, research institutes, literature screening, visiting trade fairs, etc. in order to identify and anticipate industry technology trends and bringing them into SW organization. 5. Ensure the practice are conducted according to best industry standards, by managing all necessary resources (staff, materials and equipment), in order to provide state-of-the-art solutions, with respect of time and cost targets. 6. Manage the reporting and the related documentation on technology developments progress in compliance with defined professional and company standards Preferred candidate profile 1. University degree (PhD Preferred) 2. Specialisation in polymer chemistry or organic synthesis 3.Proven experience in resin development for ideally inks and coatings 4.Min. 5 years comprehensive experience in defined technology environment (R&D, application service etc.) Perks and benefits Best in the industry

As an FPGA & Board Design Engineer, you must develop new hardware designs, including system design, CPLD/ FPGA or processor design, and board-level analog/ digital circuit design for embedded systems/ boards. You have to develop detailed specifications based on requirements and implement Hardware designs in accordance with those defined requirements and/or specifications. Your duties include Schematic design generation and entry, netlist generation, and close interaction with the CAD team for layout review and feedback. Perform simulation activities including timing analysis, behavioural, and functional simulations. Develop test benches and other test tools as needed to complete the verification of FPGA designs. Carry out proto H/W bring-up with support from firmware engineers. REQUIREMENTS B.Tech. or M.Tech. EE with 2+ years of FPGA experience including implementation, synthesis, and timing closure. Proficiency in Verilog, VHDL and System Verilog. Proficiency in Synopsys Synplify, Xilinx Vivado, ISE Hands-on with FPGA debug methodologies, such as ChipScope. Proficient in Schematic capture tools like Orcad/Altium Hands-on experience with lab debug equipment such as oscilloscopes and logic analyzers. Strong scripting skills in Perl/Python. Experience in test bench design and implementation Knowledge of high-speed interfaces including PCIe, Ethernet, and DDR3/4. Knowledge of low-speed interfaces including SPI, IIC, and UART. Knowledge and experience designing with Altera and Xilinx FPGAs. Detail-oriented individual with good interpersonal skills and excellent written and verbal communications skills.

Required MSC Chemistry with 2 to 4 years experience in organic chemistry in Chemical industry To carry out R&D expertise in lab & Pilot plant, To oversee job work. Required Candidate profile Literature work, regulatory work ( reach, DSIR etc.) Technical data management Maintening SDS,TDS folder, Luba & Mining data Making CoA/Analytical reports