2263 Synthesis Jobs - Page 26

SoC Physical Design Engineers We need experienced engineers to work on the Physical Design & Implementation of SoCs in cutting edge technology and with complex functionality. Skills: 3+ years of relevant experience in Block/SoC level Physical Design. Experience in Block/SoC Physical Design in the following topics: PnR tools like ICC2/Innovus with regards to physical/timing convergence 14nm / 10nm / 7nm / 5nm process nodes Tapeout sign-off experience is a must using industry standard tools. Cadence Encounter/Synopsys ICC2 tool set SDC, STA and Equivalence checking Flow automation exposure will be an added advantage. Working knowledge of Unix, Linux and SKILL, Shell/Python Script ability. Quick learner with excellent interpersonal, verbal/written communications, problem solving and decision-making skills Traits: Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency. Solutions orientation; Quality driven; Execution minded

Date: 8 Jul 2025 Location: Bangalore, KA, IN, 560099 Custom Field 1: Discovery Services Mandatory expectation for all roles as per Syngene safety guidelines Overall adherence to safe practices and procedures of oneself and the teams aligned Contributing to development of procedures, practices and systems that ensures safe operations and compliance to company’s integrity & quality standards Driving a corporate culture that promotes environment, health, and safety (EHS) mindset and operational discipline at the workplace at all times. Ensuring safety of self, teams, and lab/plant by adhering to safety protocols and following environment, health, and safety (EHS) requirements at all times in the workplace. Ensure all assigned mandatory trainings related to data integrity, health, and safety measures are completed on time by all members of the team including self Compliance to Syngene’s quality standards always Hold self and their teams accountable for the achievement of safety goals Govern and Review safety metrics from time to time Core Purpose Of The Role Personnel handling this profile will be responsible for conducting reactions and delivering final compounds within a fast turnaround time, meeting the specific requirements of both the project and Syngene. The candidate should be capable of independently solving chemistry problems. He or she should ensure that the experimental observations are recorded contemporaneously and in compliance with the Electronic Laboratory Notebook (ELN) policies of the project and Syngene. Role Accountabilities Perform synthetic chemistry reactions, reaction workups, purification of the compounds by column chromatography, crystallization, re-crystallization techniques, preparative TLC and operating lab equipments’ Ensure that the samples generated during synthesis are given for analysis and record subsequent results obtained and update the supervisor / group leader on the progress of synthesis and ensure samples are packed appropriately for shipment Record the observations of experiment/reaction, results, utilization of resources and other activities related to the reaction in the laboratory or e-notebook following guidelines and in timely manner and ensure that the same is handled safely and confidentially. The candidate should be capable of meeting Syngene’s productivity expectations (# of compounds/month and # of steps/month) without compromising on safety and quality. The candidate should be capable of synthesizing the final compounds at a faster turnaround time The candidate should have excellent analytical interpretation and purification skills Ensure that they know the SDS of the chemicals they are handling and aware of emergency response procedures in case of accidental spillage, leakage or fire and ensure proper waste segregation as per EHS norms Always follow EHS and quality system requirements in the workplace ensuring individual safety and lab safety Attend all mandatory trainings and update training records as and when trainings are completed Always ensure confidentiality Syngene Values All employees will consistently demonstrate alignment with our core values Excellence Integrity Professionalism Specific requirements for this role Experience Up to 5 years Skills And Capabilities Should have deeper knowledge with concepts of organic synthesis and reaction mechanisms Candidate should be capable of solving synthetic problems independently Should be excellent in purification and analytical interpretation skills. Familiar with operations of relevant apparatus - instrument / equipment. Education M.Sc in general or organic chemistry

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description Key Responsibilities Lead block-level PNR activities from floorplanning through final routing, ensuring robust physical implementation aligned with timing, power, and area goals. Drive power grid design and EM/IR-aware routing strategies to ensure block-level power integrity and reliability. Collaborate closely with timing closure engineers to resolve physical design bottlenecks impacting timing and signal integrity. Manage and optimize physical verification flows including DRC, LVS, antenna checks, and physical signoff. Automate PNR flows and develop scripts to improve productivity and design quality. Mentor and guide junior physical design engineers, fostering technical growth and best practices. Coordinate with cross-functional teams including RTL design, STA, verification, and backend integration to ensure seamless block-to-chip integration. Qualifications 8+ years of experience in physical design with a strong focus on block-level Place and Route (PNR) for complex SoC/IP subsystems, preferably at advanced technology nodes (16nm, 7nm, 5nm, or below). Proven expertise in block-level physical implementation including floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification (DRC/LVS). Hands-on experience with industry-standard PNR tools such as Cadence Innovus, Synopsys ICC2, and Mentor Calibre. Strong understanding of power grid design, EM/IR analysis, signal integrity (SI), and reliability checks at the block level. Experience in managing timing closure in coordination with STA teams, resolving congestion, and optimizing for power, performance, and area (PPA). Proficiency in scripting languages (Tcl, Python, Perl) for flow automation and custom tool development. Demonstrated ability to lead block PNR efforts, coordinate with RTL designers, physical design teams, and verification groups to meet aggressive tapeout schedules. Familiarity with low-power design techniques and power-aware physical implementation. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. I'm interested Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Job Description Roles and Responsibilities To perform product lifecycle management tasks for externally supplied products and own production products like evaluation of change controls, deviations, temperature excursions, stability data, process validation documents from Product quality point of view. Handling of problem-solving cases for products (includes both analytical and formulation related changes which have impact on product quality). Overall product quality evaluation and provide input during supplier's meetings. Follow up with suppliers and/or other stakeholders for documents related to changes for externally supplied products. E.g., possible impurities in API and finished products risk assessment in line with updated guidelines. Requesting, follow-up and tracking of Product Quality Review (PQRs) related data. Preparation and evaluation of Product Quality Review (PQRs) for externally supplied products, related coordination and follow-up with suppliers and other stakeholders. Writing of Product Quality Review (PQRs) for own production products and ensure its timely approval. Preparation and review of other documents related to Product Quality Review (PQRs). Responsible for planning stability studies, writing and/or review of stability protocols, reports and preparation of technical documents in CTD format. Co-ordinate and follow up stability studies at CROs/CQC. Writing and/or reviewing of process validation, technology transfer, study batch documentation for own products. Write/check/review pharmaceutical documents as per regulatory requirements. Candidate having knowledge of theoretical and/or possible Physico-chemical risks for products based on appropriate available data (E.g., evaluation of synthesis route of API, excipients, packaging materials details etc.) will be an added advantage. Write documents into Orion’s IT systems. Preparation and maintenance of lists/documents/records and archiving at appropriate place. Co-ordination with other departments / partners. Achievements of responsibilities within the agreed timelines. To assist the overall working of Indian Pharmaceutical team. Other possible tasks appointed by Supervisors. Note: We do not have own laboratories in India! Primary Skills (essential) Minimum 4 years' experience in Formulation R&D or API R&D activities in global Pharma industry Knowledge of organic chemistry/ Pharmaceutical medicinal chemistry/ synthetic chemistry will be an added advantage Ability to analyze the impact of change on Nitrosamine and/or other relevant physico-chemical risks assessment, if possible. Confirmed knowledge of EU requirements and ICH guidelines Candidate having interest and/or experience in pharmaceuticals documentation or any relevant pharmaceutical formulation / manufacturing related documentation will be preferred. Practical development skills from the laboratory to the production scale concerning different types of formulations (tablets, capsules, liquids, etc.) will be considered as an added advantage. Fluency in oral and written English Task oriented with learning attitude and Teamwork skills Confirmed skills of Microsoft Office are essential This job offers An excellent opportunity to work in an inspiring and important role in the area of Pharmaceuticals Great opportunity to become part of the wholly owned subsidiary of globally operating Orion Group Possibility to utilize your own strengths with the support of professionals Flexible, high spirit working environment where your skills are appreciated Good work-life balance Clear, transparent processes and responsible supervisors are our benefits to the personnel Education Bachelors/master's degree in pharmacy from a reputed College/University or Master's degree in chemistry from a reputed College/University At Orion, your work creates true impact and well-being for our customers, patients and society at large. Our culture of friendliness, respect, mutual appreciation and diversity creates a safe working environment where you can strive for excellence. We offer a wealth of career paths and development opportunities that support the development of innovative solutions and improving the quality of life. Please visit our website to find further information about our values and Orion as an employer https://www.orion.fi/en/careers/orion-as-an-employer/ . How To Apply And Additional Information Please fill Candidate Information Form on https://forms.gle/o9BhfmhigBcyp5fy7 & email your CV to recruitmentindia@orion.fi Required documents: CV/Resume Application deadline: 31.07.2025 About Us Orion is a globally operating Finnish pharmaceutical company – a builder of well-being for over a hundred years. Orion provides meaningful work for more than 3 600 Orionees in Finland and abroad. Orion is known as a responsible and reliable employer where we value each other, strive for the best and build for tomorrow. We develop, manufacture and market human and veterinary pharmaceuticals and active pharmaceutical ingredients. Orion has an extensive portfolio of proprietary and generic medicines and consumer health products. The core therapy areas of our pharmaceutical R&D are oncology and pain. Proprietary products developed by Orion are used to treat cancer, neurological diseases and respiratory diseases, among others.

Experience: 5 - 15 years Location : Hyderabad Required Experience Experience in EMIR signoff at block and SoC level. Good understanding of IR/Power-Domain-Network signoff at SOC & block level Experience in RHSC tool Good at scripting – Python Must have knowledge of Physical Implementation (Synthesis and Place & Route) Effective communication Strong analytical and problem solving abilities

Role & responsibilities Process Development: Conduct research and design experiments to develop and optimize synthetic routes for API molecules. Perform literature searches for identified API molecules to determine synthesis routes, polymorphs, and analytical methods. Conduct experimental trials to assess feasibility and optimize designed synthetic routes for API molecules. Documentation: Record all experiments in the laboratory notebook (LNB) and maintain corresponding analytical data in organized folders. Design synthetic routes for the synthesis and isolation of impurities and reference standards. Ensure all documentation meets Good Manufacturing Practices (GMP) and regulatory standards. Safety and Compliance: Adhere to all safety protocols and ensure a safe working environment in the laboratory. Develop non-infringing synthetic processes based on literature, raw material availability, and polymorph studies. Stay up-to-date with industry trends, regulatory guidelines, and advancements in chemical synthesis and analytical techniques.Team Collaboration: Plan daily activities for team members, focusing on feasibility studies, process optimization, and laboratory validation. Work closely with the Analytical Research and Development (ARD) team on method development, in-process testing, and reference standards qualification. Qualifications: Education: MSc/BSc in Organic Chemistry, Experience: Fresher or 1-2 years experience in process development and optimization in the pharmaceutical or bulk drug industry. Skills: Strong knowledge of synthetic organic chemistry and process chemistry. Proficiency in using and interpreting data from analytical instruments. Excellent problem-solving skills and attention to detail. Effective communication and teamwork skills. Ability to work independently and manage multiple projects simultaneously. Preferred candidate profile We are looking for a talented and driven junior R&D Associate to join our team. The successful candidate will be responsible for developing and optimizing chemical processes for synthesizing active pharmaceutical ingredients (APIs). This role requires a strong background in synthetic organic chemistry, process development, and scale-up techniques. The R&D Chemist will collaborate with cross-functional teams to ensure the smooth transition of processes from the lab to full-scale production. Perks and benefits

Job Summary Key Responsibilities  Lead block-level PNR activities from floor planning through final routing, ensuring robust physical implementation aligned with timing, power, and area goals.  Drive power grid design and EM/IR-aware routing strategies to ensure block-level power integrity and reliability.  Collaborate closely with timing closure engineers to resolve physical design bottlenecks impacting timing and signal integrity.  Manage and optimize physical verification flows including DRC, LVS, antenna checks, and physical signoff.  Automate PNR flows and develop scripts to improve productivity and design quality.  Mentor and guide junior physical design engineers, fostering technical growth and best practices.  Coordinate with cross-functional teams including RTL design, STA, verification, and backend integration to ensure seamless block-to-chip integration. Qualifications and Skills 8+ years of experience in physical design with a strong focus on block-level Place and Route (PNR) for complex SoC/IP subsystems, preferably at advanced technology nodes (16nm, 7nm, 5nm, or below).  Proven expertise in block-level physical implementation including floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification (DRC/LVS).  Hands-on experience with industry-standard PNR tools such as Cadence Innovus, Synopsys ICC2, and Mentor Calibre.  Strong understanding of power grid design, EM/IR analysis, signal integrity (SI), and reliability checks at the block level.  Experience in managing timing closure in coordination with STA teams, resolving congestion, and optimizing for power, performance, and area (PPA).  Proficiency in scripting languages (Tcl, Python, Perl) for flow automation and custom tool development.  Demonstrated ability to lead block PNR efforts, coordinate with RTL designers, physical design teams, and verification groups to meet aggressive tapeout schedules.  Familiarity with low-power design techniques and power- aware physical implementation.

Job Summary Static Timing Analysis (STA) & Place and Route (PNR) Key Responsibilities  Lead STA and PNR activities for complex subsystems, ensuring robust timing closure and physical implementation with a focus on power, performance, and area optimization.  Develop and refine methodologies for STA and PNR tailored to the unique challenges of large, multi-interface, or mixed-signal subsystems.  Drive automation and validation of timing and physical design data across subsystem boundaries.  Mentor and guide junior engineers, fostering technical growth and knowledge sharing within subsystem teams.  Collaborate cross-functionally to resolve design, timing, and physical implementation challenges specific to complex subsystem integration.  Exhibit excellent communication skills to present technical solutions and lead discussions with internal teams and customers, especially regarding subsystem-level trade-offs and integration Qualifications and Skills 10+ years of experience in Static Timing Analysis (STA) and Place and Route (PNR) for complex subsystems within ASIC/SoC design, including advanced technology nodes (7nm, or below).  Demonstrated expertise in STA tools (e.g., Synopsys PrimeTime, Cadence Tempus) and PNR tools (e.g., Synopsys ICC2, Cadence Innovus) applied to large, multi-block or hierarchical subsystems.  Proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems.  Proficient in scripting languages (Tcl, Perl, Python) for automating STA and PNR flows across multiple subsystem blocks.  Deep understanding of SoC design flows, with experience collaborating across frontend, physical design, and verification teams to integrate complex subsystems.  Experience with IP collateral generation and quality assurance for timing and physical design at the subsystem level preferred.  Background high-speed interfaces, or mixed-signal SoC subsystems

Job Summary Key Responsibilities  Lead block-level PNR activities from floorplanning through final routing, ensuring robust physical implementation aligned with timing, power, and area goals.  Drive power grid design and EM/IR-aware routing strategies to ensure block-level power integrity and reliability.  Collaborate closely with timing closure engineers to resolve physical design bottlenecks impacting timing and signal integrity.  Manage and optimize physical verification flows including DRC, LVS, antenna checks, and physical signoff.  Automate PNR flows and develop scripts to improve productivity and design quality.  Mentor and guide junior physical design engineers, fostering technical growth and best practices.  Coordinate with cross-functional teams including RTL design, STA, verification, and backend integration to ensure seamless block-to-chip integration. Qualifications and Skills 8+ years of experience in physical design with a strong focus on block-level Place and Route (PNR) for complex SoC/IP subsystems, preferably at advanced technology nodes (16nm, 7nm, 5nm, or below).  Proven expertise in block-level physical implementation including floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification (DRC/LVS).  Hands-on experience with industry-standard PNR tools such as Cadence Innovus, Synopsys ICC2, and Mentor Calibre.  Strong understanding of power grid design, EM/IR analysis, signal integrity (SI), and reliability checks at the block level.  Experience in managing timing closure in coordination with STA teams, resolving congestion, and optimizing for power, performance, and area (PPA).  Proficiency in scripting languages (Tcl, Python, Perl) for flow automation and custom tool development.  Demonstrated ability to lead block PNR efforts, coordinate with RTL designers, physical design teams, and verification groups to meet aggressive tapeout schedules.  Familiarity with low-power design techniques and power- aware physical implementation.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Description Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in. You will be joining a successful engineering team whose deliveries can be found in billions of mobile, compute and IoT products worldwide. Based out of Qualcomm's Bangalore office, this role offers a position in Low Power controller IP cores and subsystem digital design targeted for variety of industry leading Snapdragon SoCs for mobile, compute, IoT and Automotive markets. Key Responsibilities Micro-architecture and RTL design for Cores / subsystems. Work in close coordination with Systems, Verification, SoC, SW, PD & DFT teams for design convergence. Enable SW teams to use HW blocks. Qualify designs using static tool checks including Lint, CDC, LEC and CLP. Synthesis, LEC and Netlist CLP Report status and communicate progress against expectations. Preferred Qualifications 5 to 10 years of strong experience in digital front end design (RTL design) for ASICs Expertise in RTL coding in Verilog/SV/VHDL of complex designs with multiple clock domains and multiple power domains Familiar with UPF and power domain crossing Experience in Synthesis, Logical Equivalence checks, RTL and Netlist CLP Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI Experience in low power design methodology and clock domain crossing designs Experience in Spyglass Lint/CDC checks and waiver creation Experience in formal verification with Cadence LEC Understanding of full RTL to GDS flow to interact with DFT and PD teams Expertise in Perl/TCL/Python language Experienced in database management flows with Clearcase/Clearquest. Expertise in post-Si debug is a plus Excellent oral and written communications skills to ensure effective interaction with Engineering Management and team members. Team player, self-motivated, should be able to work with minimal supervision. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Description Invent the future with us. Recognized by Fast Company’s 2023 100 Best Workplaces for Innovators List, Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a passionate and growing team — we’d love to have you apply! About The Role Ampere Computing is looking for a qualified design engineer on power analysis, optimization, and validation, to contribute in designing our high-performance power-efficient microprocessor chipset. This person will be a part of the Silicon Engineering team and work across multiple groups to drive the power requirements, and power optimization from micro-architecture to final silicon. In this role, you will be at the forefront of AI innovation, building AmpereOne Aurora, our groundbreaking AI compute solution. Aurora combines high-performance general-purpose CPUs with integrated AI capabilities, offering a compelling combination of efficiency and market reach. This revolutionary product is poised to deliver superior performance while consuming significantly less power. Power analysis engineer is expected have strong CMOS design fundamentals and deep knowledge of power reduction techniques at various levels of abstraction. Expertise in analyzing the results given by various power estimation tools and create actionable items for power reduction. Experience in developing flows and post processing scripts to help in analysis and rollup. What You’ll Achieve Setup power analysis environment for at the RTL-level, and gate-level for power analysis of all design blocks at the pre-silicon stage. Determine tests and benchmarks to run on all blocks for pre-silicon power analysis Develop tests in DV test environment to certain use cases interesting for power analysis and reduction Run and review power analysis reports at the RTL-level and gate-level on all design blocks. Identify areas of improvements at the architecture-level, RTL-level, and synthesis. Analyze power from activities from workloads run on emulation environment Determine power optimization budgets for all blocks, and setup runs to validate them as the design progresses. Understand the different CPU use cases, Memory and Pcie workloads. Work with industry standard power analysis tools like Spyglass/Power Artist/Joules/PrimePower etc. Maintain and improve existing power modeling and analysis flows. About You Experience with power analysis using gate-level and RTL-power analysis tools Good understanding of power analysis and optimization on CMOS designs Good understanding of clock-gating, power-gating, DVFS, etc. used for power optimization Good understanding of processor designs, processor work-loads. Solid programming and scripting skills using Perl/Python/Tcl Experience running power analysis on activity from emulation environment Owned CPU or SOC design blocks and familiar with design flows (synthesis, place & route, power, timing, EM/IR) Owned power analysis methodology and/or automation in previous role Hands-on working experience with Power analysis tools and flows (one or more of the following industry-standard tools: Primepower, PTPX, Power Artist, Joules, Voltus) Advanced knowledge of Python, TCL and shell scripting M.Tech in Electronics Engineering or Computer Engineering with 6+ years of semiconductor experience or B.Tech in Electronics Engineering or Computer Engineering with 8+ years of semiconductor experience What We’ll Offer At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits Highlights Include Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process. Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts is a plus. Experience creating padring and working with the chip level floorplan team is an added advantage. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3069772

Join the leader in entertainment innovation and help us design the future. At Dolby, science meets art, and high tech means more than computer code. As a member of the Dolby team, you’ll see and hear the results of your work everywhere, from movie theaters to smartphones. We continue to revolutionize how people create, deliver, and enjoy entertainment worldwide. To do that, we need the absolute best talent. We’re big enough to give you all the resources you need, and small enough so you can make a real difference and earn recognition for your work. We offer a collegial culture, challenging projects, and excellent compensation and benefits, not to mention a Flex Work approach that is truly flexible to support where, when, and how you do your best work. The Advanced Technology Group (ATG) is the research division of the company. ATG’s mission is to look ahead, deliver insights, and innovate technological solutions that will fuel Dolby’s continued growth. Our researchers have a broad range of expertise related to computer science and electrical engineering, such as AI/ML, algorithms, digital signal processing, audio engineering, image processing, computer vision, data science & analytics, distributed systems, cloud, edge & mobile computing, computer networking, and IoT. We are seeking a talented Researcher to join our Advanced Technology Sight Research Lab. You will bring your experience in generative AI on computer vision tasks and deep learning technology to Dolby. As a prerequisite for your work, you have proven knowledge of the generative network (VAE, GAN, diffusion model), low-level/high-level computer visions, 2D/3D scene representation and reconstruction, and deep learning. Your solid understanding of trade-offs between computational complexity and achieved performance of different implementations will guide you in decisions. You will: Research and develop new neural network architectures, training methods, representation, and processing algorithms on the areas of modern computer vision. Have an in-depth understanding of the key processes in computer vision. You have extensive experience in developing architectures, VAE/GAN/diffusion-based network, multi-modal generative network, image/video generative restoration/enhancement, 3D novel view synthesis, and deep learning solution to improve performance of computer vision tasks. Join a highly skilled and motivated team to research and develop advanced computer vision and processing technologies to improve end user experience. What will you accomplish: Build cutting-edge technology in the areas of Computer Vision, AI and Deep Learning . Develop new neural network architectures, training methods, representation, and processing algorithms Creates early-stage conceptual models that demonstrate feasibility. Document and present the new architectures and algorithms in various forms, such as technical white papers and internal meeting Maintain the highest technical and moral integrity for Dolby in the workplace and marketplace. Skills, Education, And Experience Required Ph.D. degree in electrical engineering, computer engineering, or computer science. Minimum of 2 years of experience in developing algorithms for generative neural network, multi-modal tasks, generative 2D/3D computer vision tasks. You are familiar with computer graphics, video processing systems, as well as corresponding software in consumer and professional products. Solid background in the latest AI technologies and their applications to image research. Proficient in Matlab, C/C++, OpenCV, and Python (TensorFlow/PyTorch) programming applied to computer vision is required. Self-motivated, quick learner and business partner with ability to work with minimal supervision. Excellent written and verbal communication skills. It is highly desirable to have one or more of the following: Experience in filing patents of newly developed technologies. Hands-on experience in applying Generative Network, Computer Vision, and Machine Learning algorithms to real-world problems Proven track record of successful research accomplishments, published papers, and/or patent applications in the field of video encoding and processing. Note: All official communication regarding employment opportunities at Dolby will come from an official dolby.com email address. We will never request payment as part of the hiring process. If you receive a suspicious message, please verify its authenticity before responding.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SMTS SILICON DESIGN ENGINEER The Role The position will involve working with a very experienced CPU physical design team. The person is responsible for delivering the physical design of critical CPU units to meet challenging goals for frequency, power, and other design requirements for AMD's next-generation processors in a fast-paced environment with cutting-edge technology. The Person Engineer with a good attitude, strong analytical skills, effective communication, and excellent problem-solving abilities. Key Responsibilities Own critical CPU units and drive to convergence from RTL-to-GDSII - synthesis, floor-planning, place and route, timing closure, and signoff Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoffs for design closure. Develop and improve physical design methodologies and customize recipes across various implementation steps to optimize PPA. Implement floor plan, synthesis, placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), EM/IR and signoff. Handling different PNR tools - Synopsys fusion compiler, Cadence, PrimeTime, StarRC, Calibre, Apache Redhawk Preferred Experience 12+ years of professional experience in physical design, preferably with high-performance designs. Must have closed high-performance IPs- CPU/GPU/DPU/memory controller, etc. Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality; familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow - Perl/Tcl/Python Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in advanced sub 7nm nodes Excellent physical design and timing background. A good understanding of computer architecture is preferred. Strong analytical/problem-solving skills and pronounced attention to detail. Academic Credentials Qualification: Bachelors or Masters in Electronics/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Join the leader in entertainment innovation and help us design the future. At Dolby, science meets art, and high tech means more than computer code. As a member of the Dolby team, you’ll see and hear the results of your work everywhere, from movie theaters to smartphones. We continue to revolutionize how people create, deliver, and enjoy entertainment worldwide. To do that, we need the absolute best talent. This is an opportunity to play a key role in Dolby's new R&D Center in Bangalore as a Senior Research Manager in our Advanced Technology Group " ATG ", the research and technology arm of Dolby Labs. With multiple competencies that innovate on technologies in audio, video, AR/VR, gaming, music, broadcast and user-generated content, areas of expertise related to computer science and electrical engineering, such as AI/ML, computer vision, data science & analytics, distributed systems, cloud, edge & mobile computing, natural language processing, social network analysis, and computer graphics are highly relevant to our research. What You’ll Do As a Senior Manager within Dolby ATG research, you focus on three key areas of responsibility: State-of the art, cutting edge, hands-on research: As a researcher, you will invent and develop the next generation of AI driven image and video analysis, enhancement, and processing technologies. Jointly with Dolby’s world-class global research teams, you will set directions, identify projects, and build the next wave of image technologies driving Dolby’s cloud and licensing business. With a solid understanding of both traditional image processing and newer AI technologies, you will not only perform research using signal processing based only solutions, but you will also work at the intersection of classical image processing and new AI algorithms. You will apply these insights to the research of image delivery, analysis, and content creation technologies. Managing, nurturing, and grooming top research talent: As a senior leader, you will manage and mentor a small group of researchers working in image processing, computer graphics, computer science, and content enhancement. You will work with your team as a coach and mentor. You are passionate about developing junior, highly talented staff into researchers that work fully independently in a corporate environment. Contribute to developing a dynamic, flexible, transparent, results-oriented and innovative working atmosphere. Technology strategy and direction setting: Jointly with Dolby’s world-class global research teams, you will set directions, identify projects, and build the next wave of AI based technologies driving Dolby’s cloud and licensing business. You work with ATG technology leaders to co-define projects and assign your staff to global R&D initiatives led by other technology initiative leads. Work jointly with upper management, lead resource and work allocation. You will also work with Dolby’s Business Groups (BG) to bring the research to life in many products, working closely with product managers, program managers, and BG engineering teams worldwide. Education And Desired Experience Ph.D. plus 5-10 years of corporate research experience with a degree in Physics, Electrical Engineering, Mathematics, Computer Science. Very deep understanding and strong record of research in Computer Vision, image analysis, enhancement, compression, and processing technologies. You are an absolute top expert in AI with a deep and thorough theoretical understanding of the latest state-of the art AI technologies. You have a detailed understanding of all main network architectures, deployment modes, data augmentation and preparation, and theoretical performance analysis of model architectures. Knowledge of NLP and/or multi-modal architectures is highly desired. You have a good understanding of: Diffusion, autoregressive, or other generative models. Self-supervised, contrastive learning, auto-encoders Audio, image, or text applications – Source separation, text-to-speech, music synthesis, image segmentation, image captioning, question answering, language models, etc. Knowledge of Game environments, graphical processing, consumer products, SoC architectures, embedded software, GPU/CPU implementations, algorithm validation and testing, implementation of ML/AI algorithms. Demonstrated ability to create fundamentally new, novel (patentable) image processing, enhancement, and rendering technologies. Strong publication record in major image/video/AI conferences and journals (e.g. NeurIPS, ICLR, ICML, etc.). Strong track of inventing, developing and productizing video technologies in an industrial research environment. Ability to envision applications of new technologies in the form of innovative product solutions. Strong innovator. Highly skilled in C/C++, Python. Experience in managing, guiding and mentoring younger researchers. Team-oriented work ethic and interest to work in cross-continental teams. Strong personal interest in learning, researching, and creating relevant new technologies with high commercial impact. Excellent communication, collaboration, and presentation skills in English. All official communication regarding employment opportunities at Dolby will come from an official dolby.com email address. We will never request payment as part of the hiring process. If you receive a suspicious message, please verify its authenticity before responding

Hi Folks ACL Digital is Hiring! Experience: 4 - 5+ Years Location: Bangalore / Hyderabad Looking: Immediate to 20 days Hiring | RTL Design Engineer Strong experience in RTL Design using Verilog/System Verilog Exposure to complex SoC/ASIC design and integration Hands-on with synthesis, Lint, CDC preferred Share resume at himabindu.jeevarathnam@acldigital.com #RTLEngineer #ACLdigital #VLSIJobs #ASICDesign #Verilog #SystemVerilog #SoC Thanks, K Himabindu

SD Fine Chem Ltd, a pioneer in the Laboratory, Research, and Specialty Chemicals manufacturing industry since 1978, values strong customer relationships, quality, productivity, and meeting customer demands as its fundamental objectives. As an R&D Officer/Executive at SD Fine-Chem, based in Tarapur, Maharashtra, you are expected to possess an M.Sc in Organic Chemistry, with a preferable experience of 2-5 years in the chemical industry focusing on R&D. Your role will require a deep understanding of organic chemistry principles encompassing reaction mechanisms, synthesis, and characterization. Proficiency in independently setting up reactions with strict adherence to safety protocols is essential. You will be responsible for developing and optimizing reaction parameters and processes suitable for production scale, along with the ability to analyze and interpret data, including spectroscopic and chromatographic data. Preference will be given to candidates based locally in Mumbai or willing to relocate to Tarapur. To apply for this position, please send your updated CV to hrcor@sdfine.com with the subject line "R&D Executive Boisar".,

As an Integrated Circuit Designer, you will be responsible for overseeing the definition, design, verification, and documentation for ASIC development. Your role will involve determining architecture design, logic design, and system simulation. You will be defining module interfaces/formats for simulation and contributing to the development of multidimensional designs involving the layout of complex integrated circuits. Additionally, you will evaluate all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use. Analyzing equipment to establish operation data, conducting experimental tests, and evaluating results will also be part of your responsibilities. You may also be involved in reviewing vendor capability to support development. You should have wide-ranging experience and use professional concepts and company objectives to resolve complex issues in creative and effective ways. Strong project management skills are essential for this role. Leading the design and delivery of new products/process and being expert in complementary fields are key aspects of this position. You will be applying broad concepts and theories to achieve innovative and effective solutions to complex problems. In this role, you will work on complex issues where analysis of situations or data requires an in-depth evaluation of variable factors. You will exercise judgment in selecting methods, techniques, and evaluation criteria for obtaining results. Networking with key contacts outside your area of expertise will be necessary. Championing significant projects, programs, and business initiatives using demonstrated creativity and ingenuity is expected from you. You will be a team leader, leading major projects, influencing or impacting others" priorities, decisions, or activities. You will also serve as an escalation point for complex issues and coach and mentor other junior team members. As a team leader, you will provide a leadership role for the work group through knowledge in your area of specialization. You will be generally free to determine work priorities based on general direction from managers. Determining methods and procedures on new assignments, consulting with management on long-range goals, and determining your own priorities, both tactical and strategic, will be part of your responsibilities. To qualify for this position, you should have a Bachelor's degree and 8+ years of related experience. Alternatively, a Master's degree and 6+ years of related experience or a PhD and 3+ years of related experience would also be considered. Post-graduate coursework may be desirable at this level.,

As an experienced professional with 7-9 years of experience, you will be responsible for executing customer projects independently with minimal supervision in the field of VLSI Frontend Backend or Analog design. Your role will involve guiding team members technically and taking ownership of specific tasks/modules related to RTL Design, Module Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. You will lead the team to achieve results, complete assigned tasks successfully and on-time, and anticipate, diagnose, and resolve problems as necessary. Your responsibilities will also include ensuring on-time quality delivery approved by the project manager and client, automating design tasks flows, writing scripts to generate reports, and coming up with innovative ideas to reduce design cycle time and cost. Additionally, you will be expected to write papers, file patents, and devise new design approaches. To measure the outcomes of your work, quality will be verified using relevant metrics by UST Manager/Client Manager, timely delivery will be assessed based on relevant metrics, and the reduction in cycle time and cost using innovative approaches will be monitored. The number of papers published, patents filed, and trainings presented to the team will also be considered. Your outputs are expected to demonstrate high quality deliverables with zero bugs in the design/circuit design, clean delivery of the design/module, meeting functional specs/design guidelines without deviation, and thorough documentation of tasks and work performed. Timely delivery, teamwork, innovation, and creativity will be key aspects of your role, along with participation in technical discussions and training forums. Your skills should include proficiency in languages and programming skills such as System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, and Makefile. You should have experience with EDA tools like Cadence, Synopsys, and Mentor tool sets, as well as technical knowledge in IP spec architecture design, bus protocols, physical design, circuit design, analog layout, synthesis, DFT, floorplan, clocks, P&R, STA, extraction, physical verification, and more. Strong communication skills, analytical reasoning, problem-solving abilities, attention to detail, and the ability to interact with team members and clients effectively are essential. You should also be well-versed in using available EDA tools, delivering tasks on time per quality guidelines, understanding standard specs and functional documents, and continuously learning new skills as needed. If you have led and executed projects in RTL Design, Verification, DFT, Physical Design, STA, PV, Circuit Design, Analog Layout, and possess a good understanding of design flow and methodologies, this role could be a great fit for you. Additionally, experience in analog circuit design and verifications, knowledge of TSMC FinFet technologies, and familiarity with Cadence Virtuoso circuit design suite would be beneficial. In this role, you will be responsible for circuit design and verification of analog modules like Voltage regulator, LDOs, developing circuit architecture, optimizing designs, guiding layout engineers, problem-solving, and effective communication skills. Desired skills include solid CMOS Analog design fundamentals, hands-on experience with Cadence Virtuoso, technical knowledge of power-performance trade-offs, understanding device parameter variation, and being a good team player in a multi-site work environment. Join us at UST, a global digital transformation solutions provider, where you will work alongside the world's best companies to make a real impact through transformation. With deep domain expertise, innovation, and agility, UST partners with clients to embed innovation and create boundless impact, touching billions of lives in the process.,

Job Responsibilities: Small Molecule Synthetic - API R&D (L7) Should have knowledge on IP and RA guidelines. Able to develop and produce cost-effective, safe, and eco-friendly technologies for the synthesis of simple and complex APIs. Should have knowledge on characterization of compounds by using characterization tools Should knowledge on purification tools for the purification of Intermediates/API Able to manage the entire product development including requirement of analysis, finalizing specifications, designing, prototype development and testing activities. Able to facilitate the new product development initiative with key focus on quality, cost delivery; developing components in conformance to pre-set technical specifications. Able to plan and implement new projects Able to develop of cost effective and plant feasible processes. Should have knowledge on product development, optimizations, lab validations and technology transfer from R&D to production. Should have thorough understanding on process impurities, degradation impurities and carry over impurities. Should have experience in technology transfer, scaleup and validation in manufacturing facility. Able to prepare a project estimation report for new product development / Business Able to Setup the raw material, intermediate as well as finished product specification with the help of cross functional team members Able to ensure the implementation of the developed process when the process goes for scale up or commercialization with available resources and infrastructure. Able to supervise the subordinates for timely completion of assigned projects. Ensuring individual safety and lab safety Educational Qualifications Required Education Qualification: M.Sc. in Organic Chemistry or Ph.D. in Organic Chemistry Required Experience: 12-15 years in case of M.Sc. or 4-6 years in case of Ph.D.

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Job Description Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in. You will be joining a successful engineering team whose deliveries can be found in billions of mobile, compute and IoT products worldwide. Based out of Qualcomm's Bangalore office, this role offers a position in Low Power controller IP cores and subsystem digital design targeted for variety of industry leading Snapdragon SoCs for mobile, compute, IoT and Automotive markets. Key Responsibilities Micro-architecture and RTL design for Cores / subsystems. Work in close coordination with Systems, Verification, SoC, SW, PD & DFT teams for design convergence. Enable SW teams to use HW blocks. Qualify designs using static tool checks including Lint, CDC, LEC and CLP. Synthesis, LEC and Netlist CLP Report status and communicate progress against expectations. Preferred Qualifications 5 to 10 years of strong experience in digital front end design (RTL design) for ASICs Expertise in RTL coding in Verilog/SV/VHDL of complex designs with multiple clock domains and multiple power domains Familiar with UPF and power domain crossing Experience in Synthesis, Logical Equivalence checks, RTL and Netlist CLP Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI Experience in low power design methodology and clock domain crossing designs Experience in Spyglass Lint/CDC checks and waiver creation Experience in formal verification with Cadence LEC Understanding of full RTL to GDS flow to interact with DFT and PD teams Expertise in Perl/TCL/Python language Experienced in database management flows with Clearcase/Clearquest. Expertise in post-Si debug is a plus Excellent oral and written communications skills to ensure effective interaction with Engineering Management and team members. Team player, self-motivated, should be able to work with minimal supervision. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3076998

Technology Expert, PCIe 7.0 & UCIe ( Senior Director level ) www.omnidesigntech.com Location: Bengaluru www.omnidesigntech.com Location- Bangalore About Omni Design Technologies Omni Design Technologies is a leading provider of high-performance, ultra-low power IP cores, from 28nm down through advanced FinFET nodes, which enable differentiated system-on-chip (SoC), in applications ranging from 5G, wireline and optical communications, LiDAR, radar, automotive networking, AI, image sensors, and the internet-of-things (IoT). Our data converter (ADC and DAC) IP cores range from 6-bit to 14-bit resolution and from a few MSPS to more than 100 GSPS sampling rates. Omni Design, founded in 2015 by semiconductor industry veterans, has an excellent track record of innovation and collaboration with customers to enable their success. The company is headquartered in Milpitas, California with additional design centers in Fort Collins-Colorado, Bangalore-India, Hyderabad-India, Dublin-Ireland, Boston-Massachusetts. Job Summary: Principal SerDes Technology Expert We are seeking a highly motivated and experienced Principal SerDes Technology Expert to lead the development of next-generation connectivity solutions. Your journey will begin by spearheading the design and optimization of high-performance Active Electrical Cables (AECs), enhancing electrical integrity and signal quality across demanding link budgets. Building on this foundation, you will architect and implement SerDes technology tailored for PCIe 7.0, tackling challenges such as lane equalization, jitter tolerance, and power efficiency. Finally, your work will expand into integrating cutting-edge optical interconnects and optocouplers, driving innovations in retimer technologies and hybrid signaling frameworks. This role directly impacts the performance and reliability of AI and cloud infrastructure—empowering massive data throughput, energy-efficient links, and scalable system architectures. Responsibilities: Lead the architecture and design of high-speed SerDes for PCIe 7.0, targeting data rates of 128 GT/s and beyond. Spearhead the development and integration of advanced optical interconnects and retimer solutions within our Smart Cable Modules™. Define and specify the requirements for mixed-signal SerDes PHYs, including transmitter (TX), receiver (RX), and clock and data recovery (CDR) circuits. Conduct in-depth analysis and simulation of high-speed channel performance, including signal integrity (SI) and power integrity (PI). Collaborate with cross-functional teams, including hardware design, firmware, and system validation, to ensure successful product development and bring-up. Stay at the forefront of industry standards and emerging technologies, particularly related to PCIe, CXL, and high-speed optical interconnects. Mentor junior engineers and provide technical leadership across the organization. Work closely with partners and vendors to evaluate and select key components. Qualifications: Required Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. 20-25 years years of experience in high-speed SerDes design and development. Proven expertise in PCIe protocols, with direct experience in PCIe 4.0/5.0/6.0 design and a strong understanding of the upcoming PCIe 7.0 specification. In-depth knowledge of mixed-signal design, including experience with PAM4 signaling, equalization techniques (e.g., FFE, DFE), and clocking architectures. Hands-on experience with high-speed test and measurement equipment (e.g., oscilloscopes, BERTs, VNAs). Strong understanding of signal integrity principles and experience with simulation tools (e.g., HSPICE, ADS, Ansys). Preferred Qualifications: Master's or Ph.D. in a relevant technical field. Experience with the design and integration of optical interconnects, silicon photonics, or high-speed optoelectronics. Familiarity with the design of retimers and their application in Active Electrical Cables. Experience with high-level modeling of SerDes links using tools like MATLAB or Python. Knowledge of other high-speed protocols such as Ethernet, CXL, or NVLink. A track record of leading complex projects from concept to production. Excellent communication and interpersonal skills. We are seeking a highly skilled and experienced IP Design Engineer to join our team, focusing on the design, development, and validation of cutting-edge high-speed interface Intellectual Property (IP). The ideal candidate will have a strong background in complex digital and mixed-signal design, with a particular emphasis on interfaces such as UCIe, Die-to-Die (D2D), and various memory PHYs (DDR/LPDDR). Expertise in advanced clocking architectures including PLLs and DLLs is also essential. This role involves contributing to the full IP development lifecycle, from architectural definition and RTL design to silicon validation and post-silicon support, ensuring first- pass silicon success for critical products that enable next-generation data center interconnects. Key Responsibilities: • Design & Development: Architect, design, and implement high-speed interface IPs, including UCIe, D2D, DDR, and LPDDR PHYs. Contribute to the development of high-speed SerDes IP transceivers supporting rates like 100G PAM4 (106.25 Gbps), 50G PAM4 (53.125 Gbps), and 25G NRZ (26.5625 Gbps) for applications such as PCIe, Ethernet, and data center interconnects. • Clocking Design: Develop and optimize PLL (Phase-Locked Loop) and DLL (Delay- Locked Loop) circuits for high-speed clock generation and synchronization, ensuring low jitter and high accuracy. This includes experience with Fractional/Spread-spectrum/Integer Frequency synthesizers, LC VCOs, Multi- Modulus Dividers, Charge Pumps, LPFs, LDO regulators, and BGRs. • IP Development Lifecycle: Participate in the complete IP design flow, including architectural definition, specification development, RTL coding, synthesis, static timing analysis (STA), and collaborating on physical design activities (GDSII). 1 • Verification & Validation: Work closely with verification teams to define test plans, debug complex design issues, and lead pre-silicon and post-silicon validation efforts, including silicon bring-up and characterization .2 Implement features for deep in-cable diagnostics (e.g., eye metric readout, PRBS bit error rate, loopback modes), fleet management, and security for robust interconnect solutions. • Analog/Mixed-Signal Integration: Collaborate on the integration of analog and mixed-signal blocks within the PHYs, addressing complex integration challenges and optimizing for performance, power, and area (PPA). • Documentation: Create comprehensive design specifications, integration guidelines, and application notes for IP blocks.• Problem Solving: Debug and resolve complex design issues at various stages of the development cycle, including silicon debugging and fault isolation. • Standards Compliance: Ensure IP designs comply with industry standards (e.g., JEDEC for DDR/LPDDR, QSFP-DD/OSFP mechanical and common management interface specifications) and customer requirements. • Performance Optimization: Focus on achieving low-latency data paths (< 100 ns) and optimizing for lower power consumption in high-speed interconnect solutions. Required Qualifications: • Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field.3 • 20-25 years of experience in digital, mixed-signal, or analog IP design within the semiconductor industry. (Adjust X based on Senior/Principal level). • Proven experience with high-speed interface designs such as UCIe, D2D, DDR PHY, or LPDDR PHY. • Demonstrated experience in the design and optimization of PLLs and/or DLLs, including various types of frequency synthesizers and clock generation circuits. • Familiarity with the entire IP development flow from architectural concept to silicon validation. • Strong understanding of signal integrity, power integrity, and layout considerations for high-speed designs, especially for PAM4 and NRZ signaling over copper cables. • Proficiency with industry-standard EDA tools for design, simulation, and analysis. • Experience with deep diagnostic features, security implementations (firmware security, unauthorized access prevention), and non-disruptive firmware updates for high-speed modules. • Excellent problem-solving skills and attention to detail. • Strong communication and collaboration skills to work effectively with cross- functional teams. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Senior SoC Director / SoC Director Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/Bangalore A US based well-funded product-based startup looking for highly talented SoC Director for the following roles Senior Director / SoC Director of SOC is : Trust, loyalty, and ability to command Technical respect with foreign partners after having Taped out Successfully multiple chips to high volume production….this should be easily achieved under his/her belt !!!!!!!! Somebody we can trust to drive on the World stage without embarrassing us Job Description: We are seeking an experienced professional to lead full chip design for multi-million gate SoCs. The ideal candidate will have expertise in digital design and RTL development, with a deep understanding of the design convergence cycle, including architecture, micro-architecture, synthesis, timing closure, and verification. Key Responsibilities: Proficiency in AI Accelerators DNN Accelerators co-processors Interconnect Fabric Cache Coherency D2D C2C SoC Director Bangalore We are a AI semiconductor startup company headquartered in Ann Arbor, Michigan, with branches in , Taiwan and Bangalore, India. We develop highly scalable and innovative AI accelerator chips that offer high performance, low energy, and customer ease of implementation for embedded Edge AI vision-based applications and real-time data processing. Company has working HW & SW for customer sampling, with production designs in the pipeline, and a system architecture designed a future of neuromorphic computing. We are backed by excellent VC funding and is currently in a stage of rapid growth. While our tech is one of a kind we would not be able to make these advancements without our team. Our collaborative culture is one of the keys to our success. Who You Are You are an open and honest communicator who values your team You are innovative, enjoy bringing new ideas to the table and are receptive to ideas and feedback from others You’re passionate about advancing the state of the world through new technology You enjoy the ambiguity and pace of a startup environment The role This leadership role will be responsible for the global VLSI efforts at and India Site Management. It is a highly visible role reporting to Senior Director with ownership of all pre/post Si activities, leading interface with external EDA, IP, Design Service partners, managing the India site operations and a global VLSI team. What you will be doing: Ownership of pre-Si Design of the next-gen AI accelerator at driving deliverables with Design and IP Service providers, CAD tools, IPs, DFT/PD/Packaging and Test. Work closely with internal Architecture, SW, Emulation, and system board designers on product definition, microarchitecture, and design implementation. Build and manage the VLSI team of front-end design and verification engineers across India and Taiwan. Establish best practices for development, testing, reviews, and documentation. Participate in strategic discussions for product features and roadmap. What we expect to see: BS/MS in Electrical/Electronic Engineering with 18+ years of experience in VLSI, SOC design, several Si tape-out/production. Hands-on experience in front-end design, VLSI flows, and working experience for all aspects of Si tape-out, post-Si validation. Self-driven, organized with strong leadership and communication skills. Experience in building and managing teams with the ability to motivate and lead in a startup environment. Proven track record in several successful productizations. What we would be happy to see: Knowledge of AI, specifically Deep Neural Networks Application-specific accelerators or co-processors Startup experience Site Leadership experience Reports to: Site Lead Work location: Bangalore, India Hours: Full time Employment Opportunity and Benefits of Employment: We are committed to creating and fostering a diverse and inclusive workplace environment for all of our employees. We are an equal opportunity employer. Contact: Uday Mulya Technologies Email: muday_bhaskar@yahoo.com Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

IPrincipal P/RTL Design Engineer for ARM CMN Fabric and Neoverse Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Principal IP/RTL Design Engineer for ARM CMN Fabric and Neoverse Position Overview Seeking an IP/RTL Design Engineer with 10+ years of experience to design IP/RTL for ARM Neoverse-based SoCs, focusing on CMN fabric, using Socrates for configuration, targeting AI/HPC datacenter applications. Key Responsibilities Design IP blocks for ARM Neoverse SoCs, integrating CMN fabric (e.g., CMN-700/S3) for cache coherence and interconnect. Develop Verilog/SystemVerilog RTL for high-performance, low-latency designs. Configure CMN topologies using Arm Socrates for optimized performance and scalability. Implement protocols like AMBA CHI, ACE, CXL, PCIe for coherent interconnects. Optimize designs for bandwidth, latency, and power in AI/HPC workloads. Support synthesis, timing closure, and FPGA prototyping and Design Verification team Document microarchitecture and design specifications. Required Qualifications Education: BS/MS/PhD in Electronics/Computer Engineering. Experience: 10+ years in ASIC/FPGA IP/RTL design, 5+ years with ARM Neoverse and CMN fabrics (e.g., CMN-600/700/S3). Skills: Expert in Verilog/SystemVerilog RTL design. Deep knowledge of ARM Neoverse (V1/V3/N2/N3) and CMN interconnects. Deep understanding in system architecture, coherence and cache Experience with Arm Socrates for CMN configuration. Proficiency in AMBA CHI, CXL, PCIe, or CCIX protocols. Familiarity with synthesis and timing tools (e.g., Synopsys Design Compiler). Experience with AI/HPC or datacenter SoC design. Knowledge of DDR5, HBM3, or chiplet-based architectures. Familiarity with UALink or Ultra Ethernet. Strong problem-solving and collaboration skills. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Principal IP/RTL Design Engineer for TPU Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore IP/RTL Design Engineer for TPU Position Overview Seeking an IP/RTL Design Engineer with 5+ years of experience to design IP/RTL for TPUs, focusing on high-performance matrix multiplication, low-latency interconnects, and power-efficient AI acceleration. Key Responsibilities Design IP blocks for TPU cores, including systolic arrays, vector units, and memory subsystems. Develop Verilog/SystemVerilog RTL for performance, timing, and area optimization. Implement high-speed interconnects (e.g., AXI, NoC) for TPU data pipelines. Optimize designs for high throughput, low latency, and power efficiency in AI workloads. Integrate LPDDR6, HBM3, DDR5, or chiplet-based memory interfaces. Support synthesis, timing closure, and FPGA prototyping and Design Verification team Document microarchitecture and design specifications. Required Qualifications Education: BS/MS in Electrical/Computer Engineering. Experience: 10+ years in ASIC/FPGA IP/RTL design, with 3+ years in AI accelerators or TPU-like architectures. Skills: Proficient in Verilog/SystemVerilog RTL design. Knowledge of TPU architectures, systolic arrays, or matrix multiplication units. Experience with AXI, NoC, or similar interconnect protocols. Familiarity with LPDDR6, HBM3, DDR5, or high-bandwidth memory interfaces. Proficiency with synthesis and timing tools (e.g., Synopsys Design Compiler). Strong problem-solving and teamwork skills. Preferred Qualifications Experience with AI/ML workloads or datacenter TPU designs and GPU architectures Knowledge of CXL, PCIe, UALink, or Ultra Ethernet. Familiarity with power optimization for high-performance chips. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"