DFT Senior Engineer / Lead Coventine Digital

10.0 - 20.0 years

15 - 25 Lacs

Bengaluru

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Key Responsibilities: Ownership of Scan/ATPG and MBIST flows for complex SoCs Expertise in Synopsys tools , especially SMS (Synopsys Memory Solution) Deep understanding of MBIST architecture and memory repair techniques Hands-on experience with Scan insertion and ATPG for large devices using hierarchical DFT flows Debug and support issues during DFT implementation and silicon bring-up Collaborate closely with RTL, PD, and test engineering teams

Posted 1 month ago

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VLSI MBIST Engineer Coventine Digital

4.0 - 8.0 years

5 - 15 Lacs

Bengaluru

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Job Description : We are looking for a VLSI MBIST Engineer with strong expertise in Memory Built-In Self-Test (MBIST) methodologies for ASIC/SoC designs. The ideal candidate should have hands-on experience using Synopsys SMS tool and a solid understanding of MBIST test development, pattern generation, and fault simulation. Key Responsibilities : Develop and implement MBIST algorithms and test patterns for embedded memories (SRAM, DRAM, ROM, CAM) Use Synopsys SMS tool for MBIST pattern generation and validation Perform fault modeling, fault simulation, and fault coverage analysis Integrate MBIST macros into SoC designs in collaboration with RTL and physical design teams Debug MBIST issues in pre- and post-silicon stages Document MBIST flows, generate test reports, and provide support for DFT reviews Stay updated on industry trends and best practices in MBIST and memory testing Required Skills : B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, VLSI, or related fields 4+ years of experience in MBIST implementation and validation Strong experience with Synopsys SMS tool Proficiency in scripting languages like TCL, Perl, or Python Good knowledge of Verilog/SystemVerilog and digital design fundamentals Familiarity with simulation tools like VCS, ModelSim Preferred Skills : Experience with DFT tools such as Tessent Knowledge of ATPG, JTAG (IEEE 1149.1), and IEEE 1500 standards Exposure to silicon bring-up and failure analysis

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