Functional DV (Clock/Power) Verification Sr Engineer & above levels Qualcomm

1.0 - 13.0 years

0 Lacs

karnataka

On-site

As a Graphics Verification Engineer at Qualcomm Graphics HW team in Bangalore, you will be responsible for verifying the Clock and power management module with design features for low power in GPU solutions. Your key responsibilities will include: - Understanding GPU power and clock domains with power-up/down sequences - Ownership of end-to-end DV tasks from coding Test bench and test cases, writing assertions, debugging simulations, and achieving all coverage goals - Developing a test plan to verify sequences and design components for Clock and power management modules - Exploring innovative DV methodologies (formal and simulation) to continuously push the quality and efficiency of test ben...

Posted 2 weeks ago

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Functional DV (Clock/Power) Verification Sr Engineer & above levels Qualcomm

1.0 - 13.0 years

0 Lacs

karnataka

On-site

Qualcomm Graphics HW team in Bangalore is responsible for developing and delivering GPU solutions which are setting the power and performance benchmark in mobile computing industry. As a Graphics Verification Engineer, you will be verifying the Clock and power management module with design features for low power. Your responsibilities will include understanding GPU power and clock domains with power-up/down sequences, owning end-to-end DV tasks from coding Test bench and test cases, writing assertions, debugging simulations, and achieving all coverage goals. You will also develop a test plan to verify sequences and design components for Clock and power management modules. Additionally, you w...

Posted 3 months ago

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GPU Design Verification Engineers Qualcomm

2.0 - 6.0 years

0 Lacs

karnataka

On-site

Qualcomm India Private Limited is seeking a GPU Functional Verification Engineer to join the GPU HW team. As a GPU Functional Verification Engineer, you will be responsible for developing a deep understanding of 3-D Graphics hardware pipeline, feature sets, data paths, block functionalities, and interfaces. Your duties will include strategizing and proposing a DV environment, developing a test bench, owning a test plan, debugging all RTL artifacts, and achieving all signoff matrices. You will collaborate with EDA vendors, explore innovative DV methodologies, and work with worldwide architecture, design, and systems teams to meet project goals. The ideal candidate should possess a Bachelor's ...

Posted 3 months ago

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