601 Synopsys Jobs - Page 24

Hyderabad, Telangana, India Category: Information Technology Hire Type: Employee Job ID 9010 Date posted 02/24/2025 You Are: You are an experienced and passionate cloud governance professional with over seven years in the field. You possess deep expertise in cloud platforms such as Azure, AWS, or GCP and have a proven track record of implementing governance frameworks and cost management tools. Your proficiency in scripting languages like Python, PowerShell, or Bash enables you to automate complex processes efficiently. You excel in translating governance needs into actionable policies, ensuring compliance with industry standards such as SOC 2, ISO 27001, NIST, and FedRAMP. Your strong analytical skills and ability to collaborate effectively with cross-functional teams make you an invaluable asset in driving cloud cost optimization, security, and regulatory adherence. You are committed to fostering an automation-first approach to governance and compliance, educating teams on best practices, and continuously improving cloud architecture and cost efficiency. What You’ll Be Doing: Define and enforce cloud governance policies across Azure, AWS, and GCP. Implement policy-as-code solutions to automate cloud compliance and security best practices. Work with engineering teams to ensure adherence to cloud resource management, IAM, and security standards. Build and manage cost monitoring dashboards, anomaly detection, and alerting for cloud spend. Develop strategies for cost optimization, including reserved instances, spot instances, and right-sizing. Conduct regular cloud security audits, identifying risks, vendor contract reviews, and driving remediation plans. Implement automated compliance monitoring and reporting solutions. Collaborate with security teams to strengthen IAM policies, encryption, and logging. Establish guardrails using AWS SCPs, Azure Policy, or Google Organization Policies. Develop and maintain runbooks for governance incidents to ensure swift remediation. Work closely with engineering, security, and finance teams to align governance with business objectives. The Impact You Will Have: Enhancing cloud governance posture to ensure optimal cloud usage and security. Driving cost efficiency through automation and policy enforcement. Ensuring compliance with industry standards, contributing to regulatory adherence. Optimizing cloud architecture and cost efficiency by enforcing best practices. Providing insights and recommendations on budgeting, forecasting, and cloud spend efficiency. Strengthening IAM policies, encryption, and logging to enhance cloud security. Implementing automated compliance monitoring and reporting solutions. Educating teams on cloud cost management, security, and compliance best practices. Advocating for automation-first approaches to governance and compliance. Collaborating with cross-functional teams to align governance with business objectives. What You’ll Need: 5+ years of experience in cloud governance, FinOps, or cloud security. Expertise in Azure, AWS, or GCP, including governance frameworks and cost management tools. Hands-on experience with cloud cost monitoring platforms (e.g., AWS Cost Explorer, Azure Cost Management, Google Cloud Billing). Strong knowledge of Infrastructure as Code (Terraform, CloudFormation) and Policy as Code (OPA, AWS SCPs, Azure Policies). Experience with audit and compliance frameworks such as SOC 2, ISO 27001, NIST, and FedRAMP. Proficiency in scripting languages (Python, PowerShell, Bash) for automation. Strong analytical skills and ability to translate governance needs into actionable policies. Excellent collaboration and communication skills to engage cross-functional teams. Who You Are: You are a collaborative and communicative team player with a passion for cloud governance and security. You possess excellent analytical skills and have a proactive approach to problem-solving. You are committed to continuous learning and improvement, staying updated with industry standards and best practices. Your ability to educate and advocate for automation-first approaches makes you a key contributor to the team's success. You are detail-oriented, ensuring compliance with industry standards while driving cost efficiency and optimizing cloud usage. The Team You’ll Be A Part Of: You will be part of the Synopsys Cloud IT Team, a dedicated group focused on implementing and managing cloud governance strategies, establishing FinOps practices, and ensuring compliance with industry standards. The team collaborates closely with cloud engineering, security, finance, and compliance teams to optimize cloud usage, maintain security, and drive cost efficiency through automation and policy enforcement. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Hyderabad, Telangana, India Category: Engineering Hire Type: Employee Job ID 8369 Date posted 02/24/2025 Alternate Job Titles: Standard Cell Design Manager Logic Library Group Manager Standard Cell R&D Manager We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a dynamic and experienced leader with a strong background in standard cell library design. You have a Bachelor's or Master's degree from a reputed university and at least 10 years of hands-on experience in designing and optimizing standard cell circuits. You possess a deep understanding of CMOS device characteristics, submicron process nodes, and are familiar with FINFET/GAA technologies. Your expertise extends to layout design and working closely with layout designers to optimize parasitics for target PPA. You excel in a collaborative environment, working effectively with geographically distributed R&D teams and engaging in cross-functional collaborations. Additionally, you have a proven track record of mentoring and coaching junior engineers, guiding them to improve their circuit design and simulation skills. Your strong analytical and logical skills enable you to address complex technical challenges and drive innovation in the field of standard cell design. What You’ll Be Doing: Designing and validating custom standard cells, including flip flops, clock gating cells, level shifters, and power gating cells. Optimizing standard cell circuits to achieve better performance, power, and area (PPA). Engaging in hands-on development while mentoring and coaching junior R&D engineers. Collaborating with layout designers to optimize layout parasitics and achieve target PPA. Involving in layout extraction and understanding layout-dependent parameters in the extracted netlist. Implementing, testing, and analyzing circuit design guidelines and methodologies. The Impact You Will Have: Driving innovations in standard cell design that contribute to the success of Synopsys' products. Enhancing the performance, power, and area (PPA) of our silicon IP portfolio. Mentoring and developing the next generation of R&D engineers. Collaborating across functions to ensure methodology alignment and optimization. Contributing to the continuous improvement of circuit design methodologies. Supporting the integration of more capabilities into System-on-Chip (SoC) designs, meeting unique performance, power, and size requirements. What You’ll Need: Bachelor's or Master's degree in Electrical Engineering or a related field. 10+ years of experience in standard cell library design. Deep understanding of CMOS device characteristics and submicron process nodes. Experience with FINFET/GAA technologies and high sigma variation analysis. Familiarity with layout design and optimization of layout parasitics. Who You Are: Strong analytical and logical skills. Effective communicator and collaborator. Proactive problem solver with a hands-on approach. Mentor and coach for junior engineers. Innovative thinker with a passion for technology. The Team You’ll Be A Part Of: You will be part of the Logic Library Group, a team dedicated to the design and optimization of standard cell libraries. The team focuses on delivering high-performance, power-efficient, and area-optimized standard cells that are integral to Synopsys' silicon IP solutions. Collaboration and innovation are at the core of the team's values, ensuring the continuous advancement of our technology and methodologies. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Hyderabad, Telangana, India Category: Data Science Hire Type: Employee Job ID 8753 Date posted 02/24/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: As a Data Science Staff member located in Hyderabad, you are a visionary with a passion for data engineering and analytics. You thrive in dynamic environments and are motivated by the challenge of building robust data infrastructure. Your expertise in data modeling, algorithm development, and data pipeline construction is complemented by your ability to derive actionable insights from complex datasets. You possess a deep understanding of modern data stack tools and have hands-on experience with cloud data warehouses, transformation tools, and data ingestion technologies. Your technical acumen is matched by your ability to collaborate effectively with cross-functional teams, providing support and guidance to business users. You stay ahead of the curve by continuously exploring advancements in AI, Generative AI, and machine learning, seeking opportunities to integrate these innovations into your work. Your commitment to best practices in data management and your proficiency in various scripting languages and visualization tools make you an invaluable asset to our team. What You’ll Be Doing: Building the data engineering and analytics infrastructure for our new Enterprise Data Platform using Snowflake and Fivetran. Leading the development of data models, algorithms, data pipelines, and insights to enable data-driven decision-making. Collaborating with team members to shape the design and direction of the data platform. Working end-to-end on data products, from problem understanding to developing data pipelines, dimensional data models, and visualizations. Providing support and advice to business users, including data preparation for predictive and prescriptive modeling. Ensuring consistency of processes and championing best practices in data management. Evaluating and recommending new data tools or processes. Designing, developing, and deploying scalable AI/Generative AI and machine learning models as needed. Providing day-to-day production support to internal business unit customers, implementing enhancements and resolving defects. Maintaining awareness of emerging trends in AI, Generative AI, and machine learning to enhance existing systems and develop innovative solutions. The Impact You Will Have: Driving the development of a cutting-edge data platform that supports enterprise-wide data initiatives. Enabling data-driven decision-making across the organization through robust data models and insights. Enhancing the efficiency and effectiveness of data management processes. Supporting business users in leveraging data for predictive and prescriptive analytics. Innovating and integrating advanced AI and machine learning solutions to solve complex business challenges. Contributing to the overall success of Synopsys by ensuring high-quality data infrastructure and analytics capabilities. What You’ll Need: BS with 5+ years of relevant experience or MS with 3+ years of relevant experience in Computer Sciences, Mathematics, Engineering, or MIS. 5 years of experience in DW/BI development, reporting, and analytics roles, working with business and key stakeholders. Advanced knowledge of Data Warehousing, SQL, ETL/ELT, dimensional modeling, and databases (e.g., mySQL, Postgres, HANA). Hands-on experience with modern data stack tools, including cloud data warehouses (Snowflake), transformation tools (dbt), and cloud providers (Azure, AWS). Experience with data ingestion tools (e.g., Fivetran, HVR, Airbyte), CI/CD (GitLab, Kubernetes, Airflow), and data catalog tools (e.g., Datahub, Atlan) is a plus. Proficiency in scripting languages like Python, Unix, SQL, Scala, and Java for data extraction and exploration. Experience with visualization tools like Tableau and PowerBI is a plus. Knowledge of machine learning frameworks and libraries (e.g., Pandas, NumPy, TensorFlow, PyTorch) and LLM models is a plus. Understanding of data governance, data integrity, and data quality best practices. Experience with agile development methodologies and change control processes. Who You Are: You are a collaborative and innovative problem-solver with a strong technical background. Your ability to communicate effectively with diverse teams and stakeholders is complemented by your analytical mindset and attention to detail. You are proactive, continuously seeking opportunities to leverage new technologies and methodologies to drive improvements. You thrive in a fast-paced environment and are committed to delivering high-quality solutions that meet business needs. The Team You’ll Be A Part Of: You will join the Business Applications team, a dynamic group focused on building and maintaining the data infrastructure that powers our enterprise-wide analytics and decision-making capabilities. The team is dedicated to innovation, collaboration, and excellence, working together to drive the success of Synopsys through cutting-edge data solutions. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Hyderabad, Telangana, India Category: Engineering Hire Type: Employee Job ID 8804 Date posted 02/24/2025 Alternate Job Titles: Senior Cell Library Design Engineer Senior Logic Library Design Engineer Senior Standard Cell Designer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced Standard Cell Library Design Engineer with a passion for innovation and technology. You hold a Bachelor's or Master's degree from a reputable university and have over three years of experience in designing standard cell libraries. Your expertise extends to optimizing standard cell circuits to achieve superior performance, power, and area (PPA). You have designed complex circuits such as flip-flops, clock gating cells, level shifters, and power gating cells. Your deep understanding of CMOS device characteristics and design rules in submicron process nodes, especially in FINFET/GAA technologies, sets you apart. You are proficient in running high sigma variation analysis and have a knack for layout design and optimization. Your analytical and logical skills are exemplary, and you thrive in a collaborative environment, working effectively with geographically distributed R&D teams. If you are driven by innovation and eager to contribute to groundbreaking technology, we want to meet you. What You’ll Be Doing: Designing and optimizing standard cell libraries to achieve targeted PPA. Developing complex circuits including flip-flops, clock gating cells, level shifters, and power gating cells. Collaborating with layout designers to optimize layout parasitics. Engaging in layout extraction and understanding layout-dependent parameters. Conducting timing and power characterization of standard cells. Working closely with cross-functional teams for optimization across the design chain. The Impact You Will Have: Enhancing the performance, power, and area of standard cell libraries. Contributing to the development of high-impact, cutting-edge technology. Driving innovation in complex circuit design and optimization. Ensuring the successful integration of IP blocks into SoCs. Influencing the design and development of self-driving cars, AI, and IoT devices. Supporting Synopsys’ leadership in the silicon IP market. What You’ll Need: Bachelor's or Master's degree in Electrical Engineering or related field. 3+ years of experience in standard cell library design. Expertise in CMOS device characteristics and submicron process nodes. Proficiency in designing complex circuits and running high sigma variation analysis. Experience in layout design and optimization. Who You Are: Strong analytical and logical thinker. Detail-oriented with excellent problem-solving skills. Effective communicator and collaborator. Innovative and passionate about technology. Adaptable and able to work in a dynamic, fast-paced environment. The Team You’ll Be A Part Of: You will join the Logic Library Group, a dynamic team focused on developing high-performance standard cell libraries. The team collaborates closely with other R&D groups to optimize the entire design chain and deliver cutting-edge technology solutions. Together, you will work on innovative projects that drive the future of chip design and integration. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Hyderabad, Telangana, India Category: Information Technology Hire Type: Employee Job ID 9330 Date posted 02/24/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a forward-thinking Cloud DevOps Engineer with a passion for modernizing infrastructure and enhancing the capabilities of CI/CD pipelines, containerization strategies, and hybrid cloud deployments. You thrive in environments where you can leverage your expertise in cloud infrastructure, distributed processing workloads, and AI-driven automation. Your collaborative spirit drives you to work closely with development, data, and GenAI teams to build resilient, scalable, and intelligent DevOps solutions. You are adept at integrating cutting-edge technologies and best practices to enhance both traditional and AI-driven workloads. Your proactive approach and problem-solving skills make you an invaluable asset to any team. What You’ll Be Doing: Designing, implementing, and optimizing CI/CD pipelines for cloud and hybrid environments. Integrating AI-driven pipeline automation for self-healing deployments and predictive troubleshooting. Leveraging GitOps (ArgoCD, Flux, Tekton) for declarative infrastructure management. Implementing progressive delivery strategies (Canary, Blue-Green, Feature Flags). Containerizing applications using Docker & Kubernetes (EKS, AKS, GKE, OpenShift, or on-prem clusters). Optimizing service orchestration and networking with service meshes (Istio, Linkerd, Consul). Implementing AI-enhanced observability for containerized services using AIOps-based monitoring. Automating provisioning with Terraform, CloudFormation, Pulumi, or CDK. Supporting and optimizing distributed computing workloads, including Apache Spark, Flink, or Ray. Using GenAI-driven copilots for DevOps automation, including scripting, deployment verification, and infra recommendations. The Impact You Will Have: Enhancing the efficiency and reliability of CI/CD pipelines and deployments. Driving the adoption of AI-driven automation to reduce downtime and improve system resilience. Enabling seamless application portability across on-prem and cloud environments. Implementing advanced observability solutions to proactively detect and resolve issues. Optimizing resource allocation and job scheduling for distributed processing workloads. Contributing to the development of intelligent DevOps solutions that support both traditional and AI-driven workloads. What You’ll Need: 5+ years of experience in DevOps, Cloud Engineering, or SRE. Hands-on expertise with CI/CD pipelines (Jenkins, GitHub Actions, GitLab CI, ArgoCD, Tekton, etc.). Strong experience with Kubernetes, container orchestration, and service meshes. Proficiency in Terraform, CloudFormation, Pulumi, or Infrastructure as Code (IaC) tools. Experience working in hybrid cloud environments (AWS, Azure, GCP, on-prem). Strong scripting skills in Python, Bash, or Go. Knowledge of distributed data processing frameworks (Spark, Flink, Ray, or similar). Who You Are: You are a collaborative and innovative professional with a strong technical background and a passion for continuous learning. You excel in problem-solving and thrive in dynamic environments where you can your expertise to drive significant improvements. Your excellent communication skills enable you to work effectively with diverse teams, and your commitment to excellence ensures that you consistently deliver high-quality results. The Team You’ll Be A Part Of: You will join a dynamic team focused on optimizing cloud infrastructure and enhancing workloads to contribute to overall operational efficiency. This team is dedicated to driving the modernization and optimization of Infrastructure CI/CD pipelines and hybrid cloud deployments, ensuring that Synopsys remains at the forefront of technological innovation. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 8857 Date posted 02/24/2025 Staff Embedded Memory Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an innovative and dedicated engineer with a passion for embedded memory compilers. With 2-5 years of experience in Embedded SRAM compilers, you possess a robust understanding of CMOS digital circuits, and any knowledge of FinFET technology is a plus. Your expertise in transistor-level circuit design allows you to navigate the complexities of read/write margins and timing races. You thrive in a collaborative environment, often engaging with senior internal and external personnel to achieve the best possible outcomes. You are a problem-solver who can work independently, taking ownership of tasks while effectively coordinating with the layout team to resolve design and layout issues. Your ability to comprehensive knowledge creatively makes you an invaluable asset to our team. What You’ll Be Doing: Designing, developing, and troubleshooting embedded memory compilers. ing skills in memory compilers, focusing on transistor-level circuit design. Understanding various memory design aspects such as read/write margins and timing races to find effective solutions. Interacting with the layout team to address and resolve issues from both design and layout standpoints. Working independently on tasks, ensuring ownership and collaboration to achieve optimal results. Engaging frequently with senior personnel to leverage expertise and enhance project outcomes. The Impact You Will Have: Enhancing the performance and reliability of embedded memory compilers. Driving innovation in memory design, contributing to the development of high-performance silicon chips. Collaborating with cross-functional teams to optimize design and layout processes. Ensuring timely delivery of robust and efficient memory solutions. Contributing to the continuous improvement of design methodologies and practices. Supporting the advancement of Synopsys' technology leadership in the semiconductor industry. What You’ll Need: 2-5 years of experience in Embedded SRAM compilers. Strong understanding of CMOS digital circuits. Knowledge of FinFET technology (preferred). Proficiency in transistor-level circuit design. Ability to analyze and resolve design and layout issues effectively. Who You Are: Innovative and detail-oriented. Collaborative team player. Effective communicator with strong interpersonal skills. Problem-solver with a proactive approach. Self-motivated and able to work independently. The Team You’ll Be A Part Of: You will join a dynamic and dedicated team focused on the design and development of embedded memory compilers. Our team prides itself on fostering an environment of collaboration and innovation, working together to push the boundaries of technology and deliver cutting-edge solutions. As part of this team, you will have the opportunity to engage with experienced professionals and contribute to projects that shape the future of the semiconductor industry. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 8827 Date posted 02/24/2025 Experience : 5yrs to 12 years Expertise in UVM and System Verilog Experience in verification IP modelling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage. Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies. Protocol experience: Should have experience on UCIe/PCIe/CXL/Unipro/USB/MIPI/HDMI/Ethernet/DDR/LPDDR/HBM memory protocol Job responsibilities: Able to contribute to the development of the VIP Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective. Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology perspective. Locally should be to be "go-to" person on all technical aspects of VIP At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 8828 Date posted 02/24/2025 Experience : 5yrs to 12 years Expertise in UVM and System Verilog Experience in verification IP modelling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage. Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies. Protocol experience: Should have experience on UCIe/PCIe/CXL/Unipro/USB/MIPI/HDMI/Ethernet/DDR/LPDDR/HBM memory protocol Job responsibilities: Able to contribute to the development of the VIP Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective. Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology perspective. Locally should be to be "go-to" person on all technical aspects of VIP At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 4543 Date posted 02/24/2025 Design and develop software for interface IP systems Perform Device level and System level, validation and debug, in post-silicon Software Development for new validation methodologies Customer interface to capture requirement and post release support Maximize software productivity and faster time to knowledge Qualifications: Qualification: B.Tech in ECE/CS or equivalent with 4+ year of relevant experience ECE background with experience is software is preferred Skills: Excellent programming and testing skills using C/C++ Experience with embedded or resource-constrained environments Development experience on Unix, Linux and Windows Ability to pick up new flow, learn on the Job MATLAB & PYTHON programming exposure is plus Excellent verbal and written communication skills Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of digital, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk. At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 8115 Date posted 02/24/2025 Responsibilities: The candidate would be part of the VIP group responsible for development of Verification IPs. Core responsibilities would include Designing and developing the VIP/Test-bench, Creating Verification plans, Coding sequences/Test-scenarios, Coverage driven verification. The responsibility would also include enhancement of the existing Verification IP products and interface with customers during VIP deployment. This is an opportunity to work with best-in-class verification, debug tools, Design IP & close collaboration with best protocol experts in the industry. You will work with highly professional and motivated colleagues who value and support your contribution. Requirements: Bachelors/master's with good academic record. 7+ years’ experience in developing HVL based verification environments, preferably using System Verilog. Exposure to coverage driven verification. Experience in verification methodologies like UVM/OVM. Exposure to complex SV test benches involving multiple protocols and VIPs. Experience in VIP development is highly desirable. Should have a strong work exposure on any of the industry standard protocols like PCIe, USB, Ethernet, MIPI etc.. Demonstrates good analysis and problem-solving skills. Have a strong passion for work and driving things to closure. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 8825 Date posted 02/24/2025 Experience : 5yrs to 12years Expertise in UVM and System Verilog Experience in verification IP modelling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage. Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies. Protocol experience: Should have experience on UCIe/PCIe/CXL/Unipro/USB/MIPI/HDMI/Ethernet/DDR/LPDDR/HBM memory protocol Job responsibilities: Able to contribute to the development of the VIP Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective. Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology perspective. Locally should be to be "go-to" person on all technical aspects of VIP At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 7228 Date posted 02/24/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and dedicated individual with a strong background in Electronics and Communication Engineering or Computer Science. You have a keen interest in software development and system validation, and you are eager to your skills in a dynamic and innovative environment. You thrive on solving complex problems and are always ready to take on new challenges. Your technical prowess is complemented by your excellent communication skills, making you an effective team player and a valuable contributor to any project. You have a meticulous eye for detail and a commitment to delivering high-quality work. You are not only technically proficient but also adaptable, able to quickly learn new tools and methodologies. Your previous experience in embedded systems, board-level testing, and programming in C/C++ sets you apart, and you are excited about the opportunity to work with high-speed serial interfaces and FPGA-based setups. Your proactive approach and analytical mindset enable you to excel in a fast-paced, collaborative environment. What You’ll Be Doing: Developing and testing software for validation and automation purposes. Performing device-level and system-level validation and debug in post-silicon environments. Executing software tests in verification environments to ensure product quality. Working with FPGA-based setups to run validation tests and update FPGA RTL modules as needed. Creating detailed test and validation reports with statistical analysis. Interfacing with customers to capture requirements and provide post-release support. The Impact You Will Have: Contributing to the development of cutting-edge technology that drives innovation in various industries. Ensuring the reliability and performance of high-speed serial interface PHYs like USB, PCIe, and Ethernet. Enhancing the validation and debug processes through meticulous testing and analysis. Improving the overall quality and functionality of Synopsys products through rigorous validation. Supporting the continuous improvement of product development cycles. Providing valuable insights and feedback to enhance future product iterations. What You’ll Need: B.Tech in ECE/CS or equivalent with 3-7 years of previous experience in a similar role/industry. Experience in programming and testing using C/C++. Board-level test and debug experience using lab equipment. Experience with embedded or resource-constrained environments. Development experience on Unix, Linux, and Windows platforms. Ability to quickly learn new workflows and adapt to new technologies. Exposure to MATLAB/Python programming is a plus. Exposure to verification and basic RTL is a plus. Excellent verbal and written communication skills. Who You Are: A proactive and motivated individual with a passion for technology and innovation. An effective communicator who can articulate technical concepts clearly and concisely. A team player who collaborates well with others and contributes to collective goals. A detail-oriented professional with a strong analytical mindset. An adaptable learner who thrives in dynamic environments and embraces new challenges. The Team You’ll Be A Part Of: You will be part of a dedicated team focused on the development and validation of high-speed serial interfaces and embedded systems. The team collaborates closely to ensure the quality and performance of Synopsys products, leveraging a diverse set of skills and expertise. You will work alongside experienced engineers who are passionate about technology and committed to driving innovation. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Responsibilities The India System design team is responsible to own and deliver System design milestones for IBM POWER and mainframe platforms. The team collaborates with Global System design & development teams and stakeholders. As a Physical Design Engineer for PCB, the candidate must have experience to deliver complete custom PCB card designs, which would be used for our hardware products. Responsibilities As Physical Design Engineer, the responsibilities include Work with Card Logic Design and Card Signal Integrity Engineers to deliver complete custom PCB card designs. Implement feedback from bring up efforts for modifications to existing card layouts. Work in the Cadence design space to layout, wire multi-layer PCB designs. Create EC list of changes from one release to the next. Lead Physical Design reviews to support Gerber release schedules Generate and maintain documentation for PCB card designs Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Bachelors in Electrical/Electronics Engineering Experience with CAD tools for PCB design Programming experience (Python, SKILL, etc.) Preferred technical and professional experience Familiarity with server design and architecture. Experience with Cadence tools for PCB design Experience with PCB fabrication processes Multi-disciplinary engineering experience (Mechanical, Thermal, etc.) Experience with Git, GitHub, or other software repository versioning tools

Responsibilities In this role, you are expected to Efficient in LVS/DRC Runset development Hands on experience in working on LVS and DRC runset development and support Knowledge/Exposure in lower process node Have excellent debugging skills. Have strong interpersonal skills needed to coordinate deliverables and requirements from several areas within and outside of the organisation. Have familiarity with ICV , Calibre Physical Design Verification Tools Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 2-5 years of Chip Layout and Runset Coding (ICV / Calibre ) Chip layout fundamentals (understanding the layers and how they connect and the rules on sizing and spacing and the electrical connectivity logic) Runset coding in general, ICV pxl in particular Basic SKILL code (for interfacing with Virtuoso) Basic TCL for interfacing with Custom Compiler and ICV Basic Python scripting VLSI knowledge Proven problem-solving skills and the ability to work in a team environment are a must EDA tool development experience Preferred technical and professional experience Cadence,Synopsys,VLSI Knowledge

Responsibilities 1. Hands on work on custom layout for analog blocks like High Speed SerDes and General purpose IO designs with Cadence Virtuoso on latest technologies like 5nm and below and also take leadership roles in delivery of IPs 2. Work on Floor planning, power design, signal routing strategy, EMIR awareness andparasitic optimisations 3. Understand and apply analog Layout techniques to ensure the design meets performance with minimum possible area and good yield. 4. Participate in building and enhancing layout flow for faster, higher quality design process. 5. Checking physical verifications like DRC/LVS/ERC/ANT/DFM and other IBM internal checks 6. Collaborate with Circuit Designers to solve challenging problems 7. Writing SKILL/PYTHON scripts to automate repetitive tasks 8. Work with Place and Route engineer to integrate custom macros into top level. 9. Able to perform design reviews across global team 10. Work closely with required global teams to ensure the success of the whole product. 11. Leadership in delivery of macros we plan to own from India Job requirements: 1. Experience in doing layouts for analog blocks like SerDes, ADCs, DACs, LDOs, PLLs, BGAP & amplifiers etc. 2. Experience in designing layouts for high-speed circuits is a plus. 3. Layout experience in the following technology nodes:3nm, 5nm and 7nm FinFET. 4. Good team worker with multi-discipline, multi-cultural and multi-site environments 5. Strong fundamental knowledge in semiconductor device physics, layout principles, IC reliability and failure mechanisms 6. Good problem-solving skills are essential where problems are analysed upfront, identifying gaps, and providing optimum solutions7. Knowledge in Skill/perl/tcl/Python scripting is a plus. Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise The Analog layout design engineer with experience in next generation Ultra high speed serial IO link (HSS) interface for Cognitive, ML,DL, and data center applications. The engineer needs to have knowledge in the design and development full custom analog layouts for ultra high speed 32G/50G/112G IO link interfaces. Preferred technical and professional experience Experience in 7 and 14 nm analog layout design. Working on Cutting edge technology and HSS domain . Quick learner, deep layout design knowledge, problem solving skills and good communication skills with cross teams across the Geos.

Alternate Job Titles: Senior Cell Library Design EngineerSenior Logic Library Design EngineerSenior Standard Cell Designer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced Standard Cell Library Design Engineer with a passion for innovation and technology. You hold a Bachelor's or Master's degree from a reputable university and have over three years of experience in designing standard cell libraries. Your expertise extends to optimizing standard cell circuits to achieve superior performance, power, and area (PPA). You have designed complex circuits such as flip-flops, clock gating cells, level shifters, and power gating cells. Your deep understanding of CMOS device characteristics and design rules in submicron process nodes, especially in FINFET/GAA technologies, sets you apart. You are proficient in running high sigma variation analysis and have a knack for layout design and optimization. Your analytical and logical skills are exemplary, and you thrive in a collaborative environment, working effectively with geographically distributed R&D teams. If you are driven by innovation and eager to contribute to groundbreaking technology, we want to meet you. What You’ll Be Doing: Designing and optimizing standard cell libraries to achieve targeted PPA.Developing complex circuits including flip-flops, clock gating cells, level shifters, and power gating cells.Collaborating with layout designers to optimize layout parasitics.Engaging in layout extraction and understanding layout-dependent parameters.Conducting timing and power characterization of standard cells.Working closely with cross-functional teams for optimization across the design chain. The Impact You Will Have: Enhancing the performance, power, and area of standard cell libraries.Contributing to the development of high-impact, cutting-edge technology.Driving innovation in complex circuit design and optimization.Ensuring the successful integration of IP blocks into SoCs.Influencing the design and development of self-driving cars, AI, and IoT devices.Supporting Synopsys’ leadership in the silicon IP market. What You’ll Need: Bachelor's or Master's degree in Electrical Engineering or related field.3+ years of experience in standard cell library design.Expertise in CMOS device characteristics and submicron process nodes.Proficiency in designing complex circuits and running high sigma variation analysis.Experience in layout design and optimization. Who You Are: Strong analytical and logical thinker.Detail-oriented with excellent problem-solving skills.Effective communicator and collaborator.Innovative and passionate about technology.Adaptable and able to work in a dynamic, fast-paced environment. The Team You’ll Be A Part Of: You will join the Logic Library Group, a dynamic team focused on developing high-performance standard cell libraries. The team collaborates closely with other R&D groups to optimize the entire design chain and deliver cutting-edge technology solutions. Together, you will work on innovative projects that drive the future of chip design and integration. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Role Description Role Proficiency: Execute any internal project or small tasks of customer project in any field of VLSI Frontend Backend or Analog design under minimal supervison from the Lead Outcomes As an Individual contributor work on any one task of RTL Design/Module in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc. Analyse and complete the assigned task in the defined domain(s) successfully on-time with minimal support from senior engineersEnsure quality delivery as approved by the senior engineer or project lead Measures Of Outcomes Quality –verified using relevant metrics by Lead/Manager Timely delivery - verified using relevant metrics by Lead/Manager Reduction in cycle time and cost using innovative approaches Number of trainings attended Outputs Expected Quality of the deliverables: Clean delivery of the module in-terms of ease in integration at the top levelEnsure functional spec / design guidelines are met 100% of the time without deviation or limitationDocumentation of the tasks and work performed Timely Delivery Meet project timelines as given by the team lead/program managerHelp with intermediate tasks delivery by other team members to ensure progress Teamwork Teamwork participation; supporting team members in the time of needAble to perform additional tasks in case of any team member(s) is not available Innovation & Creativity Pro-actively plan approach towards repeated work by automating tasks to save design cycle timeParticipation in technical discussion training forum Skill Examples Languages and Programming skills:a. System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice (any one) EDA Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (any one) Technical Knowledge: (any one)a. Understands IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb. Knows Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec. Good knowledge of Physical Design / Circuit Design / Analog Layout d. Good understanding of Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verificatione. Knowledge in Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below Required technical skills and prior design knowledge to execute assigned tasks Ability to learn new skills in case required technical skills are not present to a level needed to execute the project Able to deliver tasks with quality and 100% on-time per quality guidelines and GANTT Strong communication skillsGood analytical reasoning and problem-solving skills with attention to detail Knowledge Examples Previous project experience in any of the design by executing any one of the following RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc. Good Understanding of the design flow and methodologies used in designing Understand the assigned tasks and have sufficient knowledge to execute the project tasks assigned by the client / manager per skill set Additional Comments Required Primary Key skills – STA, nano time Job Description: You will be part of a Physical Design / Timing Closure team for projects with GHz freq range and cutting-edge technologies. You will develop timing constraints for full chip or block level and be responsible for STA signoff for a complex multi-clock, multi-voltage SoCs. You will be responsible for Synthesis, Timing Analysis (STA), CTS at Full Chip or block level for Lower tech node ( Below 14nm) Desired Skills and Experience: B. Tech. / M. Tech. with 2-8 years of experience in Synthesis, STA Expertise in synthesis of complex SoCs at block/top level and writing timing constraints for complex designs with multiple clocks and multiple voltage domains Worked on pre and post layout timing analysis and resolving the issues Expertise on post layout timing closure for multiple tape outs, including timing ECOs and STA signoff Expertise in I/O constraints developments for Industry standard protocols (e.g. DDR1/2/3, SDR, LPDDR, Flash, SPIs, Ethernet, USBHS, USBFS, JTAG, Display etc...) Hands-on experience of working on technology nodes like 28nm, 20nm, 14nm, 10nmGood knowledge of EDA tools from RC, DC, PT, PTSI Experience in formal verification RTL-to-netlist and netlist-to-netlist with DFT constraints Good knowledge of VLSI process and device characteristics Good understanding of deep submicron parasitic effects, crosstalk effects etc.TCL, perl scripting Skills Vlsi,Tlc,Perl

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a talented, energetic, and experienced individual with a passion for Linux administration and cloud operations. With a strong foundation in Azure fundamentals, you excel in maintaining high-performance cloud environments. Your ability to communicate effectively, make practical decisions, and deliver agile goals sets you apart. You bring a wealth of experience in customer support, systems administration, and network operations, making you an ideal candidate for our team. You thrive in a dynamic environment, adept at multitasking and problem-solving, and you are ready to take on the challenge of ensuring the smooth operation of Synopsys Cloud. Your hands-on experience with UNIX system administration, coupled with your proficiency in scripting languages like Shell and Python, makes you a critical asset to our operations support team. What You’ll Be Doing: Design, automate, and support Linux systems and services in a 24*7 production environment.Work both independently and collaboratively to evaluate, recommend, and implement technical solutions that meet business needs.Collaborate with other technical teams to solve problems and continually evolve the technology landscape.Troubleshoot issues to identify root causes and help unblock the customer.Prepare and maintain comprehensive documentation of systems, standards, configurations, and procedures.Support day-to-day operations, including installation, configuration, maintenance, and troubleshooting of the engineering secure computing environment. The Impact You Will Have: Ensuring the high performance and reliability of the Synopsys Cloud environment.Contributing to the seamless operation and security compliance of our cloud infrastructure.Enhancing the efficiency and effectiveness of our technical solutions through continuous evaluation and implementation.Collaborating with cross-functional teams to drive innovation and solve complex technical challenges.Providing critical support and troubleshooting to maintain uninterrupted services for our customers.Maintaining up-to-date documentation to ensure consistency and compliance across our systems. What You’ll Need: Extensive knowledge of Linux operating systems and security patching.Experience in installing, monitoring, and administering Linux systems (Ubuntu and RHEL primarily).One or more Linux System Administrator Certifications.Proficiency with monitoring and logging tools.Strong programming/scripting skills in Shell/Python. Who You Are: Proficient in basic networking fundamentals, including TCP/IP, DNS, subnetting, and routing.Knowledgeable in networking for virtual machines, particularly regarding security and performance.Experienced with remote desktop software solutions, such as VNC, Citrix Xen server, and VDI.Solid understanding of infrastructure services like Kickstart, NFS, DNS, and DHCP.Familiar with Azure resources like VM, Network, NSG, and Blob Storage.Able to communicate technical concepts clearly to both technical and nontechnical users.Proven ability to work collaboratively in a dynamic team environment to resolve complex problems.Enthusiastic and capable of learning on the job. The Team You’ll Be A Part Of: Our team is dedicated to building, operating, and maintaining a high-performance Synopsys Cloud environment. We focus on ensuring smooth operations, compliance with security policies, and driving continuous innovation. You will work alongside a group of highly skilled professionals who are passionate about technology and committed to excellence. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled and passionate Senior Layout Design Engineer with a strong background in analog and mixed-signal (A&MS) integrated circuits. You thrive in a collaborative environment, working closely with cross-functional teams to bring cutting-edge technology to life. Your attention to detail and dedication to quality are evident in your work, and you are constantly seeking ways to improve layout design methodologies and best practices. With a keen understanding of semiconductor process technologies and their impact on layout design, you are adept at using industry-standard EDA tools to create and optimize layout designs. You have excellent problem-solving skills, and your ability to communicate effectively and work well within a team makes you an invaluable asset. What You’ll Be Doing: Collaborate with cross-functional teams to develop and implement layout designs for analog and mixed-signal (A&MS) integrated circuits.Create and optimize layout designs using industry-standard EDA tools.Perform physical verification and design rule checks to ensure design integrity and manufacturability.Participate in design reviews and provide feedback to improve design quality.Work closely with circuit designers to understand design specifications and constraints.Contribute to the development and enhancement of layout design methodologies and best practices.Stay updated with the latest industry trends and advancements in A&MS layout design. The Impact You Will Have: Ensure the highest quality and performance of our analog and mixed-signal integrated circuits.Drive innovation by developing cutting-edge layout designs that push the boundaries of technology.Enhance the manufacturability and reliability of our products through meticulous design and verification processes.Contribute to the overall success of our projects by providing valuable feedback during design reviews.Improve design methodologies and best practices, fostering a culture of continuous improvement.Support the growth and development of junior engineers by sharing your expertise and knowledge. What You’ll Need: Bachelor's or Master's degree in Electrical Engineering or a related field.2+ years of experience in A&MS layout design for integrated circuits.Proficiency in industry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler.Exceptional knowledge of layout design methods, techniques, and methodologies.Experience with physical verification tools, such as Calibre or Assura.Understanding of semiconductor process technologies and their impact on layout design.Excellent problem-solving and systematic skills.Ability to work effectively in a team-oriented environment.Good communication and interpersonal skills. Who You Are: You are an analytical thinker with a strong attention to detail. You have a passion for technology and a drive to stay current with the latest industry trends. Your problem-solving skills are top-notch, and you approach challenges with a methodical and systematic mindset. You work well in a team environment, communicating effectively and collaborating with others to achieve common goals. Your dedication to quality and continuous improvement is evident in your work, and you are always looking for ways to enhance design methodologies and best practices. The Team You’ll Be A Part Of: You will be joining a dynamic and innovative team focused on developing and implementing layout designs for analog and mixed-signal integrated circuits. Our team values collaboration, creativity, and continuous improvement. We work closely with circuit designers, verification engineers, and other cross-functional teams to ensure the highest quality and performance of our products. Together, we are committed to pushing the boundaries of technology and driving the future of chip design. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Hyderabad, Telangana, India Category: Engineering Hire Type: Employee Job ID 6831 Date posted 01/31/2025 Senior Software Developer for atomic-scale simulations GUI Synopsys is seeking a software specialist with strong experience in user interface development for the QuantumATK atomic-scale simulation platform. The QuantumATK group is a team of world leading experts in atomic-scale simulations who are developing the QuantumATK software and the Nanolab GUI. Job: Your job will be to develop the QuantumATK platform and the NanoLab GUI. Your role will be to build state-of-the-art user interfaces that makes it straight-forward for engineers to perform atomic-scale simulations, like setting up plane wave calculations, training machine-learned force fields or simulating molecular dynamics. You must have a background in scientific computing and several years’ experience building complex and powerful user interfaces for scientific applications. Ideally this includes experience with full-stack web development, UI frameworks like React or Vue, and web backend development and server-client based applications. The platform team is spread between Hyderabad (India) and Denmark (Europe), and therefore it is very important for you to be a quick learner, self-driven, innovative and easy to work with. We are looking for outstanding individual that: Has at least a master’s in science, computer science or related fields and has proven experience developing user interfaces for scientific software applications. Has a strong scientific background with clear relevance to atomic scale modelling. Proven experience with development of complex and powerful user interfaces for scientific applications. Requirements: Excellent programming skills, and broad programming experience. Primarily Python and C++ but for this role it is an advantage to have experience with web technologies. 10+ years of industry experience in similar domain Great written and oral communication skills in English. The successful applicant Is an outstanding person with exceptional competences in programming Has a broad set of skills and is ready to them to whatever task assigned Is dedicated with focus on getting the job done without sacrificing quality Is a team player Enjoys communicating and helping other people Has a positive mindset and is motivated by challenging projects Is self-motivated and takes responsibility and initiative At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: As an ideal candidate for the ASIC Digital Design Engineer, Senior role, you are a highly motivated and innovative individual with a deep understanding of ASIC development flow. You are someone who thrives in dynamic environments and embraces the challenges that come with constant technological changes. You are self-motivated, proactive, and able to balance good design quality with tight deadlines. Your excellent communication skills enable you to interact seamlessly with different design groups and customer support teams. You are known for your ability to resolve issues creatively and exercise independent judgment in selecting methods and techniques to obtain solutions. You are a team player who can produce excellent results both as an individual and as part of a team. What You’ll Be Doing: Supporting development and verification of ASIC digital designs for next-generation NRZ and PAM-based SerDes products.Setting up and running lint/cdc/rdc checks using VC-Spyglass and synthesis flow using Design Compiler/Fusion Compiler.Working with Verilog and VCS to ensure design accuracy.Defining synthesis design constraints and resolving STA issues.Setting up and running FPGA prototyping flows to map RTL designs to Xilinx FPGAs. The Impact You Will Have: Contributing to the development of cutting-edge SerDes products that lead the industry.Enhancing the performance, power, and size efficiency of our silicon IP offerings.Enabling rapid market entry for differentiated products with reduced risk.Driving innovation in high-speed digital design and data recovery circuits.Supporting the creation of high-performance silicon chips and software content.Collaborating with a world-class team to solve complex design challenges. What You’ll Need: BSEE or MSEE with a minimum of 2 years of experience in digital design and front-end flows.Proficiency in running lint/cdc/rdc checks and synthesis flow.Experience in coding, verifying Verilog and System Verilog design.Experience of working with minimum supervision and owning and delivering for front-end activities in IP/SOC.Experience of leading technically for front-end activities.Knowledge of digital design methodologies, DFT insertion, synthesis constraints, and flows.Scripting experience in Shell, Perl, Python, and TCL (preferred). Who You Are: Excellent communicator with the ability to interact with diverse teams.Self-motivated and proactive, with a strong attention to detail.A creative problem-solver who can think independently.Capable of working under tight deadlines while maintaining high-quality standards.A team player who can contribute effectively both individually and collaboratively. The Team You’ll Be A Part Of: Join our highly experienced mixed-signal design and verification team, where you will work alongside experts in digital and mixed-signal engineering. Our team is dedicated to developing innovative solutions for the next generation of high-speed SerDes products, providing continuous training and opportunities for growth. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a meticulous and innovative Technical Writer with a passion for technology and a knack for making complex concepts accessible. With 2-4 years of experience in the software or hardware industry, you have a thorough understanding of technical writing processes and can translate technical jargon into clear, user-friendly documentation. You are adept at working autonomously and flexibly with global teams, and you excel in communicating with non-native English speakers. Your ability to prioritize tasks and foster teamwork is second to none, and you thrive in dynamic environments where you can take ownership of projects and drive them to completion. Your experience with semiconductor microprocessor industries or software tools for microprocessors (compilers/debuggers/SDKs) makes you an ideal fit for our team. Additionally, you bring working knowledge of DITA, Adobe FrameMaker, ReStructured Text (ReST)/Markdown, Sphinx/LaTeX infrastructure, JSON/HTML, and GitLab/GitHub, with a preference for those who understand Python code and have experience with defect tracking systems like Jira. What You’ll Be Doing: Gathering information using prototype software, technical specifications, feature demos, and by working with developers and applications engineers.Planning, writing, updating, and delivering user documentation products including release notes, user guides, reference manuals, application notes, and tutorials.Interacting with product teams and other technical writers to ensure comprehensive and accurate documentation.Evaluating the information needs of users and developing creative solutions to address these needs.Adapting materials written by non-native English speakers to ensure clarity and readability.Taking ownership of documentation projects and driving them to completion with minimal supervision. The Impact You Will Have: Enhancing the usability and adoption of Synopsys' ARC® portfolio by providing clear and comprehensive documentation.Supporting over 275 customers worldwide who ship more than 2.5 billion ARC-based chips annually.Contributing to the development of high-performance silicon chips and software content.Facilitating the integration of more capabilities into an SoC, meeting unique performance, power, and size requirements of target applications.Reducing the time-to-market and risk for differentiated products.Enabling engineers and scientists to effectively use and understand our tools and technologies. What You’ll Need: 2-4 years of technical writing experience in the software or hardware industry.Ability to understand and write complex technical concepts for a technical audience.Thorough understanding of technical writing processes.Experience in developer documentation and DevOps.Working knowledge of DITA, Adobe FrameMaker, ReStructured Text (ReST)/Markdown, Sphinx/LaTeX infrastructure, and GitLab/GitHub. Who You Are: You are a self-motivated individual with a strong attention to detail and the ability to work both independently and collaboratively. You possess excellent communication skills and can effectively interact with global teams and non-native English speakers. Your ability to prioritize tasks, adapt to changing requirements, and foster teamwork makes you an invaluable asset to our team. You are passionate about technology and continuously seek to enhance your skills and knowledge in the field. The Team You’ll Be A Part Of: You will join a dynamic team focused on the ARC® portfolio, which includes 32-/64-bit CPU and DSP cores, subsystems, and software development tools. Our team collaborates closely with leading industry vendors to support a broad spectrum of 3rd-party tools, operating systems, and middleware. We are dedicated to providing comprehensive and user-friendly documentation to our global customer base. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys is seeking a creative, ambitious, and talented engineer to fill a full-time Analog CAD Support Engineer position in Noida/Bengaluru/Hyderabad/Pune. This role offers stimulating, challenging, and rewarding work within an excellent environment, providing positive career development opportunities. We are looking for someone who excels in teamwork, understands requirements, and thinks creatively to find solutions. While following established procedures is crucial, having a critical perspective and making informed decisions daily is equally important. The ideal candidate will be responsible and passionate about supporting R&D and improving the design process through automation to enhance quality and productivity. Responsibilities: Enable, support, and debug transistor-level flows and processes.Design, develop, troubleshoot, and debug software tools and flows for the development of integrated circuits.Support a global design team, debug CAD issues, interface with foundries, configure the CAD environment, and design flows.Develop routines and utility programs to aid in the design of integrated circuits.Build productive internal and external working relationships. Requirements: A relevant degree in electronic/microelectronic engineering.5+ years of relevant experience.Strong desire to learn and explore new technologies, demonstrating good analysis and problem-solving skills.Ability to exercise judgment within defined procedures and practices to determine appropriate action.Good knowledge of hardware integrated circuits.UNIX/Linux user knowledge.Proficiency with at least one programming language.Proficiency with scripting languages to automate processes.Good English communication skills.Capability to produce adequate technical documentation. Preferred Qualifications: Experience with the VLSI domain, including familiarity with DRC/LVS extraction, simulation, and EMIR.Experience with Cadence, Custom Designer EDA tools.Experience in data management and job scheduling tools like LSF/GRID Engine.Experience in Python, TCL, or Shell scripting.IC design experience (analog or digital). We design and verify advanced silicon chips for our customers. Our goal is to build faster chips, and we are the best in the world at doing so. We also create the processes and models necessary to manufacture these chips. By working with us, our customers can improve their chips in terms of power, cost, and performance, saving time by shortening their project schedules. At Synopsys, we are involved in groundbreaking technologies that shape the way we live and work, including self-driving cars, artificial intelligence, the cloud, 5G, and the Internet of Things. As a company, we lead the way in developing advanced chip design and software security technologies that power these innovations. If you are passionate about innovation like we are, we would love to meet you. We value inclusion and diversity. At Synopsys, we treat all job applicants equally, regardless of their race, color, religion, nationality, gender, sexual orientation, gender identity, age, military veteran status, or disability.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled and motivated Analog Design Engineer with a passion for developing cutting-edge technologies. You thrive in a collaborative environment and have a deep understanding of analog design fundamentals and device physics. Your experience with high-speed IO designs and advanced technologies positions you as a key contributor to our innovative projects. You possess excellent analytical and problem-solving skills, and your ability to execute circuit design tasks with precision and efficiency is unmatched. Your familiarity with ESD, reliability concepts, and JEDEC requirements for memory interfaces further enhances your expertise. You are an effective communicator with strong interpersonal skills, enabling you to work seamlessly with cross-functional teams across the globe. What You’ll Be Doing: Developing next-generation high-speed memory interface PHY IPs (DDR/HBM/UCIe)Executing projects in advanced technologies with a focus on analytical and problem-solving skillsDesigning high-speed IOs for memory interface PHY IP in CMOS/FinFET/GAACollaborating with cross-functional teams globally to achieve project goalsEnsuring product quality and efficiency in all design tasksStaying updated with the latest industry standards and technological advancements The Impact You Will Have: Driving the development of innovative high-speed memory interface PHY IPsContributing to the integration of advanced capabilities in SoCsEnhancing the performance, power efficiency, and size optimization of target applicationsReducing risk and accelerating time-to-market for differentiated productsCollaborating with global teams to deliver high-quality productsSetting industry benchmarks for advanced analog design technologies What You’ll Need: BTech/MTech degree in a relevant field3+ years of experience in analog design fundamentals and device physicsProficiency in high-speed IO designs in advanced technologiesExperience with ESD and reliability conceptsKnowledge of JEDEC requirements for memory interfaces and standardsFamiliarity with signal integrity and/or power integrity is a plus Who You Are: An analytical thinker with strong problem-solving skillsA collaborative team player with excellent communication and interpersonal skillsDetail-oriented and capable of executing tasks with high precision and efficiencyAdaptable and eager to learn new technologies and industry standardsPassionate about innovation and technological advancements The Team You’ll Be A Part Of: You will be part of a dynamic team of highly competent technical experts focused on developing next-generation memory interface PHY IPs. Our team thrives on collaboration, innovation, and the pursuit of excellence. Together, we drive the integration of advanced capabilities into SoCs, enabling our customers to meet unique performance, power, and size requirements quickly and with reduced risk. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Job Description & Requirements At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Our Solution IP group is ramping up high-performance computing (HPC) demand, therefore we are looking for an enthusiastic engineer to join our Methodology and Analog & Mixed-Signal Circuit Design team. You will be working with an immensely creative cross functional team of analog and mixed signal circuit designers from a wide variety of backgrounds on design and methodology. This position requires hands on experience and working knowledge of mixed signal circuit design best practices, an understanding of silicon IP release requirements, solid scripting skills to automate flows and the ability to drive and train engineers to become experts with new methodologies. Job Responsibilities: Develop and maintain circuit design methodology flows and documentation.Identify and refine circuit implementations to achieve optimal power, area and performance targets.Propose design and verification strategies that efficiently use simulator features to ensure highest quality design.Oversee physical layout to minimize the effect of parasitic, device stress, and process variation.Collaborate with digital RTL engineers on the development of calibration, adaptation and control algorithms for analog circuits.Present simulation data for peer and customer review.Mentor and Review the progress of junior engineers.Document design features and test plans. Required Qualifications: Bachelor with 2 years' experience or MSEE (or PhD) in Electrical Engineering, Computer Engineering, or similar technical fieldIn-depth familiarity with transistor level circuit design - sound CMOS design fundamentals.Silicon-proven experience implementing circuits like bandgap references, voltage regulators.Detailed design experience with high custom logic designExperience optimizing FinFET CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects.Awareness of ESD issues (i.e. circuit techniques, layout). and design for reliability (i.e. electro-migration, IR, aging, etc.).Experience with EDA tools for schematic entry, physical layout, and design verification.High proficiency with spice simulators including HSPICE, Finesim and XAKnowledgeable in Verilog-A and/or System-Verilog for analog behavioral modeling and simulation-control/data-capture. Plus Qualifications: Ability to provide automation for rapid and dynamic design needs is highly sought-afterExperience with STA and cell characterization such as Nanotime, Primetime, SiliconSmartExperienced in STAR or similar extractor to debug extraction issuesExtensive programming skills in languages such as Python, Perl, TCL and C/C++