906 Synopsys Jobs - Page 22

Design Verification Manager We need an experienced DV lead/manager to verify IP/SoC using System Verilog/UVM Exposure to various interface IP like I2C/SPI/UART/USB/NVM/PCIe; Buses AXI/AHB/APB; ARM based SoC designs is needed. Skills: Overall 7+ years industry experience with 5+ years in Design Verification using System-Verilog/C/UVM. Generic knowhow on Digital Design and Verification methodologies. Experience in System Verilog/UVM based IP/SoC verification using advanced technologies. Good understanding of Constraint based Random verification; VIP coding; Test Plan design; Test cases coding; Coverage strategies and measurement Proficient in EDA tools used for Design Verification (e.g. Cadence/Mentor/Synopsys simulation suites; Verilator). Working knowledge of Unix, Linux and SKILL, Shell/Python Script ability. Quick learner with excellent interpersonal, verbal/written communications, problem solving and decision-making skills Traits: Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency. Solutions orientation; Quality driven; Execution minded Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and motivated professional with a passion for solving challenging technical problems in the verification domain. You are open to continuous learning and thrive on working with cutting-edge technologies. You possess excellent communication skills and enjoy collaborating with domain experts across global locations. You have a strong foundation in digital design, HDLs, and System Verilog, and you are proficient in using verification technologies. Your attention to detail and innovative mindset make you a valuable team player who partners effectively with multiple stakeholders. You are self-organized, motivated, and capable of multitasking in a dynamic environment. What You’ll Be Doing: Working on challenging technical problems in the verification domain under the Synopsys Verification Platform. Engaging with HDL/HVL methodologies and dynamic simulation aspects, including debugging. Collaborating with global teams to propose and implement solutions. Utilizing your knowledge of UNIX, Tcl, and other scripting languages to enhance productivity. Participating in continuous learning and staying updated with the latest verification technologies. Contributing to a diverse environment and interacting with domain experts across various locations. The Impact You Will Have: Accelerating the design and verification of high-performance silicon chips. Enhancing the usability and adoption of Synopsys' verification products and solutions. Optimizing chip designs for power, cost, and performance, thereby reducing project schedules. Driving technological innovation and contributing to the development of next-generation processes and models. Fostering collaboration and knowledge sharing within a global team. Supporting the creation of advanced technologies that power self-driving cars, AI, the cloud, 5G, and IoT. What You’ll Need: Bachelor’s degree in Electronics with 3+ years’ experience or a Master’s degree in Electronics with 2+ years’ experience. Proficiency in verification technologies such as Simulation, UVM, SVA, and LRM. Experience with Synopsys EDA tools (e.g., VCS, Verdi) is an advantage. Strong fundamentals in digital design, HDLs (Verilog/VHDL), and System Verilog. Excellent written and oral communication skills for effective global team interactions. Who You Are: A team player with a collaborative mindset and the ability to work with multiple stakeholders. A detail-oriented and innovative thinker who can propose effective solutions. Motivated, proactive, and self-organized with good social communication skills. Open to travel and capable of multitasking in a dynamic environment. The Team You’ll Be A Part Of: You will be part of our Silicon Design & Verification business unit, which focuses on building high-performance silicon chips faster. We are the leading provider of solutions for designing and verifying advanced silicon chips, and we develop next-generation processes and models to manufacture these chips. Our team is dedicated to optimizing chips for power, cost, and performance, and we work collaboratively with global experts to drive innovation. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Senior Digital Design Manager We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: We are seeking a highly motivated and experienced Digital Design Manager to lead a team of seasoned digital design engineers. You possess a deep understanding of the ASIC digital design flow, along with hands-on experience in HDL coding, RTL2GDSII flow, and scripting languages. You excel in managing project execution from defining specifications to silicon validation and characterization. Your leadership skills foster a collaborative environment, driving your team to meet stringent project requirements and deliver superior quality designs. With a minimum of 10 years in digital design and at least 3 years in a managerial role, you bring a wealth of knowledge and a proven track record of successful project completions. What You’ll Be Doing: Work closely with 3DIO Phy Architects to define specifications and micro-architecture, supporting early evaluations and feasibility studies to meet customer and system requirements. Lead the execution of digital design solutions for 3DIO Phy projects, ensuring robust and high-performance designs. Own the implementation of RTL in Verilog and sign-off using Spyglass CDC/RDC/Lint tools. Verify the RTL to test desired functionality, coverage, and corner cases using state-of-the-art verification methods. Oversee the full execution of RTL2GDSII, including timing constraints, DFT insertion, test coverage, formal verification, physical implementation, timing closure, physical verification, EMIR, and reliability sign-off. Support silicon validation and characterization through test chip implementation. Manage team members and operations, including career development and planning. The Impact You Will Have: Drive innovation in digital design solutions for 3DIO Phy projects, enhancing Synopsys' product offerings. Ensure high-quality and robust designs that meet customer requirements and improve system performance. Streamline the digital design process from specification to silicon validation, reducing time-to-market. Lead a team of talented engineers, fostering a collaborative and productive work environment. Contribute to the continuous improvement of design methodologies and best practices. Support Synopsys' position as a leader in the semiconductor industry through successful project deliveries. What You’ll Need: Excellent understanding of ASIC digital design flow with hands-on experience in HDL coding. Proficiency in writing synthesis constraints and basics of STA. Knowledge of Lint/CDC/RDC and RTL2GDSII flow. Working knowledge of scripting languages like Perl, Shell, Python, and Tcl. Experience in leading a small team of digital design engineers to execute projects. Knowledge of high-speed/DDR PHY Layer with lane redundancy implementation is highly desirable. Exposure to FIFO, test (ATE and characterization bench), silicon validation, and debugging. Familiarity with Synopsys toolset is highly desirable. Minimum 10 years of relevant digital design experience with at least 3 years as a people manager. B.E/B.Tech/M.Tech in ECE/EE. Who You Are: Strong leadership skills with a proven track record of managing and developing teams. Excellent problem-solving abilities and attention to detail. Effective communication skills, both written and verbal. Ability to work collaboratively in a fast-paced, dynamic environment. Innovative and proactive mindset with a passion for continuous improvement. The Team You’ll Be A Part Of: You will be part of a highly skilled and dynamic team focused on digital design for 3DIO Phy solutions. The team collaborates closely with architects, verification engineers, and other stakeholders to deliver high-quality and innovative design solutions. Together, you will drive the success of Synopsys' cutting-edge technology projects. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Job Title: Physical Design Engineer · He/She should be able to do top-level floor planning, PG Planning, partitioning,placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He/She should have worked on 65nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. · Provide technical guidance, mentoring to physical design engrs. · Interface with front-end ASIC teams to resolve issues. · Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques. · Timing closure on DDR2/DDR3/PCIE interfaces. · Excellent communication skills. · Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure. · Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools. · Expertise in scripting languages such as PERL, TCL. · Strong Physical Verification skill set. · Static Timing Analysis in Primetime or Primetime-SI. · Good written and oral communication skills. Ability to clearly document plans. · Ability to interface with different teams and prioritize work based on project needs. Experience – 7 to 12 Years Location: Hyderabad/Bangalore Show more Show less

Hyderabad, Telangana, India Category: Engineering Hire Type: Employee Job ID 7482 Date posted 06/10/2025 Alternate Job Titles: Senior Technical Writer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an energetic, experienced, and organized writer passionate about cutting-edge technology. With a keen eye for detail and a knack for making complex topics accessible, you have honed your skills over 3-5 years in the software or hardware industry. Your proficiency with authoring tools like FrameMaker and Oxygen, combined with excellent problem-solving abilities, makes you a standout in your field. You excel in communication, both written and verbal, and thrive in a collaborative environment where you can work independently with minimal supervision. Your dedication to quality and your ability to learn new technologies quickly set you apart. You take pride in your work, care about others, and are committed to doing a good job. Familiarity with semiconductor design flows and tools such as Structured FrameMaker, Oxygen editor, and XML flows is a plus. What You’ll Be Doing: Plan, organize, write, and edit various types of customer documentation. Collaborate with world-class engineers to create essential customer documentation in dynamic formats. Empower customers to design-in and optimize Synopsys products through clear, concise documentation. Translate complex technical information into user-friendly content. Ensure documentation meets industry standards and is easily accessible to global customers. Continuously update and maintain documentation to reflect product updates and new features. The Impact You Will Have: Enhance customer satisfaction by providing clear and comprehensive documentation. Facilitate the adoption and optimization of Synopsys products by global customers. Contribute to the overall success of Synopsys by ensuring high-quality documentation. Support the development of innovative solutions through effective communication. Help maintain Synopsys' reputation as a leader in semiconductor IP and EDA software. Drive continuous improvement in documentation processes and standards. What You’ll Need: Degree or master's in electronics, science, hardware, computing, software, physics, mathematics, or engineering discipline. Other technical disciplines also considered. 3-5 years of technical writing experience in the software or hardware industry. Excellent problem-solving skills and strong logical reasoning. Proficiency with authoring tools such as FrameMaker and Oxygen. Exceptional English writing and speaking skills. Who You Are: Excellent communication and interpersonal skills. Energetic and capable of learning new technologies as necessary. Team player who can work independently with minimal supervision. Detail-oriented and committed to producing high-quality work. Proactive and takes ownership of projects and tasks. The Team You’ll Be A Part Of: You will join a dynamic, inclusive, and diverse team of talented professionals committed to innovation and excellence. Our Technical Publications team works closely with engineers to create documentation that empowers our customers and drives the success of Synopsys products. We value collaboration, creativity, and continuous improvement, and we are dedicated to fostering a supportive and engaging work environment. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Location: Gurugram, India (On-site/Hybrid) Type: Full-Time | Engineering Role We are seeking a skilled and detail-oriented Verilog Engineer to join our hardware design and development team. The ideal candidate will have hands-on experience in digital design using Verilog HDL , and a strong understanding of FPGA/ASIC development cycles . Key Responsibilities Design, implement, and verify digital logic circuits using Verilog Work on FPGA/ASIC development, simulation, and synthesis Perform functional verification and debugging using tools like ModelSim, Vivado, or QuestaSim Collaborate with cross-functional teams including hardware, embedded, and software engineers Create and maintain comprehensive design documentation Optimize RTL code for timing, area, and power based on design constraints Required Skills & Qualifications Bachelor’s or Master’s degree in Electronics, Electrical, or related field 2–5 years of hands-on experience with Verilog HDL, preferably in an FPGA/ASIC environment Solid understanding of digital design concepts (FSMs, pipelines, memory, interfaces, etc.) Experience with simulation and verification tools (e.g., ModelSim, Vivado, Synopsys) Familiarity with synthesis and timing analysis Knowledge of scripting (TCL, Python, Bash) is a plus Good to Have Experience with industry-standard FPGA platforms (Xilinx, Intel/Altera) Exposure to system-level modeling or verification languages (SystemVerilog, UVM) Understanding of hardware-software integration Why Join Us? Work on cutting-edge digital design projects Exposure to full-chip development cycles and real-world applications Dynamic work environment with growth opportunities Based in Gurugram with flexible hybrid options Skills: bash,python,modelsim,fpga,vivado,tcl,asic,timing analysis,synthesis,fgpa,asic design,questasim,verilog,digital design,verilog hdl Show more Show less

DataOps Specialist - Azure - 5+ Years - Gurugam Are you a data enthusiast with expertise in Azure and DataOps? Do you have experience working with data pipelines, data warehousing, and analytics? Our client, a leading organization in Gurugam, is looking for a DataOps Specialist with 5+ years of experience. If you are passionate about leveraging data to drive business insights and decisions, this role is for you! Location : Gurugam Your Future Employer : Our client is a prominent player in the industry and is committed to creating an inclusive and diverse work environment. They offer ample opportunities for professional growth and development, along with a supportive and collaborative culture. Responsibilities Design, build, and maintain data pipelines on Azure platform Work on data warehousing solutions and data modeling Collaborate with cross-functional teams to understand data requirements and provide solutions Implement and manage data governance and security practices Troubleshoot and optimize data processes for performance and reliability Stay updated with the latest trends and technologies in DataOps and analytics Requirements 5+ years of experience in data engineering, DataOps, or a related field Proven expertise in working with Azure data services such as Azure Data Factory, Azure Synapse Analytics, etc. Strong understanding of data warehousing concepts and data modeling techniques Proficiency in SQL, Python, or other scripting languages Experience with data governance, security, and compliance Excellent communication and collaboration skills What's in it for you : As a DataOps Specialist, you will have the opportunity to work on cutting-edge data technologies and make a significant impact on the organization's data initiatives. You will be part of a supportive team that values innovation and encourages continuous learning and development. Reach us : If you feel this opportunity is well aligned with your career progression plans, please feel free to reach me with your updated profile at rohit.kumar@crescendogroup.in Disclaimer : Crescendo Global specializes in Senior to C-level niche recruitment. We are passionate about empowering job seekers and employers with an engaging memorable job search and leadership hiring experience. Crescendo Global does not discriminate on the basis of race, religion, color, origin, gender, sexual orientation, age, marital status, veteran status or disability status. Note : We receive a lot of applications on a daily basis so it becomes a bit difficult for us to get back to each candidate. Please assume that your profile has not been shortlisted in case you don't hear back from us in 1 week. Your patience is highly appreciated. Scammers can misuse Crescendo Globals name for fake job offers. We never ask for money, purchases, or system upgrades. Verify all opportunities at www.crescendo-global.com and report fraud immediately. Stay alert! Profile keywords : DataOps, Azure, Data Engineering, Data Warehousing, Analytics, SQL, Python, Data Governance

Sr. Silicon Design Engineer Hyderabad, India Engineering 66192 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SE NIOR SILICON DESIGN ENGINEER THE ROLE: The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and and problem-solving skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 8+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering LOCATION: Hyderabad / Bangalore #LI-PK2 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SMTS Silicon Design Engineer Bangalore, India Engineering 66143 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SMTS SILICON DESIGN ENGINEER THE ROLE: We are looking for an adaptive, self-motivative Synthesis/PD/STA engineer to join our growing team. As a key contributor, you will be part of a team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Physical Design Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and physical design in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects for the new features to be implemented in layout End-to-end RTL to GDS implementation of complex IPs and supporting the SOC customers Working with RTL team to resolve timing and congestion issues Build and develop methodology to converge multiple PNR blocks from RTL to GDS Analyze design metrics and make implementation choices to optimize PPA PREFERRED EXPERIENCE: ASIC design flow and direct experience with ASIC design in sub-7nm technology nodes Circuit timing/STA, and practical experience with Prime Time or equivalent tools Experience into various sign off flows like EMIR, physical verification, CDC Low power digital design and analysis Expertise in synthesis and physical design flows Modern SOC tools including Synopsys Fusion compiler, Primetime and Redhawk TCL, Perl, Python scripting Strong verbal and written communication skills Ability to organize and present complex technical information Fluent in working with Linux environment Mimimum 12 years of industry experience ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR5 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SENIOR SILICON DESIGN ENGINEER The Role The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and and problem-solving skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 8+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. Academic Credentials Qualification: Bachelors or Masters in Electronics/Electrical Engineering LOCATION: Hyderabad / Bangalore Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. Show more Show less

Senior Manager-VLSI Services to lead customer engagement, project delivery, and team development in our semicon business. Own client relationships for key semicon accounts. Work closely with sales and pre-sales teams to grow business with existing and new clients. Participate in customer calls,solutioning,and proposal creation for new opportunities. Contribute to account mining and business development initiatives in semicon vertical.B.E./B.Tech or M.E./M.Tech in Electronics or related field. 12-16 years of experience in semiconductor/VLSI services with at least 3-5 years in delivery or practice leadership roles. Deep understanding of ASIC/SoC design flow- RTL to GDS2 and/or pre/post-silicon validation. Proven experience managing cross-functional teams and multiple client engagements. Exposure to EDA tools(Synopsys / Cadence / Mentor) , scripting(TCL / Perl / Python) , and project tracking tools(JIRA/MS Project). Excellent communication,client interfacing, and leadership skills.

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: PD Engineer (AMD Experience) Location : Hyderabad Work Type: Onsite Job Type: Full time Job Description: Good understanding of physical design and familiar with RTL2GDS flow. Ability to close tiles/blocks from RTL2GDS including timing, noise, power, IR, phyV, conformal equivalence and all signoff checks. Familiarity with advanced technology nodes(7nm and below) and related issues. Synopsys tool suite experience a must. High frequency(>2Ghz) design experience a plus AMD experience a big plus and highly preferred Work experience: 3 - 5 Years TekWissen® Group is an equal opportunity employer supporting workforce diversity. Show more Show less

Full Chip Physical Design Engineer Job Summary: We are seeking a highly motivated and skilled engineer to join our SoC implementation team. You will be responsible for the physical design of complex ASICs and SoCs, working on full-chip floorplanning, integration, and signoff activities to meet aggressive PPA (Power, Performance, Area) goals. Key Responsibilities: Drive full chip-level physical design flow from RTL to GDSII. Ownership of chip-level floorplanning, partitioning, and integration. Collaborate with RTL, synthesis, DFT, and STA teams to resolve cross-functional issues. Implement place & route flows including timing closure, IR/EM, and congestion optimization. Perform physical verification (LVS/DRC/ERC) and work with foundries to fix violations. Manage static timing analysis (STA) at top level and work closely with timing owners for signoff. Handle power planning and power domain implementation (UPF/CPF-based). Contribute to methodology improvements and automation. Required Qualifications: Bachelor's or Master’s degree in Electrical/Electronics/Computer Engineering or related field. 3–6 years of experience in physical design with at least one full chip tapeout. Hands-on expertise with industry-standard tools such as Synopsys (ICC2, Fusion Compiler, PrimeTime), Cadence (Innovus), and Mentor (Calibre). Strong knowledge of physical design concepts: floorplanning, CTS, routing, timing closure, IR drop, EM, DRC/LVS. Proficiency in scripting languages like Tcl, Perl, Python, or Shell. Familiarity with hierarchical design and ECO flows. Experience: 3 to 6 Years. Location: Bangalore / Hyderabad . Notice Period: Less than 30 days Show more Show less

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Skills/Experience 2-5 years of strong experience in digital front end ASIC design verification Bachelors or Masters Degree in Engineering in Electronics, VLSI, Communications or related field. We are looking for a highly motivated and talented RTL verification engineer to join our team to work on the next generation complex cores used in High End Modem/Mobile chips. In this role, a successful incumbent would: - Develop verification environment and testbench components such as BFM and checkers. - Develop comprehensive test plan for unit level verification of IP/Module features and implement test cases. - Verify design in unit level environment using directed and constrained random testing, assertion-based verification, formal analysis, and functional verification. - Write functional cover-groups and cover-points for coverage closure. - Perform RTL code coverage, assertion coverage, functional coverage and gate level simulations. - Have expertise in verifying designs at system level and block level using constrained random verification. - Operate at Expert level in System Verilog and UVM based verification. - Expertise in coding SV Testbench, drivers, monitors, scoreboards, checkers - Strong and independent design debugging capability. - Understanding of AHB, AXI and other bus protocols, digital design and system architecture - Understanding of TCP/IP Packet Processing Algorithms like Filtering, Routing, NAT, Decipher, Checksum, Ethernet Bridging, Tunneling is a Plus. Should possess good communication skills to ensure effective interaction with Engineering Management and team members. Should be self-motivated with good teamwork attitude and need to function with minimal guidance or supervision Responsibilities Work in close coordination with Systems, Design, SoC team , SW team, Validation & DFT teams to get the goals completed. Developing the Verification Strategy, Testbench architecture and implementing the design verification plan and tests using SV/UVM/C. HW verification using Cadence and Synopsys simulator tools, SV/UVM based TB development, Regression analysis, bug-triage. Formal Verification using Jasper, VCF etc. Power Aware Verification on RTL and DC/PD Gate lebel Netlist. Conducting High-/Mid-/Low- level verification reviews, coverage closure and sign-off on block and Sub-system testing. Assisting SOC team with IP Integration testing at SOC level. Post-Silicon Debugs in close collaboration with Design, Validation and SW teams. Self-Motivated to Execute the defined tasks almost independently with minimal guidance Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3071061 Show more Show less

Role Description Physical Design Engineer Exp:4 to 7 Handled Netlist to GDS II at block level for multiple tape outs. Hands-on experience on technology nodes like 28nm, 20nm, 14nm, 10nm Good knowledge of EDA tools from Synopsys , Cadence and Mentor, particularly experience with ICC, PTSI, Encounter, Nanoroute, Calibre, StarRC Hands-on experience in floor planning, placement optimizations, CTS and routing. Hands-on experience in block/top level signoff STA, physical verification (DRC/LVS/ERC/antenna) checks and other reliability checks(IR/EM/Xtalk) Exposure in physical implementation of timing/functional ECO’s Good knowledge of VLSI process and device characteristics TCL, perl scripting. Skills Physical Design,DRC,LVS,ERC,antenna Show more Show less

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description We are looking for technically sound and highly skilled High-speed SERDES IO PHY Layout designer with 12-15 years of experience. Apart from Serdes PHY Layout, the ideal candidate should have a strong background in analog/IO design principles, hands-on experience with layout tools, and a passion for solving challenging technical problems. Key Responsibilities: Develop and optimize Serdes PHY, analog and mixed-signal IC layouts, ensuring high performance and manufacturability. Collaborate with design engineers to understand design requirements and translate them into precise layouts. Strong experience in debugging DRC, ERC, LVS, EMIR and PERC issues independently. Work closely with the physical design team to integrate custom blocks into the overall chip design. Identify and resolve layout-related issues, providing creative solutions to meet design specifications. Conduct design reviews and provide technical feedback to improve layout practices and methodologies. Stay up-to-date with industry trends, tools, and technologies to continuously enhance layout processes. Qualifications 12-15 years of experience in Serdes Phy, Analog and Mixed-signal IC layout design. Proficiency in layout tools such as Cadence, Synopsys, or Mentor Graphics. Hands-on experience with custom layout design for various Serdes Phy, Analog and IO circuits is required, including expertise in Bandgap references, LDOs, Clocking circuits, GPIOs, DDR IOs. Familiarity with custom digital layout (i.e. high speed logic paths). Knowledge of signal integrity issues (i.e. clock/data routes, differential routing, shielding). Strong understanding of analog/IO design principles, including circuit performance and parasitic effects. Aware of layout techniques to mitigate ESD, latch-up issues. Holds advanced knowledge of CMOS and FinFET technologies and their impact on design and performance issues in deep sub-micron process nodes, specifically 5nm and below. Experience with layout concepts that incorporate reliability considerations, including techniques for managing electromigration (EM), IR drop, and self-heating. Experience with layout optimization for power, performance, and area (PPA) metrics. Excellent problem-solving skills and attention to detail. Effective communication and teamwork abilities. Preferred Skills: Knowledge of scripting languages (e.g., Skill,TCL and SVRF) for automation tasks. Qualifications Bachelor’s or Master’s degree in Electronics or Electrical Engineering Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Show more Show less

Job role: At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk. We're looking for ASIC Digital Verification Engineers with different experience levels to join the team! Does this sound like a good role for you? You will be working on VLSI IP verification of controllers related to complex protocols. You will be part of the Solutions Group at our Bangalore Design Center, India. The position offers learning and growth opportunities. This is a Technical Individual Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in the Verification domain. Job Responsibilities - Understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create micro-architecture and detailed design for some of the components of the Test Environment for the DesignWare family of synthesizable cores in protocol areas such as Ethernet/DSC/AMBA (AMBA2, AXI, CHI)/ SD/eMMC/DDR/PCIe/ USB/ MIPI Be an individual contributor in the Verification Tasks – Architect testbenches, coding of TE, debug, verification coverage improvement, etc. Will contribute to technical review of TE Code of medium complexity. Will contribute to technical process and quality improvement to achieve high quality deliveries Will be expected to Solve complex/ abstract problems The candidate should be able to analyze the coverage metrics and improve them with definition of additional test cases in CRV environment. The candidate will work in a project and team-oriented environment with teams spread across multiple sites, worldwide. May need to take the role of technical lead for a few of the components of the Test Environment and achieve high quality verification with a small team of verification engineers. The role offers ample scope to mentor junior engineers and interns and to enhance ones’ leadership skills. Key Qualifications And Experience Must have BSEE/ MSEE in EE with 5 to 8 years of relevant experience in the following areas: Verification of IP Cores or SoC Designs for Set Top Boxes, Mobile handsets, Smart Devices, etc. Knowledge of one or more of protocols: Ethernet/AMBA (AMBA2, AXI, CHI)/ SD/eMMC/USB/ DDR/PCIe MIPI/DSC. Knowledge of Ethernet protocol will be plus. Hands on experience with creating detailed design of components of Test Environment from Functional Specifications/ Test Environment Specifications. The TE must have used methodologies such as UVM, OVM Test Planning, Coverage Planning, Assertion Planning Hands on experience with System Verilog coding and Simulation tools; Deep Knowledge of OOPs Concepts Experience with Perforce or similar revision control environment Knowledge of Perl/Shell scripts. Exposure to quality processes in the context of IP design and verification is an added advantage In addition, the candidate should have good communication skills, will be a team player, and will have good problem-solving skills. Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, colour, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability. Show more Show less

Sr. Staff- ASIC Verification. This is a verification focused individual contributor’s role. The candidate will be part of the DesignWare IP Verification R&D team at our Bangalore Design Center, India. Implement state-of-the-art Verification environments for the DesignWare family of synthesizable cores and perform Verification tasks for the IP cores. Work closely with RTL design team and be part of a global team of expert Verification Engineers. Domains will include but not be limited to USB, PCI Express, Ethernet, AMBA. Job role will have a combination of Test planning, Test environment coding both at unit level and system level, Test case coding and debugging, FC coding and analysis and meeting quality metric goals and regression management. Requirements: BS/BE in EE with 8+ years of relevant experience or MS with 6+ years of relevant experience in the verification of IP cores and/or SOC verification. Experience in developing HVL based test environments, developing and implementing test plans, implementing and extracting verification metrics such as functional coverage. HVL coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and relevant debugging tools. Exposure to verification methodologies such as UVM/VMM/OVM is required. Familiarity with HDLs such as Verilog and scripting languages such as perl is highly desired. Exposure to IP design and verification processes including VIP development is an added advantage. Basic understanding of functional & Code coverage. It is essential that the individual has good written and oral communication skills and is able to demonstrate good analysis, debug and problem solving skills and be self-driven. Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk. At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: As an ideal candidate, you are a seasoned VLSI professional with a strong background in product engineering. You thrive in cross-functional environments, seamlessly collaborating with diverse teams to drive product success. With a minimum of 8 years of experience in VLSI product engineering, you have a deep understanding of analog and digital SOC design flows and methodologies. You have a proven track record in RTL Development, RTL Verification, and RTL to GDS flow, demonstrating your ability to innovate across different technology nodes. Your customer-centric approach allows you to prioritize and manage multiple projects effectively. You excel in communication, adept at interfacing with various organizational levels, and possess strong written and verbal skills. Your proficiency in database management and data cleanliness ensures the integrity of our product portfolio. Additionally, you stay abreast of industry trends and emerging technologies, continuously enhancing your expertise. What You’ll Be Doing: Collaborate with cross-functional teams to drive product success. Develop and execute product engineering strategies. Serve as the technical interface between teams. Engage with sales and pre-sales teams to align product goals. Build and manage time plans and schedules for product development. Ensure seamless communication and coordination across different levels of the organization. The Impact You Will Have: Drive innovation in VLSI product engineering, influencing the development of cutting-edge technology. Enhance product quality and performance through strategic engineering initiatives. Foster collaboration and knowledge sharing across cross-functional teams. Contribute to the successful execution of complex projects, meeting organizational goals. Enhance customer satisfaction by delivering high-quality, reliable products. Support the growth and development of the Synopsys product portfolio. What You’ll Need: Minimum 8 years of experience in VLSI product engineering. Exposure to analog and digital SOC design flows and methodologies. Experience in RTL Development, RTL Verification, and RTL to GDS flow. Proven track record of working on different technology nodes and driving product innovation. Strong customer-centric approach with the ability to manage multiple projects. Who You Are: Excellent communicator with strong written and verbal skills. Adept at interfacing with various organizational levels. Proficient in database management and ensuring data cleanliness. Knowledgeable about industry trends and emerging technologies in VLSI. Motivated and experienced professional looking for a new challenge. The Team You’ll Be A Part Of: You will be joining a dynamic and innovative project management team at Synopsys. Our team is dedicated to driving product success through strategic engineering initiatives and cross-functional collaboration. We focus on delivering high-quality, reliable products that meet the evolving needs of our customers and the industry. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Alternate Job Titles: SPICE/FastSPICE Simulation Engineer Custom Compiler Frontend Engineer Senior Application Engineer - SPICE Simulation We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced engineer with a deep understanding of SPICE/FastSPICE simulation and custom compiler frontend applications. You excel at problem-solving and have a strong background in designing and verifying analog circuits, including clocking circuits and data converters. You are proficient in memory design and have a solid grasp of competitive EDA tools in digital, analog, and mixed-signal design and verification. Your exceptional communication and presentation skills enable you to interface effectively with customers and R&D teams. Your proactive approach and project management expertise make you a valuable asset in driving business growth and technical innovation. With your advanced degree and extensive experience, you are ready to tackle complex technical challenges and contribute to the success of Synopsys. What You’ll Be Doing: Providing technical support to customers for SPICE/FastSPICE simulation and custom compiler frontend applications. Collaborating with Sales, R&D, Product Application Engineers, and Marketing to drive business growth. Understanding customer requirements and exploring business opportunities. Creating simulation flows and debugging technical issues. Leading technical benchmarks and customer engagements. Writing customer requirement specifications and conducting product training sessions. The Impact You Will Have: Enhancing customer satisfaction and loyalty through exceptional technical support. Driving the adoption and successful implementation of SPICE/FastSPICE simulation and custom compiler solutions. Improving product usability and performance based on customer feedback and insights. Fostering strong relationships with customers and understanding their needs and challenges. Collaborating with R&D teams to influence product development and innovation. Contributing to Synopsys' reputation as a leader in technology and innovation. What You’ll Need: Design and verification experience in clocking circuits (PLLs), data converters (ADCs, DACs), and other analog circuits. Experience in memory design and verification of SRAM, SRAM compilers, DRAM, Flash, or other non-volatile memories. Knowledge of competitive EDA tool products in digital, analog, and mixed-signal design and verification. Proficiency in English for written and verbal communication. Excellent communication, presentation, problem-solving, and project management skills. BSEE or equivalent with 2-5 years of relevant experience, or MS/Ph.D. with 2 years of relevant experience. Who You Are: Collaborative and team-oriented, with strong interpersonal skills. Proactive and self-motivated, with a strong sense of ownership and responsibility. Detail-oriented and meticulous, with a focus on delivering high-quality solutions. Adaptable and flexible, with the ability to thrive in a fast-paced and changing environment. Passionate about technology and innovation, with a continuous learning mindset. The Team You’ll Be A Part Of: You will be part of a dynamic and innovative team focused on providing exceptional technical support and solutions to our customers. Our team collaborates closely with Sales, R&D, Product Application Engineers, and Marketing to ensure the successful adoption and implementation of SPICE/FastSPICE simulation and custom compiler solutions. We are dedicated to continuous improvement and innovation, always striving to enhance the customer experience and contribute to the success of Synopsys. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned professional with a passion for RTL Design and Verification. With 4-9 years of experience in electronics, you possess a deep understanding of RTL Signoff Checks such as LINT, CDC, and RDC. You thrive in dynamic environments and are adept at developing timing constraints for synthesis and timing. Your hands-on experience with static verification tools, including Spyglass, positions you as an expert in your field. You have a keen eye for detail and can identify design/architecture pitfalls across clock/reset domain crossings. Your ability to synthesize designs and ensure RTL and gate equivalence through formality checks is unmatched. You are a collaborative team player, ready to integrate IPs in SoCs/Subsystems and create RTL designs that meet customer needs. If you are ready to leverage your expertise in a role that shapes the future of semiconductor design, Synopsys is the place for you. What You’ll Be Doing: Perform RTL Quality Signoff Checks such as LINT, CDC, and RDC. Understand design/architecture and develop timing constraints for synthesis and timing. Run preliminary synthesis to ensure design can be synthesized as intended. Run formality to ensure equivalence of RTL and gates. Integrate IPs in SoCs/Subsystems and create RTL design as per customer needs. Collaborate with cross-functional teams to deliver high-quality RTL designs. The Impact You Will Have: Ensure high-quality RTL Signoff for semiconductor designs. Contribute to the development of cutting-edge semiconductor technologies. Improve design efficiency and performance through effective timing constraints. Enhance the reliability and functionality of SoCs and subsystems. Support customer success by delivering tailored RTL designs. Drive innovation in RTL Design and Verification methodologies. What You’ll Need: B.E/B. Tech/M.E/M. Tech in electronics with 4-9 years’ experience in RTL Design and Verification. Hands-on experience with static verification tools such as Spyglass performing LINT, CDC, RDC. Good conceptual understanding of design/architecture pitfalls across clock/reset domain crossings. Strong grasp of RTL rule checks. Proficiency in synthesis and timing constraints development. Who You Are: Detail-oriented with a focus on quality and precision. Excellent problem-solving skills and analytical thinking. Strong communicator, able to collaborate effectively with cross-functional teams. Adaptable and open to learning new technologies and methodologies. Proactive and self-motivated, with a passion for innovation. The Team You’ll Be A Part Of: The role is for RTL Design and Signoff of IP/Subsystem/SoC Design in the System Solutions Group (SSG). At SSG, we are a team of experts in various Synopsys technologies to deliver architecture, design, verification, implementation, tools, and methodology to enable our customers to complete their most challenging SoC Design projects. Our work spans from sub-blocks to full turnkey end-to-end SoCs. Our customers range from start-ups to industry leaders, commercial companies, and government agencies. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

At Juniper, we believe the network is the single greatest vehicle for knowledge, understanding, and human advancement the world has ever known. To achieve real outcomes, we know that experience is the most important requirement for networking teams and the people they serve. Delivering an experience-first, AI-Native Network pivots on the creativity and commitment of our people. It requires a consistent and committed practice, something we call the Juniper Way. Job Description At Juniper, we believe the network is the single greatest vehicle for knowledge, understanding, and human advancement the world has ever known. To achieve real outcomes, we know that experience is the most important requirement for networking teams and the people they serve. Delivering an experience-first, AI-Native Network pivots on the creativity and commitment of our people. It requires a consistent and committed practice, something we call the Juniper Way. Physical Design Engineer Experience: 4+ Years Job Specification Work with internal Design teams and Methodology teams to successfully Lead/implement Physical Designs of multiple blocks of Complex ASICs . The position requires good understanding of the physical design flow from RTL to GDS & several chips tapeout experience. The successful candidate should possess in-depth knowledge & experience in physical synthesis, design planning, floor planning, place & route, static timing analysis and design closure & physical verification Responsibilities Will be responsible for all aspects of Physical Design for Fullchip/Blocks covering Floorplanning, Placement, Budgeting, Clock Tree planning & analysis, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis & fixes, Low Power solution development & implementation. Prefer sound knowledge in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, Calibre, internal tools & flow, etc. Work closely with the methodology team to solve the implementation challenges & provide inputs to improve the Physical design flow. Experienced in design automation. Understanding of Timing constraints, SI prevention, Power reduction. Must have prior experience with Synopsys/Cadence/Mentor place and route tools. Must have completed design in 16nm and or 7nm.. Proficient in Unix/TCL/Perl. Good communication and presentation skills. Requires good interpersonal skills and problem-solving ability. Minimum Qualifications 4+ years experience in ASIC physical design Experience with block implementation, extraction, timing and or full-chip designs Strong communication skills Strong hands-on TCL/Perl development skills Preferred Qualifications Experience as a full-chip floorplanning, routing, or timing lead for a large silicon project Track record of taping out complex chips on advanced process nodes About Juniper Networks Juniper Networks challenges the inherent complexity that comes with networking and security in the multicloud era. We do this with products, solutions and services that transform the way people connect, work and live. We simplify the process of transitioning to a secure and automated multicloud environment to enable secure, AI-driven networks that connect the world. Additional information can be found at Juniper Networks (www.juniper.net) or connect with Juniper on Twitter, LinkedIn and Facebook. WHERE WILL YOU DO YOUR BEST WORK? Wherever you are in the world, whether it's downtown Sunnyvale or London, Westford or Bengaluru, Juniper is a place that was founded on disruptive thinking - where colleague innovation is not only valued, but expected. We believe that the great task of delivering a new network for the next decade is delivered through the creativity and commitment of our people. The Juniper Way is the commitment to all our colleagues that the culture and company inspire their best work-their life's work. At Juniper we believe this is more than a job - it's an opportunity to help change the world. At Juniper Networks, we are committed to elevating talent by creating a trust-based environment where we can all thrive together. If you think you have what it takes, but do not necessarily check every single box, please consider applying. We’d love to speak with you. Additional Information for United States jobs: ELIGIBILITY TO WORK AND E-VERIFY In compliance with federal law, all persons hired will be required to verify identity and eligibility to work in the United States and to complete the required employment eligibility verification form upon hire. Juniper Networks participates in the E-Verify program. E-Verify is an Internet-based system operated by the Department of Homeland Security (DHS) in partnership with the Social Security Administration (SSA) that allows participating employers to electronically verify the employment eligibility of new hires and the validity of their Social Security Numbers. Information for applicants about E-Verify / E-Verify Información en español: This Company Participates in E-Verify / Este Empleador Participa en E-Verify Immigrant and Employee Rights Section (IER) - The Right to Work / El Derecho a Trabajar E-Verify® is a registered trademark of the U.S. Department of Homeland Security. Juniper is an Equal Opportunity workplace. We do not discriminate in employment decisions on the basis of race, color, religion, gender (including pregnancy), national origin, political affiliation, sexual orientation, gender identity or expression, marital status, disability, genetic information, age, veteran status, or any other applicable legally protected characteristic. All employment decisions are made on the basis of individual qualifications, merit, and business need. Show more Show less

To work as a timing engineer (STA) and taking care of end to end timing responsibilities for complex SoC projects. Job Description In your new role you will: Defining and verification of STA constraint for Functional and Test/SCAN Modes. Defining PVT’s corners required for covering all desired scenarios for a design Knowledge on OCV/AOCV/POCV derates. Understanding of Prime-Time and TEMPUS tools, which helps in quick debugging of design/timing issues. VASTA timing closure based on chip IR drop. Knowledge on signal SI analysis and PT-PX flow. Your Profile You are best equipped for this task if you have: Bachelors or Masters in Electrical/Electronics Engineering. BE/B.Tech/M.Tech with 6+ years. Project leading knowledge is preferred. Delivery oriented, Passionate to learn and explore, Transparent in communication, Flexibility related to project situations. Candidate should have strong STA fundamentals. Has done timing sign-off including timing margin calculations. independently, hands-on STA lead of projects. Experience in handling STA of multi-power domain designs & constraint mode merging. STA flow development, abstraction with bottleneck identification. Proficient in design margins and SDC constructs. TAT reduction in multi-mode, multi power domain/designs. Generate timing ECOs for Physical design. Drive ambitious schedules and enables dependent teams to accomplish. Interface to design team and PD team and drive TAT reduction for PD. Has experience in mentoring junior engineers. Proficient with EDA tools from Synopsys/Cadence. Excellent analytical & communication skills. Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone. Proficient in Tcl and Perl or other scripting relevant language is a plus. Contact: Swati.Gupta@infineon.com #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon. Show more Show less

www.Sevyamultimedia.com VerificationLead About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills Approach We support a mix of engagement models to support diverse client requirements. Engagement Models Turnkey (SoW) Engagement Staff Augmentation (T&M) Offshore Design Center Key Enablers Hands on Leadership Proven Industry Experts TSMC DCA Parternship Collaboration with Academia ================ Design Verification Lead DV lead/manager to verify IP/SoC using System Verilog / UVM --------------------------------------------------------------------------------------- Exposure to various interface IP like I2C/SPI/UART/USB/NVM/PCIe; Buses AXI/AHB/APB; ARM based SoC designs is needed. Skills: Overall 7+ years industry experience with 5+ years in Design Verification using System-Verilog/C/UVM. Generic knowhow on Digital Design and Verification methodologies. Experience in System Verilog/UVM based IP/SoC verification using advanced technologies. Good understanding of Constraint based Random verification; VIP coding; Test Plan design; Test cases coding; Coverage strategies and measurement Proficient in EDA tools used for Design Verification (e.g. Cadence/Mentor/Synopsys simulation suites; Verilator). Working knowledge of Unix, Linux and SKILL, Shell/Python Script ability. Quick learner with excellent interpersonal, verbal/written communications, problem solving and decision-making skills Traits: Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency. Solutions orientation; Quality driven; Execution minded Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! NVIDIA is looking for a best-in-class ASIC STA Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency for today's AI platforms! Come and take a part in designing our groundbreaking large scale and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What You Will Be Doing Be in charge of full chip and/or chiplet level STA convergence from early stages to signoff. Take part in top level floor plan and clock planning. Optimize, together with CAD signoff flows and methodologies. Digital Partitions' and analog IPs' timing integration, giving feedback to PD/RTL and driving convergence. Work closely with logic design and DFT engineers to define and implement constraints for the various work modes, including their optimization for runtime and efficiency. What We Need To See B.SC./ M.SC. in Electrical Engineering/Computer Engineering. 3-8 years of experience in physical design and STA Proven experience in RTL2GDS and STA design and convergence Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.) Hands on STA experience from early stages to signoff using Synopsis Primetime. Deep knowledge in timing concepts required. Great teammate. NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry! JR1995153 Show more Show less