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TitlePE and LB timing ACL Digital

5.0 - 9.0 years

0 Lacs

karnataka

On-site

As a candidate for the position in Bengaluru, you should possess a minimum of 5 years of experience in the field. Your responsibilities will include: - .LIB timing file generation - Verilog Modelling - Analog design characterization - Familiarity with Cadence Spectre and Synopsys Hspice - Assist with Analog Quality Checks including EM/IR simulation In addition to the technical skills mentioned above, you should have: - Embedded product knowledge such as UFS and eMMC - Proficiency in Embedded C, C++, and Python - Background in automation - Experience in debugging using tools like T32 would be highly valued If you meet the criteria mentioned above and are seeking a challenging opportunity in t...

Posted 2 months ago

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