2 Synopsys Fc Jobs

About Marvell Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Built on decades of expertise and execution, Marvells custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, youll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, automotive, and networking applications. What You Can Expect In this role based in Hyderabad, you will work with a global team on both the physical design of complex chips as well as the methodology to enable an efficient and robust design process. You will be responsible for maintaining, enhancing, and supporting Marvell&aposs Place and Route Flow, leveraging industry-standard EDA tools. Your tasks will include performing synthesis, place and route, as well as timing analysis and closure on multiple intermediate and complex logic blocks. You will play a crucial role in developing and implementing timing and logic ECOs, collaborating closely with the RTL design team to drive modifications that address congestion and timing issues. Additionally, your involvement with the global timing team will include debugging and resolving any block-level timing issues encountered at the partition level. This position provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell. What We&aposre Looking For Bachelors Degree in Electronics/Electrical Engineering or related fields and have 5-8 years of related professional experience OR a Masters degree and/or PhD in Electronics/Electrical Engineering or related fields with 4-7 Years of related professional experience. In your coursework, you must have completed a digital logic course and projects that involved circuit design, testing, and timing analysis. Good understanding of standard Synthesis to GDS flows and methodology. Good scripting skills in languages such as Perl, tcl, and Python. Good understanding of digital logic and computer architecture. Hands-on experience in advanced technology nodes upto 2nm. Strong hands-on experience in blocks/subsystem P&R implementation using Cadence Innovus and Synopsys FC. Good experience in block level signoff power, timing, PV closure & debugging skills. Knowledge of Verilog/VHDL. Good communication skills and self-discipline contributing in a team environment. Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. Were dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what its like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Show more Show less

Tenstorrent is at the forefront of AI technology, setting new standards in performance, usability, and cost efficiency. With the evolution of AI reshaping computing, there is a growing need for innovative solutions that integrate advancements in software models, compilers, platforms, networking, and semiconductors. Our team comprises diverse technologists who have created a high-performance RISC-V CPU and share a common passion for AI, striving to develop the ultimate AI platform. We value collaboration, curiosity, and a dedication to solving complex problems. As we expand our team, we are seeking individuals at all levels to contribute to our mission. We are currently seeking an experienced engineer to lead the clock design efforts for our IP, CPU, and SoC teams. In this role, you will be responsible for defining clocking strategies that strike a balance between stringent timing requirements, power efficiency, and area constraints. You will collaborate closely with RTL, PD, and power engineers to construct robust, high-performance systems. This position is based in Bangalore and requires onsite presence. We invite candidates with a minimum of 6 years of experience to apply for this role. Throughout the interview process, candidates will be evaluated for their proficiency, and job offers will be made based on the assessment, which may vary from the details provided in this listing. As an ideal candidate: - You possess a solid background in clock tree synthesis and clock network design. - You are adept at working with timing, CDC, and low-power design methodologies. - You have experience working with advanced technology nodes, particularly 5nm or below, influencing design decisions. - You enjoy developing scripts to automate tasks and streamline engineering workflows. Key responsibilities include: - Taking charge of the end-to-end clock architecture for intricate SoCs. - Collaborating effectively with RTL, physical design, and power teams to achieve project objectives. - Proficiency in utilizing tools like Synopsys FC, ICC2, and scripting languages such as Python, Perl, or Tcl. - Demonstrating a problem-solving mindset focused on enhancing efficiency and resilience. This role offers the opportunity to: - Architect clocking strategies that are scalable across IP, CPU, and SoC designs. - Learn techniques to minimize power consumption and jitter while meeting aggressive power, performance, and area (PPA) targets. - Enhance workflows and reduce manual interventions through intelligent automation. - Address and resolve challenges specific to cutting-edge technology nodes. Join us at Tenstorrent and be part of a dynamic team dedicated to pushing the boundaries of AI technology.,