212 Sv Jobs - Page 3

Job Description: We're looking for a verification SME, responsible for the SoC verification process and designing the next-generation HBM DRAM products. Deep understanding of SoC Verification, testbench architecture, SoC verification methodologies, and 2.5D & 3D package integration. Responsibilities: • Develop test plans at SOC Level and analyze Coverage. • Build verification environments to verify complex SOCs. • Develop Random/Directed test in RTL and GLS environments. • Review architectural specifications to ensure high quality. • Work with customers to understand their verification &validation requirements • Debug and identify root causes and solutions for pre-silicon and post-silicon is...

VeriFast Technologies is hiring Sr Verification Engineers in Pune with minimum 3+ to 5+ years of experience with PCIe/PCI-E, UCIe, CXL, strong SV, UVM, hands on AXI with ASIC/SoC. Do call me at 9934158404 or drop your CV to [HIDDEN TEXT]. Let's chat about it.

Long Description 1. ASIC RTL Engineer : RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory PCIe/DDR/Ethernet - Any One I2C,UART/SPI - Any One Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One scripting languages like Make flow, Perl ,shell, python - Any One LocationBangalore / Hyderabad / Kochi Experience - 7+ - Lead/Architect 2. Emulation Lead JD - Emulation Lead (Zebu/ HAPS /Veloce/Palladium and Module Build (End to End) Location - Bangalore / Hyderabad Experience - 7+ - Lead/Architect 3. Lead Design Verification Engineer : 7+ years of hands-on DV experience in SystemVerilog/UVM. Must be able to own and drive the verification of a block / s...

Key Responsibilities: Develop, integrate, and validate RTL designs for complex ASIC/SoC projects. Perform lint checks, CDC analysis, and RDC verification using industry-standard tools (Spyglass, Meridian, etc.). Collaborate with design verification teams to ensure functional correctness and quality sign-off. Drive synthesis-friendly RTL coding practices and participate in design reviews. Debug and resolve issues across RTL, lint, CDC, and timing. Work closely with architecture and verification teams for spec-to-RTL implementation . Required Skills & Expertise: 5+ years of experience in ASIC RTL design & verification . Strong hands-on expertise in Lint, CDC, and Meridian tools. Proficiency in...

As an experienced professional with 2-6 years of expertise in micro architecture design and system design using Verilog, SV, or VHDL, you will play a crucial role in this position. Your responsibilities will include: - Utilizing Spyglass Lint, CDC, SoC Integration, logic design with Verilog and SV, ASIC Synthesis, STA, timing closure, and working with any Processor based system. - Demonstrating familiarity with design using SoC, AXI/AHB/APB System bus, and peripherals such as Ethernet, PCIe, DDR, USB, UART, SPI, and I2C. - Conducting synthesis, timing analysis using various industry standard tools, and proficiency in TCL and Python scripting. To excel in this role, you should ideally possess...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performanc...

This position is for RTL designer role in DSP processor team. The position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the challenges posed by advanced technologies. The successful candidate will possess detailed understanding of RTL design, synthesis, static timing analysis, formal verification, PLDRC, clock domain crossing, and low power techniques. Knowledge and experience of microprocessor integration is a definite advantage. Skills/Experience Must have 3 to 15 years of practical experience with details of RTL development (VHDL and/or Verilog) including: functional and structural RTL design, design partitioning, simulation and regression, collaboration wi...

General Summary: This position is for RTL designer role in DSP processor team. The position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the challenges posed by advanced technologies. The successful candidate will possess detailed understanding of RTL design, synthesis, static timing analysis, formal verification, PLDRC, clock domain crossing, and low power techniques. Knowledge and experience of microprocessor integration is a definite advantage. Skills/Experience Must have 3 to 15 years of practical experience with details of RTL development (VHDL and/or Verilog) including: functional and structural RTL design, design partitioning, simulation and regression,...

Industry experience in analog/mixed signal behavioral modeling at various levels of abstraction and full chip verification (AMS and DMS DV) using SV RNM or Custom UDNs. Good understanding of analog design concepts and mixed signal design architectures. Exposure to products that integrate a wide variety of Analog/Mixed-Signal building blocks such as Power Management, PLL/Synthesizers, bandgap references, oscillators, SerDes etc. and related digital control and signal processing. Demonstrated experience of verification plan development, UVM verification environment development/debug and verification of complex mixed signal products at block, Subsystem & chip-top levels. Familiarity with Analog...

Role Overview: You will be responsible for verifying IP sub-systems with a minimum of 5 years of solid verification experience. Your key tasks will include creating SV/UVM based testbenches, writing test cases, developing checkers, monitors, debugging, and performing coverage analysis. Preference will be given to candidates with IP level verification experience in high-speed IOs such as DDR/USB/PCIE. Additionally, you should have a good understanding of infrastructure and tools like Perl and Python. Key Responsibilities: - Create SV/UVM based testbenches - Write test cases - Develop checkers and monitors - Debug issues - Perform coverage analysis Qualifications Required: - Minimum 5 years of...

Role & responsibilities : * Pre-Silicon Support: Simulate, analyze, and debug pre-silicon full-chip designs to ensure functional accuracy. * Test Case Development: Develop stimulus and test cases to increase the functional coverage for DRAM, SRAM, and other emerging memory technologies. Core Requirements: * Strong Communication Skills: Ability to collaborate effectively within a team. * Leadership: Guide new team members and engineers, sharing your knowledge and experience. * Analytical Expertise: Deep understanding of complex CMOS and/or gate-level circuit designs. * Proficiency in SPICE and/or Verilog simulations. Preferred candidate profile : Required Skills: * Experience with SystemVeril...

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Lead the development of the verification plans, environment, testbenches and writing testcases to verify Cache structures & protocols in processor. Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design Work with development team to ensure coverage criteria is met. Required education Master's Degree Required technical and professional expertise 5 + years of experience in Functional Verification of processors or ASICs. 3+ years of experien...

Job Description Total experience (5 -7 years) with SOC GLS experience of minimum 3+ years Hands on experience in GLS (Zero Delay, SDF, PAGLS) Excellent debugging skills and fixing issues Knowledge in SV/UVM and test bench flow Good experience in EDA tools such as Synopsys Verdi, Cadence NC Sim. Understanding of SOC Architecture Education Qualification: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field.

Design Verification Engineer (5+ Years) Responsibilities: Develop, enhance, and maintain verification environments and testbenches using System Verilog and UVM. Create test plans from design specifications and contribute to coverage-driven and metric-driven verification goals. Build and integrate UVM components such as agents, monitors, scoreboards, sequencers. Write, debug, and automate tests to verify complex RTL modules/IP blocks; perform test regression and analyse results. Implement and analyse functional and code coverage metrics for quality signoff. Work closely with design, software, and architecture teams for feature coverage and bug resolution. Document verification results, covera...

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Lead the development of the verification plans, environment, testbenches and writing testcases to verify Cache structures & protocols in processor. Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design Work with development team to ensure coverage criteria is met. Required education Master's Degree Required technical and professional expertise 6 + years of experience in Functional Verification of processors or ASICs. 3+ years of experien...

* As a Formal verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. * Develop the verification environment and test bench and creating testcases.* Develop skills in IBM Formal verification tools and methodologies. * Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Required technical and professional expertise * 5 - 10 years of relevant industry experience * Proven experience in Formal/Functional Verification - Demonstrated execution experience of verification of logic blocks verification. * Knowledge of formal methodology, Knowledge of...

Job Title: Lead / Staff Engineer ASIC IP & Subsystem Verification Location : Bangalore Notice Period : Immediate to 30 Days About the Role We are seeking a highly experienced Design Verification professional (Lead/Staff Engineer) to drive IP, Subsystem, and SoC-level verification for Micron’s advanced memory and semiconductor products. This role is hands-on with opportunities to mentor small teams, own verification strategy, and ensure signoff-quality verification closure across a wide range of products (digital, mixed-signal, low-power). Key Responsibilities Lead end-to-end verification for IPs, Subsystems, and SoCs – including planning, execution, and coverage closure. Architect, enhance, ...

Required Skills & Experience 3 to 5 years of experience in IP/Subsystem/SoC design verification. Strong knowledge in SystemVerilog, UVM , and functional coverage. Understanding of digital design concepts (FSMs, pipelines, FIFOs, memory, clock/reset domains). Experience with protocols like AMBA (AXI/AHB/APB) or similar. Familiarity with assertion-based verification (SVA) . Hands-on with EDA tools (Cadence Xcelium, Synopsys VCS, Mentor Questa, or equivalent). Proficiency in debug tools (Verdi, SimVision, DVE). Strong problem-solving and debugging skills. Scripting skills in Python/Perl/TCL/Makefile for automation. Good to Have (Optional) Exposure to DFT/DFX verification, UPF/power-aware flows,...

Job Description : Sub System Verification Lead : Team- Functional subsystem Verification team for MediaTek's TV/Automotive/5G/other advanced SoC development Roles Close co-work with global teams to define/verify new features for Mediatek next-gen SoC products Mentor cross-domain teams to achieve the verification goals Responsible for enhancing/developing subsys/SoC test plans and verification methodologies specific to a subsys. Be the domain expert to facilitate and set verification guidelines for global teams Opportunity to interact with top management for subsys verification related expert opinions Drive internal and 3rd party resources to build a strong subsys expertise at MediaTek Bangal...

Job Title: Lead Design Verification Engineer Location: m Bangalore Job Type: Full-time Experience Level: 7+ years Department: Hardware Engineering / VLSI Design Job Summary: We are seeking a highly experienced Lead Design Verification Engineer to lead verification efforts for complex digital designs. The ideal candidate will drive testbench architecture, verification planning, and execution for ASIC/SoC or FPGA-based designs, ensuring first-time-right silicon or system functionality. You will work closely with RTL design, DV, and system engineering teams to deliver high-quality products. Key Responsibilities: Lead and drive the verification strategy, planning, and execution for IP, subsystem...

order General information #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness,...

Job Description: We are seeking Design Verification Engineers with 515 years of experience in SystemVerilog, UVM, and SoC/IP-level verification. The role involves building scalable verification environments, driving coverage closure, debugging complex issues, and ensuring robust design quality. Key Responsibilities & Requirements: Strong experience in ASIC/IP/SoC design verification (block/IP/SoC level). Expertise in SystemVerilog, UVM, testbench architecture, and reusable verification components. Ability to create and execute detailed verification plans. Skilled in constrained-random verification, functional coverage, assertions, and scoreboarding. Solid knowledge of AMBA protocols (AXI, AH...

General Summary: Job Function : Camera Design Lead/Staff Candidate will be responsible for design/developing next generation SoCs sub systems for mobile phone camera . Candidate will be working on ASIC based on the latest technology nodes. This role will require the candidate to understand and work on all aspects of VLSI development cycle like architecture, micro architecture, Synthesis/PD interaction and design convergence. Skills/Experience 5-10 years with Masters (6 to 10 years with Bachelors) Solid experience in digital front end design for ASICsSolid Expertise in RTL microarchitecture and design coding in Verilog/SV for complex designs with multiple clock and power domainsExpertise with...

General Summary: QCT's Bangalore Wireless R&D(WRD) HW team in Bangalore is looking for experienced Wireless HW design verification engineers to work on Qualcomms best in class chipsets for mobile phones, wearables and IOT . Candidate will be working with ASIC designs on the latest technology nodes. This role will require the candidate to understand and work on all aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies. In this role of WRD Verification Engineer, you will be verifying Wifi and/or Modem from both TX and RX perspective. The responsibilities will majorly include :...

Wafer Space is looking for smart and enterprising Design Verification engineers to join the team and engage in cutting-edge work within a dynamic and exciting work environment. We are currently involved in various in-house turnkey projects and client site projects, many of which require comprehensive verification from specification to closure, including the development of complete DV environments in SV-UVM. As a Design Verification Engineer at Wafer Space, your responsibilities will include building SV, SV UVM, OVM based environments and working with a variety of networking and other protocols. The role requires 3 to 7 years of experience in IP verification, with a strong background in SV/UV...