65 Sv Jobs - Page 2

Hiring Now ASIC Design Verification Experts | Automotive Chip Projects Location: Bangalore, Pune, Noida, Chennai Experience: 3 to 20+ Years | Notice Period: Immediate to 45 Days Send Resume to: prabhu.p@acldigital.com JD 1: VIP Development – Technical Lead / Manager 10–20+ years in UVM-based VIP Development & Integration Strong expertise in PCIe, SerDes, MIPI CSI/DSI, Ethernet, SATA Experience in IP & Chip-Level Verification for automotive SoCs Strong in SystemVerilog , Assertions , and Protocol Checkers Ability to lead verification strategy and mentor IC team members Excellent debugging, ownership, and communication skills IC + Team Leadership responsibility in a global ODC setup JD 2: Processor-based SoC / Subsystem DV – Lead & Engineer Roles Lead (15+ yrs): Strong in ARM Cortex-M/A, SoC bring-up (boot code, ISRs), AMBA protocols – Led 2–3 SoC DV projects, 10+ team size, Xtensa experience is a plus Engineer (3–10yrs): – SoC DV with C/Assembly testcases, SV/UVM, AHB/AXI protocol (Team: 9) – SoC or IP DV with SV/UVM, AHB/AXI, C/ASM optional (Team: 6) Why Join Us? Work on flagship automotive chip programs Fast-track your career with IC & Lead roles Get rewarded with attractive referral bonuses

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. This role is based in Bengaluru. But you"™ll also get to visit other locations in India and globe, so you"™ll need to go where this job takes you. In return, you"™ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. We make real what matters! This is your role Deploy Siemens EDA ProFPGA prototyping software and hardware solutions at customers and guide the customers to successful design bring-up Work closely with R&D to solve problems, review product specs, and find good general solutions that improve the overall product Train AE"™s and customers on the solutionWin pre-sales engagements in cooperation with the technical sales teams Successfully deploy our solutions at early customer sites. This means educating the customer on best practices and tool requirements. It also means working with R&D to make the tool improvements necessary for the customer"™s success. Ensure existing customers maximize the value they receive from the solution by developing and enhancing methodology that exploits the solution"™s capabilities Ensure customers are kept up-to-date with the latest enhancements Provide customer requirements to R&D and marketing Work with QA and Docs to help them create tests and documentation that will improve our solutions Create examples and tutorials that are shipped with our products. Develop and/or refine methodology employed in creating and using prototypes and maximizing the value of our prototyping solution We don"™t need superheroes, just super minds! A good understanding of FPGA based hardware prototyping platforms Working knowledge of multi FPGA prototyping flows(Synthesis, partitioning, PnR, runtime and debug) Practical insights into the application and usage of FPGA prototyping systems Knowledge of design mapping, testbench mapping and transactor development Expertise of hardware/software debug solutions related to FPGA prototyping Knowledge of test bench acceleration, ICE and co-model solutions Highly proficient in HDLs (Verilog/SV) for RTL design and HVLs (SV/UVM) for verification Solid background in Functional Verification, RTL synthesis and PnR flows Conversant with SoC design and architecture concepts Good communication and inter-personal skills. #disw #LI-EDA #LI-Hybrid We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. At Siemens, we are always challenging ourselves to build a better future. We need the most innovative and diverse Digital Minds to develop tomorrow"™s reality. Find out more about the Digital world of Siemens here: www.siemens.com/careers/digitalminds We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Siemens Software. Where today meets tomorrow

Looking for Siemens EDA ambassadors Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the Increasingly complex world of chip, board, and system design. Real trendsetters in every language. Before our software developers write even a single line of code, they have to understand what drives our customers. What is the environment and the user story based on? Implementation means trying, testing, and improving outcomes until a final solution emerges. Knowledge means exchange discussions with colleagues from all over the world. Join the team and enjoy the freedom to think in completely new categories. Be an integral part of a team that is developing comprehensive verification IPs for interfaces such as PCIe Gen5/Gen6, USB3.2, 400Gigabit Ethernet, DDR5, LPDDR5 and leading coherency protocols like CXL for use with Questa RTL simulation! We make real what matters. This is your role. Questa verification IP"™s help design teams find more bugs in less time than conventional simulation techniques. You will specify, implement, test and enhance these verification components for a wide range of end user applications. You will work on technologies involving SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger. You will work well with TMEs and Field AEs or directly with customers to deploy or resolve customer issues. We don"™t need superheroes, just super minds. We are seeking Electronics Engineers (B.Tech/M.Tech) or professionals from related fields, graduated from reputed institutes, who possess strong expertise in verification engineering and bring 1-4 years of hands-on experience to the table. You've sound knowledge of System Verilog for test bench with exposure to verification methodologies like UVM, VMM etc. You've intimate knowledge of one or more standard bus protocols, like PCIe, USB, SATA, NVMe, Flash, DIMM etc. We are phenomenal teammates, resilient and sincere, with a passion for learning new things and building our knowledge base in new areas! We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we welcome applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit, and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, bonus scheme, generous holiday allowance, pension, and private healthcare. Transform the everyday! #LI-EDA #LI-Hybrid #DVT

Title : AMS Verification Engineer Location : Manipal/Bangalore Experience : 5 - 15 Years Salary : As per the Industry Key Responsibilities: Basic understanding of analog / mixed signal circuits ( like op-amps, amplifiers, current mirrors, LDO, ADC .. etc ). Understand the usage of cadence tools like Xcellium, Spectre, Simvision .. etc. Writing Verilog, Verilog-A/MS, Real Number Models. Develop/Use SV, UVM based Verification flows Understand metric based Verification closure using Code and Functional coverage Good scripting skills using perl, python is a plus. Must possess good communication, debugging skills and ability to work well in a team

Extensive experience in IP/SOC Verification. Proficiency in System Verilog and UVM. Hands-on experience in verifying IP protocols such as PCIe, DDR, USB, Ethernet, CXL, HDMI, MIPI, DSI, CS, GLS, CPU Verification, or other high-speed protocols. Familiarity with scripting languages like Python, Perl, TCL, etc. Experience in assembly language or C is a plus. Ability to develop testbenches from scratch and take ownership of the entire verification process, including subsystem/chip-level coverage. Strong debugging skills. Location: Chennai and Ahmedabad,Bengaluru,Hyderabad,Pune

An experienced and passionate ASIC Digital Verification Engineer with a deep understanding of RTL-based IP cores and complex protocols. You have over 12 years of experience in functional verification and are adept at making architectural decisions for test bench designs. You are proficient in SystemVerilog (SV) and Universal Verification Methodology (UVM), and you have a proven track record of implementing coverage-driven methodologies. You bring a wealth of knowledge in protocols such as DDR, PCIe, AMBA, and more. Your technical expertise is matched by your strong communication skills, ability to work independently, and your innovative problem-solving capabilities. Your experience may also include familiarity with functional safety standards such as ISO26262 and FMEDA. What You ll Be Doing: Making architectural decisions on test bench design. Writing verification plans and specifications. Implementing test bench infrastructure and writing test cases. Implementing a coverage-driven methodology. Leading technical aspects of verification projects. Collaborating with international teams of architects, designers, and verification engineers. The Impact You Will Have: Enhancing the robustness and reliability of IP cores used in critical applications. Driving innovation in verification methodologies and tools. Ensuring high-quality deliverables through rigorous verification processes. Improving productivity, performance, and throughput of verification solutions. Contributing to the success of Synopsys customers in industries such as AI, automotive, and server farms. Mentoring and guiding junior engineers in the verification domain. What You ll Need: Knowledge of protocols such as DDR, PCIe, AMBA (AXI, CHI), SD/eMMC, Ethernet, USB, MIPI. Hands-on experience with UVM/VMM/OVM, test planning, and coverage closure. Proficiency in SystemVerilog and UVM, object-oriented coding, and verification. Experience with scripting languages like C/C++, TCL, Perl, Python. Experience with functional safety standards such as ISO26262 and FMEDA (preferred). Who You Are: Independent and precise in your work. Innovative and proactive in problem-solving. Excellent communicator and team player. Detail-oriented with a strong analytical mindset. Eager to learn and grow within a technical role

Role & Responsibilities : As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Lead the development of the verification plans, environment, testbenches and writing testcases to verify Cache structures & protocols in processor. Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design Work with development team to ensure coverage criteria is met. . Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Required Professional and Technical Expertise : 9 + years of experience in Functional Verification of processors or ASICs. 3+ years of experience in the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Core architecture/micro-architecture verification Multi-processor Cache (L2/L3) Coherency, Memory Hierarchy Verification Minimum one full life cycle leadership experience of a processor/SoC verification flow with focus on Cache Coherency Verification Developed test-plans and test strategies for IP/unit/block level verification of Cache Coherency structures in processor/SoC Good object-oriented programming skills in C++/SV, scripting languages like Python/Perl. Knowledge of functional verification methodology like UVM/OVM Knowledge of HDLs (VHDL/Verilog) Worked on multiple levels of verification (unit/element/sub-system/system level) Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenarios, debugging and triaging fails Experience in driving verification coverage closure. Preferred technical and professional experience Additional skill Stress testing and ability to identify corner case scenarios.

SOC Verification engineers with 3+ years of experience Knowledge of ARM architecture, CPU fundamentals & Cache coherency Experience with C/C++, assembly, and scripting languages. Familiarity with low-power design and verification Develop CDV UVM verification environments at system level Verify CPU connectivity to IP blocks Develop SoC test plans and test cases and track metrics including code and functional covera Job Requirement: Bachelors or Masters in EE/CS or related field 3+ years of SoC in ASIC/FPGA verification experience Proficiency in SV and UVM Experience with simulation, emulation, and formal verification Strong debugging and problem-solving skills Experience (years) : 3+ Year Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Interested candidates can forward resume to : vlsi.team07@gmail.com

About The Role The graphics GT validation team is responsible for validating industry-leading GPU (3D, Media, Compute) hardware intellectual property (IP) blocks and system-on-a-chip (SoC) products for discrete graphics and throughput computing. We strive to lead the industry through continuous innovation and world-class engineering. We work closely with partners across Intel and do not let any organizational boundary get in the way of solving problems. We are looking for a GPU Design Verification Engineer to join our team. In this position you will help us with the following responsibilities Pre-silicon verification and content development of Intel's GPU IP, with focus on 3D/Compute pipelines and Memory Fabric. Engaged in the full lifecycle of verification from planning to test execution. Closely interface with architecture and design teams to understand design product requirements and develop comprehensive test plans and test content. Conduct, participate in test plan, test reviews, develop verification tests, their execution, debug, and triage of failures. The ideal candidate will have the following skills in addition to the qualifications listed below. Thoughtful and perceptive analytical skills A genuine curiosity for understanding the system Be dedicated and committed to creative problem solving and getting things done Strong verbal and written communication skills and Work well in a team environment Qualifications Btech/BS and Ms/MTech in Electrical Engineering, Computer Engineering, Electronics, or related field. BTech/BS with minimum 3 years of experience or Ms/MTech with Minimum 1 Year experience in the above-mentioned specializations.Your experience should be in the following areas Strong background in Pre-Si verification. Strong background in Logic Design and Architecture. Experience with a design simulator, functional coverage concepts and implementation, test development, execution, and debug. Working knowledge of SV assertions, Coverage Point coding.Development and execution of validation test plans. Familiarity of C/C++ languages and experience in software development using any of these languages is an added advantage Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

About The Role Role and Responsibilities You will be part of Intel Core Design Team driving Intel's latest CPUs in the World's leading process technologies. Develops pre-Silicon functional verification tests to verify system to meet design requirements. Creates test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests. Analyzes and uses results to modify test bench and tests. We're looking for a highly motivated, Pre-Silicon Verification Engineer who is responsible to ensure: Development of Complex Pre-Silicon Verification environment Development of Verification Components and coverage plans Write and execute validation Plans to ensure Right First Time Success of our Products Work directly with hardware architects, logic designers to influence overall SoC and system design. Qualifications Qualifications Candidatemust possess a master's degree in Electronics or Computer Engineering with at least 8+ or more years of experience in related field. Preferred Qualifications: Experience in Processor verification Experience with Specman/SV Language is plus Experience in verifying Power Mgmt, Cache controllers and memory features is plus Experience with Formal verification techniques is a plus Strong background in scripting- PERL/Python System hardware and software debug skills Understanding of software and/or hardware validation techniques Solid understanding of system and processor architecture, and the interaction of computer hardware with software. Candidate should demonstrate excellent Self-motivation, communication, strong problem solving, excellent in cross-site communication and teamwork skills. Inside this Business Group The Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core „¢, and critical IPs that power Intel's leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies.

About The Role Develops pre silicon functional validation tests to verify system will meet design requirements Creates test plans for RTL validation defining and running system simulation models and finding and implementing corrective measures for failing RTL tests Analyzes and uses results to modify testingKnowledge of Verilog ,System Verilog, UVM Based Testbench developmentUnderstanding of code functional coverage system Verilog assertion codingGeneral Scripting and programming skills Python Per TCL etcFormal verification would be a plusIP Level testbench development using SV and UVMTestplan development using Verification planner, tracking and closer of code and functional coverageReq LocationSRR4 Bangalore About The Role Your responsibilities include but are not limited to: Define and develop test env to verify the IP/Sub System functionality. Define Test plans and develop Tests contents.Define Checkers/monitors strategy. Define and Develop Assertions.Define Cover points and analyze functional coverage with analysis. Define Volume regressions strategy and run simulations followed by failure debugs. Develop formal verification assertions, properties. Define and perform Performance Verification. Mentoring and coaching junior verification engineers. Leadership to manage stake holders with end to end objectives in mind. The candidate should have ability to work effectively with both internal and external teams/stakeholders. Should possess strong problem solving/communication skills. Should be a very good team player. Qualifications QualificationsYou must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications:Candidate should possess a Bachelor's degree in Electrical, Electronics, Computer Engineering or Computer Science or any related field with 7+ years' experience -OR - a Master's degree Electrical, Electronics, Computer Engineering or Computer Science or any related field with 5+ years experience -OR- PhD degree in Electrical, Electronics, Computer Engineering or Computer Science or any related field with 3+ years experience in:VLSI design.Verification/validation tests.Expertise in System Verilog/C++/OVM or UVM methodology and/or Formal Verification techniques.Preferred qualification:System simulation models, and debugging RTL/tests.Experience with Cache Coherency protocols or PCIE/CXL would be a huge plus Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

**Verification Planning and Execution*: 2. Develop and execute comprehensive verification plans. 3. Close verification with coverage closure, ensuring high-quality results. 4. Apply standard ASIC verification techniques, including test planning, testbench creation, code and functional coverage, directed and random stimulus generation, and assertions. 5. **Testbench Development*: 6. Create and enhance testbenches using SystemVerilog (OVM/UVM) or other standard testbench languages. 7. Implement reusable Verification IP (VIP) components. 8. Collaborate with third-party VIP providers. 9. Developing vertically and horizontally re-usable test-benches 10. **Methodology and Flows*: 11. Demonstrate a solid understanding of ASIC design and verification methodologies. 12. Apply object-oriented programming principles effectively. 13. Implement constraint random verification methodology. 14. **Technical Skills*: 15. Proficiency in SystemVerilog (OVM/UVM) and other relevant languages (C/C++, Perl, Tcl, Python, Verilog PLI, SV/DPI) 16. Familiarity with industry standards (e.g., I2C/SPI/AHB). 17. Gate level simulation 18. Experience with low-power verification using UPF (Unified Power Format) is a plus. 19. Knowledge of formal verification techniques is advantageous. 20. **Collaboration and Communication*: 21. Work effectively with internal teams and external customers. 22. Strong written and verbal communication skills. 23. Initiative, analytical problem-solving abilities, and adaptability within a diverse team environment.

Design Verification Engineer In-House ODC Project We are looking for an experienced Design Verification Engineer to be part of our in-house ODC project . The ideal candidate will be an individual contributor with expertise in SoC, Subsystem, or IP verification using high-speed serial protocols and advanced protocols . The candidate should have a strong command of SystemVerilog (SV) and UVM , including writing test cases, sequences, OOPs concepts, and UPF implementation . The role requires hands-on experience in scratch-level work , ensuring verification coverage from the ground up. Experience: 4 to 20+ years Location: Bangalore, Chennai, Pune Notice Period: Immediate to 30 days If you are interested please share your updated CV chandana.l@acldigital.com

About The Role You will be part of Intel Data Center and AI group driving Intel's latest AI SoCs in the World's leading process technologies. In this role you will be responsible to develop SoC / SS pre-Silicon functional verification environment along with a team of highly skilled engineers to verify system level design . Your role spans end to end Pre-Silicon verification from verification architecture definition to PRQ/ customer support.We're looking for a highly motivated, Pre-Silicon Verification Lead Engineer who will be responsible to : Define Verification architecture that is scalable across multi level verification for most advanced multi die SoCs Define domain level verification plan Develop VIPs, protocol checkers, scoreboards. Define coverage, assertion based verification methodologies. Work directly with hardware architects, logic designers to influence overall SoC and system design. Mentor and technically lead junior engineers. Qualifications Candidate should have a Bachelors/ Masters in Electrical or Computer Science Engineering or related field with 15+ years of technical experience. Related technical experience should be in/withSilicon Design and/or Validation/Verification.Preferred QualificationsExperience in CPU/ GPU verification Experience with SV/ UVM Language Experience with Formal verification techniques is a plus Strong background in scripting - PERL/Python System hardware and software debug skills Understanding of software hardware co-validation techniques Solid understanding of system and processor architecture, advanced memory and IO technologies Candidate should demonstrate excellent Self-motivation, communication, strong problem solving, excellent in cross-site communication and teamwork skills. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world.

About The Role Architects, develops and integrates layered Verification IPs, testbenches, testplans and test suite to validate the integrity and quality of Verification IPs and compliance with standards and SoC architecture & micro-architecture requirements. Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and conform to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, micro-architects, full chip architects, RTL developers, post-silicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from post-silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience. Related technical experience should be in/withSilicon Design and/or Validation/Verification. Preferred Qualifications: Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. Proficiency in UVM/SV constrained-random coverage based design verification. UVM/SV Verification IP architecture, development and validation experience. Robust understanding of fundamental principles of cache coherency in multi-processor SOCs, and experience with layered protocols - transaction layer, data link layer, and PHY layer. Experience with one or more scripting languages to facilitate automation. Strong debug skills and self-reliance in taking an issue to closure with internal and external partners. Takes ownership of assigned tasks. Keen problem solver, strong communicator, quick learner, effective team player and open to learning and teaching new and more efficient validation execution techniques to meet time-to-market. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation testbenches and test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world.

About The Role You will be part of Intel Data Center and AI group driving Intel's latest AI SoCs in the World's leading process technologies. In this role you will be responsible to develop SoC / SS pre-Silicon functional verification environment along with a team of highly skilled engineers to verify system level design . Your role spans end to end Pre-Silicon verification from verification architecture definition to PRQ/ customer support.We're looking for a highly motivated, Pre-Silicon Verification Lead Engineer who will be responsible to : Define and execute verification plans for one or more of the following domain, Coherency/ Memory/ Power Management/ Security/ domains Develop VIPs, Test stimulus, protocol checkers, scoreboards necessary for execution. Define and execute coverage, assertion based verification framework. Work directly with hardware architects, logic designers to influence overall SoC and system design. Mentor and technically lead junior engineers. Qualifications Candidate should have a Bachelors/ Masters in Electrical or Computer Science Engineering or related field with 15+ years of technical experience. Related technical experience should be in/withSilicon Design and/or Validation/Verification. Preferred Qualifications: Experience in CPU/ GPU verification Experience with SV/ UVM Language Experience with Formal verification techniques is a plus Strong background in scripting - PERL/Python System hardware and software debug skills Understanding of software hardware co-validation techniques Solid understanding of system and processor architecture, advanced memory and IO technologies Candidate should demonstrate excellent Self-motivation, communication, strong problem solving, excellent in cross-site communication and teamwork skills. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world.

About The Role Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 15+ years of technical experience. Related technical experience should be in/withSilicon Design and/or Validation/Verification.Preferred Qualifications Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. Proficiency in UVM/SV constrained-random coverage based design verification. OVM/UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. UVM/SV Verification IP architecture, development and validation experience. Robust understanding of fundamental principles of cache coherency in multi-processor SOCs, and experience with layered protocols - transaction layer, data link layer, and PHY layer. Experience with one or more scripting languages to facilitate automation. Strong debug skills and self-reliance in taking an issue to closure with internal and external partners. Takes ownership of assigned tasks. Keen problem solver, strong communicator, quick learner, effective team player and open to learning and teaching new and more efficient validation execution techniques to meet time-to-market. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation Experience on Pre-Si validation on Emulation, preferably Zebu.Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world.

About The Role Conducts verification of IP and/or SoC microarchitecture using formal verification tools, methodologies, and technologies based on model checking and equivalence checking algorithms. Creates comprehensive formal verification test and coverage plans including definition of formal verification scope, strategy, and techniques. Creates abstraction models for convergence on the design, carves out the right boundaries for the design, and tracks, verifies, and applies abstraction techniques. Develops formal proofs to implement the verification plan, reviews the completed proofs, and develops new formal verification methodologies. Performs convergence on design by creating formal verification methodology, abstraction, and simulation techniques. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications: 5+ years of experience in the verification of IPs Hands on experience in applying formal property verification for Ips signoff at least for 3 years Hands on experience in resolving convergence issues using FV on multiplies Managing and Guiding juniors in their verification task, Stakeholder management. Preferred Qualifications: Expertise in FV verification planning and strategies Good understanding of FV tools and capabilities Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Function :Camera Design Lead/Staff Candidate will be responsible for design/developing next generation SoCs sub systems for mobile phone camera . Candidate will be working on ASIC based on the latest technology nodes. This role will require the candidate to understand and work on all aspects of VLSI development cycle like architecture, micro architecture, Synthesis/PD interaction and design convergence. Skills/Experience Solid experience in digital front end design for ASICsSolid Expertise in RTL microarchitecture and design coding in Verilog/SV for complex designs with multiple clock and power domainsExpertise with various bus protocols like AHB, AXI and NOC designs Experience in low power design methodology and clock domain crossing designsUnderstanding of full RTL to GDS flow to interact with DFT and PD teams Experience in Tools like Spyglass Lint/CDC checks and waiver creationExperience in formal verification with Cadence LEC Experience in mobile Multimedia/Camera design is a plus DSP /ISP knowledge is a plus. Working knowledge of timing closure is a plusExpertise in Perl, TCL language is a plusExpertise in post-Si debug is a plus Good documentation skillsAbility to create unit level test plan General Should possess good communication skills to ensure effective interaction with Engineering Management and mentor group members. Should be self-motivated and good team working attitude and need to function with little direct guidance or supervision Responsibilities Digital design and development (RTL) working in close collaboration with Multi-site leadsDeveloping the micro architecture and implementing the design using Verilog/SV. Integrate and deliver complex subsystem to SoCDesign and implement defined tasks independently. Work in close coordination with Systems, Verification, SoC team , SW team, PD & DFT teams to get the goals completed.Analyze reports/waivers or run various tools :Spyglass, 0-in, DC-Compiler, Prime time, synthesis, simulation etc Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is a company of inventors that unlocked 5G, ushering in an age of rapid acceleration in connectivity and new possibilities. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform its potential into world-changing technologies and products. Qualcomm GPU is an industry-leading solution which is driving the benchmarks in mobile computing industry and the future of mobile AR/VR. Selected candidates will be part of the GPU HW team which is passionate about developing and delivering the best GPU Cores for all Qualcomm Snapdragon SOC products. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. GPU Functional Verification Engineer In the role of GPU Functional Verification Engineer, your project responsibilities will include the following, Develop deep understanding of 3-D Graphics hardware pipeline, feature sets, data paths, block functionalities & interfaces Strategize, brainstorm, and propose a DV environment, develop test bench, own test plan, debug all RTL artefacts, and achieve all signoff matrices Engage with EDA vendors, explore new and innovative DV methodologies to push the limits of sign off quality Collaborate with worldwide architecture, design, and systems teams to achieve all project goals Currently, we are looking for candidates who can match one or more of the profiles listed below, Strong knowledge of UVM based System Verilog TB Knowledge of GPU pipeline design is a plus, not mandatory Proficiency with formal tools "“ working knowledge of Property based FV is a plus, not mandatory Strong communication skills (both written and verbal) Most importantly, ability to learn, improve and deliver The pre-Si verification team in Bangalore is currently heavily involved in the following UVM/SV based constrained random test bench for functional verification Subsystem level TB for complete GPU workload analysis and compliance Emulation platforms to analyze performance and pipeline bottlenecks Formal tools "“ both for reduced time to bug & property based FV sign-off Power Aware & Gate level simulations to deliver a high-quality GPU implementation Perl/Python scripts for automation in managing regressions, optimize run time, manage database and bug GPU Functional DV ( Clock/Power) Verification Engineer In this role of Graphics Verification Engineer, you will be verifying the Clock and power management module with design features for low power. The responsibilities will majorly include: Understanding of GPU power and clock domains with power-up/down sequences Own end to end DV tasks from coding Test bench and test cases, write assertions, debugging simulations and achieving all coverage goals Develop test plan to verify sequences and design components for Clock and power management modules. Explore innovative DV methodologies (formal and simulation ) to continuously push the quality and efficiency of test benches Successful candidate will be required to collaborate with worldwide design, silicon and architecture teams to achieve all project goals. Hence, we are looking for candidates with strong communication skills. Understanding of GPU power and clock domains with power-up/down sequences Strong System Verilog/UVM based verification skills & experience with assertion & coverage-based verification methodology Experience in formal / static verification methodologies will be a plus Basic understanding of low power design techniques Good understanding of design components such as clock gates, level shifters, isolation cells and state retention cells. Experience with Synopsys NLP (native Low Power) tool. Experience with scripting languages such as Perl, Python is a plus

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Digital Verification Engineer for IPs, ASICs and Chipsets used in Qualcomm Snapdragon power solutions. Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create job s, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in. Digital Verification Engineer for for Mixed-Signals IPs, ASICs and Chipsets used in Qualcomm Snapdragon power solutions. IPs include telemetry ADCs, 100W+ charging (Quick Charge 5.0), 5G power (mmW, envelope tracking, high performance low noise oscillators etc") and high efficiency power management (DC-DC charge pumps, bucks and linear regulators). * Work includes partnering with international teams in all stages of development from system definition to high-volume (100M+) OEM launches. * Digital Verification aspects include all stages of the verification process from test planning, UVM-compliant test-bench architecture, constrained-random stimulus creation, score-boarding and coverage closure. * Work includes verification of digital and mixed-signals IPs and exposure to analog behavioral models is a plus. * Work includes debugging of complex embedded systems including SOCs, firmware, embedded sequencers. * Position includes IP or chip DV ownership including task planning and project risk mitigation. * Work in a dynamic team environment with aggressive schedule towards metrics-based high quality target. Preferred Qualifications Strong troubleshooting skills across embedded systems disciplines (digital RTL, Firmware, analog behavioral models) Strong communication and organizational skills Strong process-oriented mindset. Expert-level System Verilog Programming Advanced UVM/SV (Universal Verification Methodology using System Verilog) Python or Perl scripting Minimum Qualifications Bachelor's degree in Science, Engineering, or related field. 8+ years ASIC design, verification, or related work experience Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Looking for 4+ yrs of design verification Engineers with below skills Developed verification methodology and test plan for new design Good knowledge on the verification flows, SV and UVM Perform RTL code coverage and functional coverage, formal analysis Be responsible for defining the verification strategy and plan for the development Develop coverage-driven verification test plans Knowledge on assertion development and coverage improvement Write test specifications (plans) and create directed and random test cases Good debugging skill

Role & responsibilities : * Pre-Silicon Support: Simulate, analyze, and debug pre-silicon full-chip designs to ensure functional accuracy. * Test Case Development: Develop stimulus and test cases to increase the functional coverage for DRAM, SRAM, and other emerging memory technologies. Core Requirements: * Strong Communication Skills: Ability to collaborate effectively within a team. * Leadership: Guide new team members and engineers, sharing your knowledge and experience. * Analytical Expertise: Deep understanding of complex CMOS and/or gate-level circuit designs. * Proficiency in SPICE and/or Verilog simulations. Preferred candidate profile : Required Skills: * Experience with SystemVerilog, PLI coding, and UVM Test Benches. * Expertise in DRAM, SRAM, or other memory-related fields. * Familiarity with AMS verification and co-simulation is a plus. * Experience with Ethernet, SATA, Perl Scripts, and Debugging is helpful. * Knowledge of full-chip DDR, gate-level simulation, and SPICE simulation is optional but advantageous. Perks and benefits : Flexible Working Hours , Transport facility, Competitive Salary

Role & osition: Sr vefication engg 1 position exp - 7-10 yrs SV & UVM method, verilog simulation, exp in memory (Not theoretical, BUT practical)- really great SRAM DRAM - v good prf - Masters degree, graduate also ok. gate level simulation, AMS skills good to have Cadence, VCS - normal verification Mentor experience required, not team lead TMSC not required preference will be given to SPICE simulation No protocols required– should be a able to write a test plan, test bench Knowledge on Pearl can be alternative to PLI coding responsibilities Preferred candidate profile Perks and benefits