150 Sv Jobs - Page 2

Experience : 5+years Location : Bangalore Job Description: You will be part of the team verifying IPs and SoCs leading to first Si success. Manage and lead a team of Verification engineers IP verification is coverage driven using latest industry standard methodologies and HVLs. Work involves defining verification strategy, writing test plans, developing efficient test benches and test cases. Code coverage, Functional coverage and assertions are desired. ARM based SoC verification experience is an added advantage. Proficiency in one scripting language like Perl, C++, Python, Unix Make, Unix Shell Scripts etc. is a great plus. Multiple positions with emphasis on AMS and Power aware verificatio...

As a Formal verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Develop the verification environment and test bench and creating testcases. Develop skills in IBM Formal verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5 – 10 years of relevant industry experience Proven experience in Formal/Functional Verification - Demonstrated execution experience of verification of logic blocks verification. Knowledge of formal me...

The job is based in Bangalore/Hyderabad and requires a notice period of 15 to 30 Days with a minimum experience of 4 Years. As a candidate, your key responsibilities will include developing test plans, coding and bringing up asm, c++ tests, coding and maintaining UVM test bench components, debugging regression fails, and working with protocols such as DDR, PCIE, USB, MIPI, and PCIE. The ideal candidate should have experience working on Processor based Systems or Sub-system level verification. It is preferred that you have hands-on experience with assembly, UVM, SV, C++, and have worked on developing complex test bench/models in UVM, Verilog, and System Verilog. Additionally, you should have ...

Understand the design specification , TB architecture Learn in IBM Fusion and Trek verification languages and tools, apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise 8+ years of work experience in IP, Sub-system & SOC level - Exp in creating multiple UVM/SV based env from scratch, Strong in Block Level verification Exp in developing checkers, Scoreboards, Monitors, Test plan development, Code c...

Job Description: SOC Verification engineers with 3+ years of experience Knowledge of ARM architecture, CPU fundamentals & Cache coherency Experience with C/C++, assembly, and scripting languages. Familiarity with low-power design and verification Develop CDV UVM verification environments at system level Verify CPU connectivity to IP blocks Develop SoC test plans and test cases and track metrics including code and functional covera Job Requirement: Bachelors or Masters in EE/CS or related field 3+ years of SoC in ASIC/FPGA verification experience Proficiency in SV and UVM Experience with simulation, emulation, and formal verification Strong debugging and problem-solving skills Experience (yea...

Roles and Responsibilities Design verification using UVM methodology for IP/SOC level verification. Create testbenches from scratch, including drivers, monitors, and scoreboard components. Develop VIPs (Virtual Interface Platform) for functional verification of IP blocks. Collaborate with cross-functional teams to identify requirements and develop test plans. Participate in peer review process to ensure high-quality deliverables.

We make real what matters. This is your role. Questa verification IPs help design teams find more bugs in less time than conventional simulation techniques. You will specify, implement, test and enhance these verification components for a wide range of end user applications. You will work on technologies involving SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger. You will get along with TMEs and Field AEs or directly with customers to deploy or resolve customer issues. We dont need superheroes, just super minds. You're an Electronics Engineer (B.Tech/ M.Tech) or related field from a reputed institute You've got phenomenal knowledge of verification engineering and have ...

Role & responsibilities : Lead /manage SoC/IP/Package-level verification projects, ensuring quality and timely delivery. Architect and drive UVM-based verification environments and methodologies. Define verification strategies, develop test plans, and ensure signoff criteria (functional & code coverage, power analysis, GLS) are met. Collaborate cross-functionally with design, DFT, physical design, and software teams to ensure robust verification coverage and silicon success. Manage team deliverables, mentor junior engineers, and provide technical guidance. Interface with stakeholders for project scoping, scheduling, and resource allocation. Drive silicon debug, pattern verification, and post...

As a Developer, you will be responsible for operation and production support of the SV system. You will design, code, test and document in an agile team,Your tasks are to execute, monitor & report daily routines and to manage and fix error tickets.

To work in AMS Verification domain with relevant experience in mixed signal SOCs or subsystems/IPs. Leading a project for AMS requirements is a value add. Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS) Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus Functional knowledge of analog and mixed signal building blocks, ...

Job Description We are looking for an experienced Design Verification Engineer to join our team and contribute to the verification of complex SoC/ASIC designs. The ideal candidate will have strong expertise in verification methodologies, testbench development, and debugging. Key Responsibilities: Develop and implement verification plans, environments, and testbenches using SystemVerilog/UVM. Write and execute test cases for functional, regression, and coverage-driven verification. Perform debugging and root cause analysis for design and verification issues. Collaborate with RTL design, architecture, and validation teams to ensure quality deliverables. Analyze functional coverage metrics and ...

At 7Rays Semiconductors, we specialize in providing comprehensive VLSI design solutions to assist our clients in achieving excellence in execution. Our team of experts is highly skilled in various areas including architecture, RTL design, verification, validation, physical design, implementation, and post-silicon validation. We utilize the latest technologies and methodologies to deliver top-notch solutions tailored to meet our clients" specific needs. As a Design Verification Engineer specialized in protocols such as PCIe, CXL, and UCIE, you will be responsible for: - Demonstrating expertise in interconnect protocols such as PCIe, CXL, and UCIE. - Having a solid understanding of AXI/ACE/CHI...

We are seeking a Director of Engineering (Design Verification) to oversee and expand our DV practice. With over 15 years of experience in SoC/ASIC verification, exceptional technical expertise, demonstrated leadership abilities, and the talent to motivate high-performing teams, you will play a pivotal role in our organization. Responsibilities include leading end-to-end SoC/ASIC Design Verification programs, establishing DV methodologies, flows, and best practices (UVM, SV, C-based), delivering technical leadership and practical problem-solving, managing and guiding top-performing engineering teams, collaborating with cross-functional teams for project success, driving customer engagement, e...

As an experienced Design Verification professional with over 8 years of experience, you will be responsible for working with a large Semicon Services Organization with revenue exceeding 400 million USD. The ideal candidate will be located in Pune or Bangalore and possess a strong background in SystemVerilog (SV) and Universal Verification Methodology (UVM) based verification. In this role, expertise in memory controller or cache verification will be crucial. Additionally, the ability to effectively debug complex issues is a must-have skill for this position. If you are interested in this exciting opportunity, please contact Uday at Mulya Technologies via email at muday_bhaskar@yahoo.com. Joi...

Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus. Job Description In your new role you will: Candidate should have working experience with AMS Verification on multiple SOCs or sub-systems. One should have proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools. Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. Candidate should be familiar with the concepts of behavioral m...

Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected. Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus. Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment. In your new role you will: Behavioral modeling: Verilog, Wreal or SV-RNM -Full AMS Verification for SoC or IPs -Full Test plan preparation as per the dynamics of product specifications - Full Dealing challenges with AMS methodologies of Cadence: irun/xrun or Synopsys: XA-VCS o...

You are a skilled SOC Verification engineer with over 3 years of experience in the field. Your expertise includes a strong knowledge of ARM architecture, CPU fundamentals, and Cache coherency. You are proficient in programming languages such as C/C++, assembly, and scripting languages. Additionally, you have a good understanding of low-power design and verification methodologies. In this role, you will be responsible for developing CDV UVM verification environments at the system level. You will verify CPU connectivity to IP blocks and develop SoC test plans and test cases. Tracking metrics, including code and functional coverage, will be an essential part of your responsibilities. To qualify...

HCL Technologies is a next-generation global technology company that helps enterprises reimagine their businesses for the digital age. With a strong foundation built on four decades of innovation, a world-renowned management philosophy, and a relentless focus on customer relationships, we pride ourselves on our culture of invention and risk-taking. HCL is committed to diversity, social responsibility, sustainability, and education initiatives, exemplified by our worldwide network of R&D facilities and co-innovation labs. With over 187,000+ Ideapreneurs across 50 countries, we deliver holistic services across industry verticals to leading enterprises, including 250 of the Fortune 500 and 650 ...

Strong on Digital Design, SV, UVM. Hands-on experience in any of the DV protocols like PCIe, USB 3.0, DDR 3/4/5, AMBA, Ethernet (10G/100G), SATA, and MIPI (CSI/DSI), UFS, CXL Also Hiring PD, RTL, DFT Apply& Share resume to mansoor@hisoltech.com

Description As a Design Verification Manager, you will contribute to exploring innovative hardware designs to enhance our devices You will define verification methodology and implement test plans for advanced functional blocks while collaborating with cross-functional teams to develop world-class hardware devices You will participate in the bringup of such blocks on Simulation and Emulation platforms, Role You will work closely with multi-disciplinary groups including Architecture, RTL Design, PD, Validation, Software and Product Design to architect and implement verification environments for complex functional block that enable development of world-class hardware devices In this role, you w...

As a Staff Engineer - Design Verification at Micron Technology, you will be part of a highly innovative and motivated design team working on cutting-edge memory technologies to develop advanced DRAM and Emerging memory products. Your role will involve verifying high density memory chips with complex circuit capabilities, ultra-high-speed designs, and next-generation DDR/LPDDR technologies. You will collaborate with various design and verification teams globally to ensure the successful completion of design projects. Your responsibilities will include: - Taking ownership of verification and conducting end-to-end analysis of complex block-level custom designs for DDR4, LPDDR4, DDR5, and LPDDR5...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: About The Role Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in. You will be joining a successful engineering team whose deliveries can be found in billions of mobile, compute and IoT products worldwide. Based out of Qualcomm's Bangal...

Must Have: SV/UVM, Test Bench Development , Any Protocols Must be able to own and drive the verification of a block / subsystem or a SOC. Must have extensive experience in verification Share resume to mansoor@hisoltech.com

You will work in the AMS Verification domain, requiring relevant experience in mixed signal SOCs or subsystems/IPs. Leading a project for AMS requirements is considered a value add. Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools is essential. You should have knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles. Analog circuit basics understanding is necessary, and previous analog design experience would be a plus. You should be familiar with the concepts of behavioral modeling, including digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from a mixed signal persp...

Position: Design Verification Engineer Experience: 48 Years We are looking for a skilled Design Verification Engineer with hands-on experience in MIPI protocols and Display IP. For any queries or further details, feel free to reach me at karthik.adasu@Proxilera.com Responsibilities: Experience in MIPI protocol verification (e.g., MIPI DSI, CSI). Strong hands-on experience in Display IP verification and validation. Ability to develop and execute verification plans targeting display and MIPI components. Perform RTL, gate-level, low-power simulations; ensure ISO 26262 compliance. Build SystemVerilog/UVM testbenches tailored to MIPI and Display IPs. Perform simulation and debug activities for MI...