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4.0 - 12.0 years
0 Lacs
karnataka
On-site
Role Overview: You have 12+ years of experience in Digital ASIC/Processor Design with strong fundamentals in core areas such as Microarchitecture, Computer Arithmetic, Circuit Design, and Process Technology. Your communication skills are excellent, enabling you to collaborate effectively with design teams globally. Key Responsibilities: - Lead, train, and mentor a team of junior engineers for a large modem design project in advanced process nodes - Collaborate with RTL, DFT, and PD leads to take a project from Post-RTL to Netlist release, focusing on area, timing, power, and testability - Write timing constraints, conduct synthesis, formal verification, CLP, Primetime, PTPX, and CECO tasks -...
Posted 3 months ago
4.0 - 12.0 years
0 Lacs
karnataka
On-site
As an STA CAD methodology lead at Qualcomm India Private Limited, you will be responsible for leading the deployment of new features and methodologies related to Static Timing Analysis (STA) and Engineering Change Order (ECO) domain. Your role will involve covering various aspects such as STA flow/methodology development, continuous efficiency improvement, and providing flow development/support for ECO convergence using tools like PrimeTime, Tempus, Tweaker, and PrimeClosure. You will face challenges in ensuring timing convergence at both block and top levels on cutting-edge technology for high-performance designs to guarantee successful design tapeouts on time with high quality. Key Respons...
Posted 3 months ago
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