8 Subsystem Jobs

Job Description: You will be responsible for performing ASIC/IP/Sub-System/SoC level design verification for high-speed interfaces, ensuring functional correctness across PCIE and other protocols under PVT conditions. Your role will involve developing and executing test plans using SystemVerilog and UVM, as well as collaborating with cross-functional teams for design bring-up, debug, and coverage closure. Key Responsibilities: - Perform ASIC/IP/Sub-System/SoC level design verification for high-speed interfaces - Ensure functional correctness across PCIE and other protocols under PVT conditions - Develop and execute test plans using SystemVerilog and UVM - Collaborate with cross-functional te...

Summary: Own end-to-end RTL design for complex SoC or large subsystem blocks, from micro-architecture through tapeout and silicon bring-up. Responsibilities: Define micro-architecture from specs; write high-quality synthesizable SystemVerilog/Verilog RTL for SoC-level or large subsystems. Own design bring-up, block/subsystem integration, and close on timing, power, and area with synthesis and PnR teams. Drive design reviews, close bugs, and support silicon validation and post-silicon debug. Collaborate with DV to define test plans, assertions, and coverage goals; support emulation/FPGA only as a secondary validation aid (not counted toward the 8 years). Must-have qualifications: 8+ years of ...

Good Knowledge of Linux & QNX device drivers as well as peripheral subsystems. Strong in C programming skills. Working experience in Android AOSP/Linux based infotainment and build environments Development experience in Display, Touch, Audio subsystem drivers (Serializer-Deserializer, Platform specific frameworks, GMSL/LVDS FPD Link, DSI, Touch Firmware, Audio calibration and TDM /PCM/DSP configurations, I2S, A2B). Experience on DSI, DP port configurations across various SoC platforms like Qualcomm, Samsung, MediaTek. Display bridge chip bring-up/configuration experience. DRM, Surface flinger, Openwfd, screen related understanding to debug issues. TFT panel display timing configuration and d...

Quality Manager in Railway Project - 10 to 18 Years at Pune. Position - Quality Manager in Railway Project Experience - 10 to 18 Years Location - Pune Note Looking candidates only from rail domain. Job Description: Minimum 10 years of experience in Quality Management within Electrical or Infrastructure projects. Metro, Railway experience. Solid work experience in mega projects in the field of QM. Practical knowledge of ISO standards 9001, 14001, and 45001 is highly appreciated. Proven track records and work experience in quality management Leading site quality for large and complex electromechanical work. Providing leadership and guidance to the quality teams of the subsystems. Define and im...

Production within engineering product development processes required Strong experience in Door’s tool required Experience with Functional Safety (ISO26262), ASPICE 3.0 Strong experience in IBM RTC & requirement tasks break down allocation preferred. Required Candidate profile At least 5 years of engineering requirements engineering experience with complex subsystemsincluding multiple engineering disciplines required (Mechanical, Electrical & Electronics, Controls

Job Title: Emulation Engineer Location: Bangalore Experience: 3+ Years Notice Period: Immediate Joiners Preferred Industry: Semiconductors / VLSI / EDA Employment Type: Full Time, Permanent Job Description: We are looking for a highly motivated and skilled Emulation Engineer to join our SoC/Sub-System Pre-Silicon Verification team. The ideal candidate will have hands-on experience with Protium , Palladium , and other leading emulation/prototyping platforms. You will be responsible for enabling accelerated verification using Synthesizable BFMs and VIPs, supporting early software bring-up, and collaborating across cross-functional teams. Key Responsibilities: Develop and deploy Accelerated Ver...

Develop/customize solutions in HCL Commerce v9+. Implement/manage RESTful APIs with Commerce REST framework. Utilize CI/CD tools and understand containerization in HCL Commerce v9. Develop with Spring Boot.Enhance member, payment,and order subsystems

Hiring Now ASIC Design Verification Experts | Automotive Chip Projects Location: Bangalore, Pune, Noida, Chennai Experience: 3 to 20+ Years | Notice Period: Immediate to 45 Days Send Resume to: prabhu.p@acldigital.com JD 1: VIP Development – Technical Lead / Manager 10–20+ years in UVM-based VIP Development & Integration Strong expertise in PCIe, SerDes, MIPI CSI/DSI, Ethernet, SATA Experience in IP & Chip-Level Verification for automotive SoCs Strong in SystemVerilog , Assertions , and Protocol Checkers Ability to lead verification strategy and mentor IC team members Excellent debugging, ownership, and communication skills IC + Team Leadership responsibility in a global ODC setup JD 2: Proc...