926 Sta Jobs - Page 9

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Overview Experienced STA/Timing Engineer with 3-10 Years of hands-on experience on timing sign off/convergence for complex SOCs. Ability to start immediately on timing analysis/sign-off with PD/Methodology teams across multiple sites and different technology nodes. : STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs. Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus. Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. Evaluate multiple timing methodologies/tools on different designs and technology nodes. Work on automation scripts within STA/PD tools for methodology development. Good Technical writing and Communication skills. Willing to work in cross-collaborative environment. Experience in design automation using TCL/Perl/Python. Familiar with digital flow design implementation RTL to GDS ICC, Innovous , PT/Tempus Familiar with process technology enablementCircuit simulations using Hspice/FineSim, Monte Carlo. Education B.Tech or MTech/MS in Electrical/Electronics/Microelectronics/VLSI. Preferred Qualification/Skills Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling. Hands-on experience with STA tools - Prime-time, Tempus Have experience working on timing convergence at Chip-level and Hard-Macro level. In-depth knowledge crosstalk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling, Knowledge of ASIC back-end design flows, methods, and tools (ICC2, Innovus) Knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation. Proficient is scripting languages – TCL, Perl, Python Basic knowledge of device physics

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm GPU team is actively seeking candidates for several physical design engineering positions. Graphics HW team in Bangalore is part of a worldwide team responsible for developing and delivering GPU solutions which are setting the benchmark in mobile computing industry.Team is involved in Architecture, Design, Verification, implementation and Productization of GPU IP COREs that go into Qualcomm Snapdragon SOC Products used in Smartphone, Compute, Automotive, AR/VR and other low power devices. Qualcomm has strong portfolio of GPU COREs and engineers get an opportunity to work with world class engineering team that leads industry through innovation and disciplined execution. As a Graphics physical design engineer, you will innovate, develop, and implement GPU cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power GPU COREs. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction and performance goals. Additional responsibilities in this role involves good understanding of functional, test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, debugging and fixing violations and formal verification. The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and delivers complex Physical Design solutions from netlist and timing constraints to the final product. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelor's/Master’s degree in Electrical/Electronic Engineering from reputed institution 8+ years of experience in Physical Design/Implementation Minimum Physical Implementation activities for high performance GPU Core, which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Physical Design Planning. Experience3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Physical Verification. Experience1-3 Years.

Drawing, SOR & Specification study along with supplier for giving timely inputs to minimize design changes. (DFM / DFA ) FTG & APQP and tracking at all the stages of product development. Support suppliers for the development of parts and ensure QCD targets. Proactively identifying & resolving problems and maintaining quality standards First time right Development of parts. PPAP submission to QA for closure and handing over for regular supplies. Poka yoke implementation Good knowledge of quality tools, FTG and processes to ensure seamless flow of information on quality concerns to seniors. Meet all material requirement time targets by continuous interaction with supplier and internal agencies. Verifying compliance as per predetermined and approved audit schedule. Monitoring & Tracking Part development as per MPDS guidelines Releasing schedules & Procuring parts based on project gateways to ensure smooth vehicle builds. Capacity Assessment of supplier and risk identification.

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Design for Testability (DFT) Good to have skills : NAMinimum 3 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your day will involve overseeing the application development process, coordinating with team members, and ensuring project milestones are met. Roles & Responsibilities:Bachelors degree in computer science, Electronics Engineering or related fields and 6+ years of related professional experience.Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at-least couple of DesignsCore DFT skills considered crucial for this position should include some of the following Scan compression and insertion, Memory BIST, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate-level verification, silicon debugUnderstanding of DFT Flows and Methodologies and Experience with Cadence/Mentor/Synopsys Tool set (Genus,Modus,NCSim / DC,Tessent,Spyglass/Tmax)Experience coding in Verilog RTL, and scripting language like TCL, and/or PerlProficient in Unix/Linux environmentsStrong fundamentals in Digital Circuit Design and Logic Design are required. Professional & Technical Skills: - Must To Have Skills: Proficiency in Design for Testability (DFT)- Strong understanding of software development methodologies- Experience in leading and managing software development projects- Knowledge of technologies and tools used in software development- Excellent communication and interpersonal skills Additional Information:- The candidate should have a minimum of 5 years of experience in Design for Testability (DFT)- This position is based at our Chennai office- A 15 years full time education is required Qualification 15 years full time education

3 to 5 years of experience in static timing analysis, constraints and other physical implementation aspects. Solid understanding industry standard tools PT, Tempus, And should be familliar to PNR tools like Innovus/FC Solid grip on STA fixing aspects to solve extreme critical timing and clock path analysis Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs and manual ECOs as well. Experience in deep submicron process technology nodes is strongly preferred - Below 10nm Knowledge of high performance and low power interface timing is added benefit. Strong fundamentals on basic VLSI design concepts, synchronous design timing checks, understanding of constraints Good experience with in Unix, TCL, PT-TCL, Tempus-TCL scripting Familiarity with Python background is added bonus

Kindly share your resume on sv14@svmanagement.com Key Responsibilities: Carry out supplier Initial assessment audit in case of new suppliers to ensure manufacturing/ Technology capability to meet product and process requirement. Supplier Quality Improvement audits for existing suppliers to ensure effective implementation of Quality Management System & process controls. Support suppliers for advanced product quality planning (APQP) Perform on-site supplier visits for process and product audits, root cause analysis and verification of corrective actions of supplier quality issues Collate and evaluate supplier quality data, manufacturing process to identify process improvement and value enhancement opportunities within the supply chain. Promote the use of preferred techniques for continuous improvement such as Lean manufacturing, Six-Sigma, Poka-Yoke (Error Proofing), Measurement System Analysis, SPC and Process Failure Mode and Effects Analysis (PFMEA). Report on Key Performance Indicators (KPIs) in order to adhere to process and prevent occurrence of any non-conformity relating to product, process or system Qualifications and Skills: Degree in Mechanical, Automobile and Production with 8-10 years experience in automotive OEM, Tier I auto components manufacturing companies. Experience of working in Quality Assurance Department, preferably in Supplier Quality & New Product Development. Additional preference to certified VDA 6.3 & IATF 16949 lead auditor. Strong knowledge of Advanced Product Quality Planning (APQP), Production Part Approval Process (PPAP), Failure Mode and Effect Analysis (FMEA). Knowledge of Quality Management System, IATF16949 and VDA 6.3, Measurement techniques, metrology and equipments. Understanding and interpretation of engineering drawings Knowledge of manufacturing processes such as Casting, Forging, machining & Heat Treatment.

For sub system in high performance microprocessor design, you are responsible for Timing constraintmodelling given timing specification, generation, validation. Design timing data generation, validation, timing data analysis. Driving timing convergence across different timing corners , by working with logic, circuit, integration designers. Ensuring quality and efficiency in timing convergence. Engaging in automation of flow, data analysis. Required education Bachelor's Degree Required technical and professional expertise 5+ years of industry experience Hands on experience in static timing analysis, modelling timing constraints, setting up timing environment and timing runs, data analysis, timing fix implementation, timing ECO generation. Knowledgeable in physical design flow, logic. Experience with timing fixes (slack, electrical, noise). Preferred technical and professional experience Require programming skills with any language PYTHON, PERL , and/or TCL .

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Required technical and professional expertise . 6 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Lead Capacity meeting and work with Program team, Purchasing, STA & regional constraints management team to ensure appropriate supplier s capacity data is available in GCP & MCPV system. - Responsible to Analyze the Capacity data & manufacturing constraints at suppliers to ensure the suppliers readiness for new launches / existing programs Vehicle & Powertrain - Resolve any constraint to support vehicle & powertrain program Candidate Profile 3-5 years hands-on experience in Supply Chain/Production Planning/ Capacity Planning Strong communication skills to interact with Global cross functional team(written and oral) Strong analytical skills Good multi-tasking ability Demonstrates interpersonal skills and problem-solving skills Ability to manage pressure situations Education: Qualified candidates must have a B. Tech or BE degree in Business, Technology, or equivalent degree Capacity Planning: To work with CPAT (Capacity Planning Activity Team) to determine volume (APW) and mix for new / existing vehicles & power train. Participate in weekly CPAT meetings and contribute on any volume and supplier capacity data requirements Provide input to GBS team on the volume and mix for GCP (Global capacity planning) & MCPV (Manufacturing Capacity Planning Volume) to generate part level volume data and perform supplier studies along with Purchasing To work with Bill of Material team / IT team to ensure part level volume generated through GCP/MCPV for the vehicle line is in line with requirement Work with Purchasing and suppliers to identify the part level shortfall thorough the GCP/MCPV study process and then identify the tooling and lead time required to resolve the shortfall identified Represent India in Capacity Planning forums to support capacity studies for globally shared powertrain commodities. Lead Short term capacity studies to meet the monthly operating plan by working with Purchase/STA/ MP&L teams/Suppliers Validate & analyze the quality of capacity data in GCP & MCPV system. Interact with Capacity planning, Purchasing, STA & constraints team to clarify all technical queries of suppliers regarding part release, part volume & sourcing. Support monthly programming process in SPCPS system Supplier capacity update in SPCPS Derive supply base supportability for different variants of Vehicle &Power train and support Capacity Planning team accordingly Identify issues with wrong part volume generation by understanding Vehicle Line processing, Bill of Material generation and other related concerns to maintain accurate Volume in system Create desk procedures and checklists with necessary process flow charts and obtain approval from business team. Continuous process improvement to enhance value for the organization. Constraints Management: To develop the current status including demand and supply for any constraints reported. Develop constraint commodity summary report and provide supporting data to drive decision, utilizing standard Constraint Management formats and methodologies. Work with SCM/ Purchase / STA /Suppliers to identify Interim support plan to meet the current build requirement. Work with Sales and Scheduler to find opportunities in managing the demand in case the Interim plan does not meet the current build requirement. Develop Management report on the constraints and drive for decision on the next steps based on evaluation of SCM on premium freight / purchasing / STA on any incremental support and Sales in terms of any volume adjustment. Represent in Global Constraints forums (GCAC) to support GCAC allocation for shared constraints. Communicate and implement the allocation within India. Provide Operation Planning team / Scheduler with availability shared constraints commodities prior to final approval of Production plan. Develop allocations plans for the constraints commodities and coordinate with the SCM team and cross functional constraints team to ensure parts are ordered and delivered per ag

SUMMARY Part-Time Weekend Job Join Leading Food & Beverage Industry Team in Chennai Job Role: Weekend Supporting Staff Company: Food & Beverage Industry Location: Chennai Work Locations: T. Nagar Nungambakkam Vadapalani Velachery Thuraipakkam Marina Mall (Egattur) Shift Timing: 11:00 AM 8:00 PM Work Days: Saturday and Sunday Estimated Monthly Earnings: 5,000 7,000 Work 9 hours and earn extra income every weekend Key Responsibilities: Support kitchen and floor staff Serve starters, beverages, and non-vegetarian items (including chicken) Maintain cleanliness in service and dining areas Ensure smooth dining operations Requirements: No prior experience required (orientation provided) Must be energetic, disciplined, and customer-friendly Comfortable handling non-vegetarian food Age 18+ and available on both days What We Offer: Quick payouts Flexible part-time weekend shifts Work experience with a leading restaurant brand Apply Now Turn your weekends into an earning opportunity!

Lead Capacity meeting and work with Program team, Purchasing, STA & regional constraints management team to ensure appropriate supplier s capacity data is available in GCP & MCPV system. - Responsible to Analyze the Capacity data & manufacturing constraints at suppliers to ensure the suppliers readiness for new launches / existing programs - Vehicle & Powertrain - Resolve any constraint to support vehicle & powertrain program Candidate Profile 3-5 years hands-on experience in Supply Chain/Production Planning/ Capacity Planning Strong communication skills to interact with Global cross functional team(written and oral) Strong analytical skills Good multi-tasking ability Demonstrates interpersonal skills and problem-solving skills Ability to manage pressure situations Education: Qualified candidates must have a B.Tech or BE degree in Business, Technology, or equivalent degree Capacity Planning: To work with CPAT (Capacity Planning Activity Team) to determine volume (APW) and mix for new / existing vehicles & power train. Participate in weekly CPAT meetings and contribute on any volume and supplier capacity data requirements Provide input to GBS team on the volume and mix for GCP (Global capacity planning) & MCPV (Manufacturing Capacity Planning Volume) to generate part level volume data and perform supplier studies along with Purchasing To work with Bill of Material team / IT team to ensure part level volume generated through GCP/MCPV for the vehicle line is in line with requirement Work with Purchasing and suppliers to identify the part level shortfall thorough the GCP/MCPV study process and then identify the tooling and lead time required to resolve the shortfall identified Represent India in Capacity Planning forums to support capacity studies for globally shared powertrain commodities. Lead Short term capacity studies to meet the monthly operating plan by working with Purchase/STA/ MP&L teams/Suppliers Validate & analyze the quality of capacity data in GCP & MCPV system. Interact with Capacity planning, Purchasing, STA & constraints team to clarify all technical queries of suppliers regarding part release, part volume & sourcing. Support monthly programming process in SPCPS system - Supplier capacity update in SPCPS Derive supply base supportability for different variants of Vehicle &Power train and support Capacity Planning team accordingly Identify issues with wrong part volume generation by understanding Vehicle Line processing, Bill of Material generation and other related concerns to maintain accurate Volume in system Create desk procedures and checklists with necessary process flow charts and obtain approval from business team. Continuous process improvement to enhance value for the organization. Constraints Management: To develop the current status including demand and supply for any constraints reported. Develop constraint commodity summary report and provide supporting data to drive decision, utilizing standard Constraint Management formats and methodologies. Work with SCM/ Purchase / STA /Suppliers to identify Interim support plan to meet the current build requirement. Work with Sales and Scheduler to find opportunities in managing the demand in case the Interim plan does not meet the current build requirement. Develop Management report on the constraints and drive for decision on the next steps based on evaluation of SCM on premium freight / purchasing / STA on any incremental support and Sales in terms of any volume adjustment. Represent in Global Constraints forums (GCAC) to support GCAC allocation for shared constraints. Communicate and implement the allocation within India. Provide Operation Planning team / Scheduler with availability shared constraints commodities prior to final approval of Production plan. Develop allocations plans for the constraints commodities and coordinate with the SCM team and cross functional constraints team to ensure parts are ordered and delivered per ag

SUMMARY Part-Time Weekend Job Join Leading Food & Beverage Industry Team in Bangalore Job Role: Weekend Supporting Staff Company: Food & Beverage Industry Location: Bangalore Work Locations: Lulu Mall (Rajajinagar) Phoenix Marketcity (Whitefield) Shift Timing: 12:00 PM 5:00 PM Work Days: Saturday and Sunday Estimated Monthly Earnings: 3,000 3,500 Work 4 5 hours and earn extra income every weekend Key Responsibilities: Support kitchen and floor staff Serve starters, beverages, and non-vegetarian items (including chicken) Maintain cleanliness in service and dining areas Ensure smooth dining operations Requirements: No prior experience required (orientation provided) Must be energetic, disciplined, and customer-friendly Comfortable handling non-vegetarian food Age 18+ and available on both days What We Offer: Quick payouts Flexible part-time weekend work Opportunity to work with a popular restaurant brand Apply Now Turn your weekends into an earning opportunity!

Responsible for all aspects of physical design and implementation.Responsibilities include chip floor plan, power/clock distribution, chip assembly and P&R, timing closure, power and noise analysis and back-end verification across multiple projects. High level of expertise in complete physical implementation tool chain; Good working knowledge and experience of netlist to GDSII flows Hands-on technical experience with deep sub-micron technology ASIC design, STA and physical implementation;Expertise in Synthesis, Static Timing Analysis and Timing Closure of High Performance Hard-Macros and/or Full Chip Physical DesignsShould be independent, self-driven and a strong team player. Thorough understanding and knowledge of the entire Back end flow Netlist to gdsii Must be familiar with Industry standard tools like ICC/Encounter/Talus/Olympus Should have expertise in Timing analysis and closure Should have Tcl and perl scripting skills Should have work experience in the latest technology nodes like 16nm/14nm/10nm Should be familiar with low-power design and their impact on Back end flow (power switches/Level shifter/Isolation cell/retention cells/Back biasing/Forward biasing)

Responsible for all aspects of physical design and implementation.Responsibilities include chip floor plan, power/clock distribution, chip assembly and P&R, timing closure, power and noise analysis and back-end verification across multiple projects. High level of expertise in complete physical implementation tool chain; Good working knowledge and experience of netlist to GDSII flows Hands-on technical experience with deep sub-micron technology ASIC design, STA and physical implementation;Expertise in Synthesis, Static Timing Analysis and Timing Closure of High Performance Hard-Macros and/or Full Chip Physical DesignsShould be independent, self-driven and a strong team player. Thorough understanding and knowledge of the entire Back end flow Netlist to gdsii Must be familiar with Industry standard tools like ICC/Encounter/Talus/Olympus Should have expertise in Timing analysis and closure Should have Tcl and perl scripting skills Should have work experience in the latest technology nodes like 16nm/14nm/10nm Should be familiar with low-power design and their impact on Back end flow (power switches/Level shifter/Isolation cell/retention cells/Back biasing/Forward biasing)

Responsible for all aspects of physical design and implementation.Responsibilities include chip floor plan, power/clock distribution, chip assembly and P&R, timing closure, power and noise analysis and back-end verification across multiple projects. High level of expertise in complete physical implementation tool chain; Good working knowledge and experience of netlist to GDSII flows Hands-on technical experience with deep sub-micron technology ASIC design, STA and physical implementation;Expertise in Synthesis, Static Timing Analysis and Timing Closure of High Performance Hard-Macros and/or Full Chip Physical DesignsShould be independent, self-driven and a strong team player. Thorough understanding and knowledge of the entire Back end flow Netlist to gdsii Must be familiar with Industry standard tools like ICC/Encounter/Talus/Olympus Should have expertise in Timing analysis and closure Should have Tcl and perl scripting skills Should have work experience in the latest technology nodes like 16nm/14nm/10nm Should be familiar with low-power design and their impact on Back end flow (power switches/Level shifter/Isolation cell/retention cells/Back biasing/Forward biasing)

90/130/150nm and higher node with PMIC layout experience. Performs layout and takes corrective actions in such a way that the final result meets all requirements as stated in the Design document, section layout, including all remarks from review, the customer and back annotation. Performs layout in such a way that the final result meets all general layout guidelines and matches 1-to-1 with parameter devices and hierarchy used in simulations. Create floorplan Performs DRC and takes corrective actions if needed until DRC is error free Performs LVS and takes corrective actions if needed until result is successful Performs layout in such a way that final result meets the foundry layout rules. Provides extracted netlist for back annotation to DE as specified in the Design document, section layout. Translates sub block schematics to sub block layouts, taking care of the same hierarchical build-up and respecting the guidelines of the Block review document, section layout. Adds extra useful information to the Block review document, section layout.

Exp with Spark, Flask, SQL, Python, Cloud platform, Machine Learning, Deep Learning & Engineering aspects of ML model deployment, data analysis, mathematics/probability, & statistical analysis. Mail us- info@a1selectors.com

Job Title: Verification Engineer Key Responsibilities: Perform standard cell characterization (up to 40% of the time). Conduct static timing analysis (STA) (approximately 60% of the time). Characterize basic standard (STD) cells. Write ARC (Analysis and Results Capture) for STD cell characterization using PrimeLib and Silicon Smart . Conduct .lib QA checks to ensure model quality and accuracy. Understand circuits at both block-level and full-chip level . Execute STA for DRAM at block level, top level, and cell level. Write constraints and analyze STA reports for setup, hold, and timing violations. Report violations to the design team and take ownership of closure . Support parasitic modeling and assist in design validation , reticle experiments , and tape-out revisions . Perform verification using industry-standard simulators , involving modeling and simulation. Collaborate across teams to contribute to standardization and cross-functional success . Drive innovation for future memory generations within a dynamic and challenging work environment. Required Experience: 3 to 5 years of relevant experience in digital/analog verification and STA.

floor planning, bump planning, routing, power grid design, clock design, optimization for high-speed digital circuits high-speed digital layouts, DDR and other high-speed interfaces EDA tools for chip-level physical verification (DRC, LVS, ERC) Accessible workspace Food allowance Health insurance Annual bonus Provident fund

Key Responsibilities: Floor planning: Develop and optimize floorplans for ASIC designs, ensuring optimal placement of cores, macros, and I/O cells while considering performance and manufacturability. Place & Route (P&R): Perform place-and-route tasks, optimizing for timing, power, and area, ensuring congestion-free routing and maximizing PPA (Performance, Power, Area). Static Timing Analysis (STA): Carry out static timing analysis to identify violations and work on techniques for timing closure such as resizing, retiming, or re-optimization. Power Analysis & Optimization: Perform power analysis, targeting low-power designs using techniques such as clock gating, power gating, and low-power state optimization. Signal Integrity & Noise Analysis: Perform signal integrity analysis to avoid noise and crosstalk in the design. Design Rule Check (DRC) and Layout vs. Schematic (LVS): Run DRC and LVS checks to ensure the layout adheres to manufacturing rules and matches the schematic. RC Extraction: Perform parasitic extraction and analyze RC effects to ensure the design functions at the required operating frequencies. Verification: Participate in the final sign-off processes for physical design and support tape-out efforts, ensuring all design specifications are met. Collaboration: Work closely with design, verification, and CAD teams to troubleshoot and resolve any design-related issues. Documentation: Maintain clear documentation throughout the physical design flow for ease of understanding and for future reference. Qualifications: Education: Bachelors/Masters degree in Electronics/Electrical Engineering or a relevant degree. Experience: Minimum 3-14 years of experience in ASIC physical design. Proficiency in place and route (P&R), static timing analysis (STA), power analysis , and DRC/LVS checks. Experience with tools like Cadence Innovus , Synopsys IC Compiler , or Mentor Graphics for physical design. Knowledge of advanced process nodes (e.g., 7nm, 5nm) is a plus. Technical Skills: Proficiency in digital design concepts and semiconductor process flows. Strong knowledge of timing optimization techniques and power optimization strategies. Familiarity with parasitic extraction and signal integrity analysis. Ability to script in languages like Tcl , Python , or Perl to automate tasks. Preferred Skills: Experience with 3D IC design or FinFET technologies. Familiarity with full-chip tape-out procedures. Exposure to machine learning techniques in physical design optimization will be added advantage.

Key Responsibilities : Lead and manage RTL design activities for complex ASICs, ensuring high performance and low power consumption. Integrating RTL components into System-on-Chip (SoC) designs Integrating RTL components into System-on-Chip (SoC) designs Architect and implement RTL for digital circuits (such as processors, communication systems, or custom IP cores). Mentor and guide junior RTL engineers in best practices for design, coding standards, and optimization techniques. Develop and refine RTL code in Verilog/SystemVerilog for ASIC development. Collaborate with cross-functional teams (Verification, Physical Design, and Software) to ensure successful integration of the ASIC design. Perform RTL design reviews, debugging, and optimization to meet design targets such as area, speed, and power. Work on creating micro-architectural specifications and ensure the design meets project requirements. Ensure designs are implemented with proper synchronization, timing constraints, and low power techniques. Participate in top-level design, integrating IP blocks, ensuring design consistency across subsystems. Drive the design flow from architecture and specifications through to implementation. Prepare and maintain technical documentation for designs and related processes. CDC, LINT and Integration expertise is expected. Required Skills & Experience : Bachelor's, Master's, or PhD in Electrical Engineering or related fields. 3-12 years of experience in RTL design for ASICs, with at least 3 years in a team lead role. Expertise in RTL design using Verilog or System Verilog. Solid understanding of digital design principles, including timing analysis, state machines, and pipelining. In-depth knowledge of ASIC design flow, from RTL to tape-out. Experience with EDA tools for synthesis, simulation, and timing analysis (e.g., Synopsys, Cadence). Strong debugging and problem-solving skills. Good knowledge on scripting (Python, Perl and Shell scripting) Knowledge of power, performance, and area (PPA) optimization techniques. Experience with designing for low-power, high-speed circuits is highly desirable. Excellent communication skills and the ability to work in a team environment.

JOB DESCRIPTION A Job Speci cation 1 Company Name : Muthoot Fincorp Ltd. 2 Position/Designation : Senior Business Development Executive 3 Grade : JMM3 4 Department : BRANCH 5 Sub Department (if any) : N/A-Sub Department 6 Employment Type : Probationer B Job Role 1 Job Role : Branch Business Development 2 Reporting to - Designation and Grade : Branch Manager 3 No Of Reportees : 4 Main Tasks : Increase the Branch business 1.Field Marketing. 2.Generate Leads on daily basis. 3.Conversation of leads 4.Sales Calls 5.Generate new customer Business for GL and Third party. 5 Areas of Responsibility : 1.Achieve Monthly Sales Target. 2.Cross selling and up selling of third Party and group products to Gold Loan customers. 3.Adhere to lending norms and maintain integrity in customer transactions. 4.Support the branch in interest collection. 5.Conduct branch catchment development activities and generate customer leads and converting them to NCA. 6 Special Requirements (if any) : Graduate/Post Graduate. 7 Compensation Band : Based on Market Standards/Internal norms 8 Entitlements : As per policy 9 Stake Holders : MFL Sta , Group Company Sta , Customers 10 Assets Required : As per policy 11 Career Progression : Null Personal Speci cation 12 Educational Quali cation : Graduate (minimum) 13 Technical Certi cation : Basic Computer Knowledge, esp.MS O ce applications mandatory. MS Excel preferable. 14 Skill Sets : Sales orientation. Good communication skills. Outgoing and confident. Problem solving capabilities, Result oriented, Proactive, Creative, and innovative, Perseverance, Flexibility, Pleasant and Smart, Integrity, Effective, Team player. And Empathetic 15 Communication Skills : Conversant in local language and English 16 Total Field Sales Experience : 1Year(s)0 Month(s) 17 Behavioral Competencies : NA 18 Other Requirements (if any) : Null 19 Remarks : C Approvals 24 Prepared by (Name/Designation/ Date) : 25 Approved by (Name/Designation/ Date) : Need to be a Team player. Ability to work stretch/Multi-Tasking Environment. Effective Communication ability at different levels. Adaptable to complex Work environments live Organizational values.

JOB DESCRIPTION A Job Speci cation 1 Company Name : Muthoot Fincorp Ltd. 2 Position/Designation : Senior Business Development Executive 3 Grade : JMM3 4 Department : BRANCH 5 Sub Department (if any) : N/A-Sub Department 6 Employment Type : Probationer B Job Role 1 Job Role : Branch Business Development 2 Reporting to - Designation and Grade : Branch Manager 3 No Of Reportees : 4 Main Tasks : Increase the Branch business 1.Field Marketing. 2.Generate Leads on daily basis. 3.Conversation of leads 4.Sales Calls 5.Generate new customer Business for GL and Third party. 5 Areas of Responsibility : 1.Achieve Monthly Sales Target. 2.Cross selling and up selling of third Party and group products to Gold Loan customers. 3.Adhere to lending norms and maintain integrity in customer transactions. 4.Support the branch in interest collection. 5.Conduct branch catchment development activities and generate customer leads and converting them to NCA. 6 Special Requirements (if any) : Graduate/Post Graduate. 7 Compensation Band : Based on Market Standards/Internal norms 8 Entitlements : As per policy 9 Stake Holders : MFL Sta , Group Company Sta , Customers 10 Assets Required : As per policy 11 Career Progression : Null Personal Speci cation 12 Educational Quali cation : Graduate (minimum) 13 Technical Certi cation : Basic Computer Knowledge, esp.MS O ce applications mandatory. MS Excel preferable. 14 Skill Sets : Sales orientation. Good communication skills. Outgoing and confident. Problem solving capabilities, Result oriented, Proactive, Creative, and innovative, Perseverance, Flexibility, Pleasant and Smart, Integrity, Effective, Team player. And Empathetic 15 Communication Skills : Conversant in local language and English 16 Total Field Sales Experience : 1Year(s)0 Month(s) 17 Behavioral Competencies : NA 18 Other Requirements (if any) : Null 19 Remarks : C Approvals 24 Prepared by (Name/Designation/ Date) : 25 Approved by (Name/Designation/ Date) : Need to be a Team player. Ability to work stretch/Multi-Tasking Environment. Effective Communication ability at different levels. Adaptable to complex Work environments live Organizational values.