Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains"“ LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux "“ Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills 3+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. General Summary PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains"“ LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux "“ Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 12+ years Hardware Engineering experience or related work experience. 12+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm Chennai is looking for a VLSI engineers who is passionate in to work with cross-functional engineering teams . In this position, the engineer will be involved in all stages of the design and development cycles Strong knowledge of digital design and SOC architecture. Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C Experience in HDL such as Verilog Knowledge of ARM/DSP CPU architecture, High Speed Peripherals like USB2/3, PCIE or Audio/Multimedia Familiarity with Power-aware Verification, GLS, Test vector generation is a plus Exposure to Version managers like Clearcase/perforce Scripting language like Perl, Tcl or Python Analytical and Debugging skills 2-4 yrs experience Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Bachelors / Masters degree in electrical or electronics engineering with 2 - 4 yrs of experience is preferred

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: We are seeking a highly skilled and experienced SoC Management IP Design lead to join our team. This position requires overseeing the development of all SoC Management IPs primarily Debug and Timer IPs, which includes creating micro-architecture specifications, IP design and verification. The ideal candidate will have a strong background in IP development and SoC Management Architecture, with a focus on both technical leadership and management responsibilities. IP Design, Verification and Delivery SoC and Platform Architecture Development Key Responsibilities Leadership and Management Lead and manage the development of SoC management IPs, Primarily Debug and Timer IPs IP Design, Verification and Delivery Provide technical leadership and guidance to the IP development team. Oversee the entire lifecycle of IP development, from concept to implementation and validation. Collaborate with cross-functional teams to ensure seamless integration of IPs into SoC designs. Technical Expertise Experience of RTL design for complex SoC development using Verilog and/or SystemVerilog Experience with Arm-based designs and/or Arm System Architectures Drive the architecture and design of SoC Management IPs. Ensure the IPs meet performance, power, and area requirements. Stay updated with the latest industry trends and technologies in SoC management and IP development. Troubleshoot and resolve complex technical issues related to IPs. Collaboration and Communication Work closely with other engineering teams, including SoC design, verification, and validation teams. Foster a collaborative and innovative work environment. Communicate effectively with team members, management, and external partners. Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience in SoC Management IP development, including debug and timers IPs. Strong technical leadership and management skills. Excellent understanding of SoC architecture and design principles. Strong problem-solving and analytical skills. Excellent communication and interpersonal skills. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 6+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 5+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Job description: Role requirement is for CAD engineer with 3-4 years work experience in the Signoff CAD Team at Qualcomm BDC. The team is a part of a Global CAD team that builds reference flows for PD implementation and supports the design teams in Project execution across geographies. The specific role is a requirement in this CAD team for position that has the following responsibilities Be involved in building software solutions for cross domain requirements Contribute in building and supporting Signoff and Extraction Reference flows Explore and build differentiating scripts/tools to improve productivity and improve timing signoff convergence with high quality LPE outputs Build scripts and flows that help debug capabilities in adjacent signoff domains (Physical verification/ STA) Skill Set required Strong experience in SW coding skills (Python, C++, Perl, TCL) is a must Demonstrated experience in building end to end software solutions Must have experience in Parasitic Extraction tools and VLSI flow Background in FC/Innovus tool usage

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3 to 5 years of experience in static timing analysis, constraints and other physical implementation aspects. Solid understanding industry standard tools PT, Tempus, And should be familliar to PNR tools like Innovus/FC Solid grip on STA fixing aspects to solve extreme critical timing and clock path analysis Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs and manual ECOs as well. Experience in deep submicron process technology nodes is strongly preferred - Below 10nm Knowledge of high performance and low power interface timing is added benefit. Strong fundamentals on basic VLSI design concepts, synchronous design timing checks, understanding of constraints Good experience with in Unix, TCL, PT-TCL, Tempus-TCL scripting Familiarity with Python background is added bonus

About the Opportunity Job TypePermanent Application Deadline13 May 2025 About The Role Title Test Analyst Department FIL India Technology - WPFH - Testing Location Gurgaon, India Level Technology Quality Assurance - 1 Were proud to have been helping our clients build better financial futures for over 50 years. How have we achieved this? By working together - and supporting each other - all over the world. So, join our technology engineering testing team and feel like youre part of something bigger. About team Technology and engineering testing team is evolving at a fast pace to cater to strategic technology drivers and to meet end customer experience demands. Here experienced technologists drive this space with dedicated energy, passion, and inspiration and delivery quality solution with faster pace. About role The role would focus on services, functional, test automation and cover for key capability gaps and give this a shape of a programme with clear prioritized / agreed scope and agenda. The role will leverage/guide the existing automation experts to get this prioritized backlog delivered on time. The key outcomes shall be (but not limited to) to create services and functional automation suite keeping DevOps principle of speed and quality in mind. The role shall be responsible for managing the day-to-day activities of the team along with tech guidelines, best practices and reference implementations for the existing and new automation assignments. About Candidate Experience and Qualifications 2-4 years B.E./B.Tech/M.C.A Essential Skills Expert level experience on Core Java and J2EE development. Experience of test automation framework design for service layer/API. (SoapUI knowledge) Expert in at least one functional test automation tool like Selenium, Test Complete etc. Relevant experience in Application development tools and frameworks like maven, Jenkins, Git Experience with Oracle (preferably Oracle 10G), queries Experience of using source code management tools, e.g., GitHub Candidate needs to have rich experience around engineering skills, CI/CD, and build/ deployment automation tools. Good soft skills Skill Matrix Sample Skill/Experience STA Must Have Should Have Could Have Technical Skills Java (Core) Yes Java/JavaScripts Yes Cloud Computing (AWS) Yes Implementing Selenium/Testing frameworks on Cloud/Test Pyramid Understanding Implementation Yes API knowledge, Automation Framework Development Yes Selenium Yes Test Complete Yes SoapUI, Groovy Yes CI-CD Implementation -Maven, Git, Jenkins Yes Database Testing Yes Soft Skills Excellent Communication Yes Innovative/Good Analytical/Motivated Yes Feel rewarded For starters, well offer you a comprehensive benefits package. Well value your wellbeing and support your development. And well be as flexible as we can about where and when you work finding a balance that works for all of us. Its all part of our commitment to making you feel motivated by the work you do and happy to be part of our team. For more about our work, our approach to dynamic working and how you could build your future here, visit careers.fidelityinternational.com. For more about our work, our approach to dynamic working and how you could build your future here, visit careers.fidelityinternational.com.

Defining and developing ASIC RTL design and verification at both chip and block levels. Writing and modifying test cases, checkers, and scoreboards in a system Verilog-based test environment. Collaborating with cross-functional teams to ensure seamless integration of analog and digital components. Conducting AMS verification, particularly for high-speed SerDes designs supporting multi-protocols. Utilizing Synopsys analog mixed-signal design tools for efficient design and verification processes. Programming and scripting using TCL, Perl, and Python to automate and streamline workflows. The Impact You Will Have: Enhancing the performance and reliability of our high-performance silicon chips. Contributing to the development of innovative technologies that drive the Era of Pervasive Intelligence. Improving the efficiency and effectiveness of our design and verification processes. Ensuring the seamless integration of analog and digital components in our products. Supporting the creation of cutting-edge solutions for self-driving cars, learning machines, and more. Driving continuous technological innovation within Synopsys and the broader industry. What You ll Need: Looking for 2+yrs experience with BTech / MTech in VLSI / Electronics/ Microelectronics Knowledge or hands-on expertise/analysis of Analog and digital CMOS circuit designs Knowledge on electrical circuit networks and analysis Knowledge or hands-on Verilog/System Verilog languages and supported methodologies like VMM, UVM Must be able write/modify testcases, checkers, scoreboards in a system Verilog based test environment AMS verification experience in high speed Serdes designs supporting multi-protocols is an advantage. Experience with the Synopsys Analog mixed-signal design tool set is an advantage. Modelling languages Verilog-a/ams can be an advantage Programming/scripting know-how e. g. tcl, perl, python Experience with Linux Good communication skills, ability to take ownership Self-organized to ensure that project timescales are met Who You Are: Excellent communicator with strong interpersonal skills. Proactive and able to take ownership of projects. Self-organized and capable of managing time effectively. Collaborative team player who thrives in a dynamic environment. Detail-oriented and committed to delivering high-quality results.

You are a highly motivated and experienced professional with a deep understanding of VLSI design and a strong background in high-speed protocols such as Ethernet, DDR, and PCIe Your technical expertise is complemented by your hands-on experience in simulation, synthesis, and static timing analysis (STA) With a Bachelors and/or Masters Degree in Electrical Engineering or a related field, you bring at least 10 years of design, verification, or application engineering experience to the table You thrive in a UNIX environment and are proficient with ASIC/SoC tape-out processes from concept to full production Your ability to work across teams, coupled with strong analytical, reasoning, and problem-solving skills, sets you apart as a creative and results-oriented professional Excellent verbal and written communication skills in English are essential, as you will be collaborating with customers and teams worldwide Occasional travel is something you are comfortable with, and you are ready to take on the challenge of integrating leading Interface IP into next-generation products What You ll Be Doing: Acting as a trusted advisor for our Interface IP customers, providing guidance throughout their SoC flow. Supporting customers in resolving technical challenges and performing integration reviews at key milestones. Assisting with silicon/system bring-up and debugging critical issues. Collaborating with internal teams to deliver tailored solutions to customers. Staying updated with the latest industry specifications and applications in various hot market segments. Participating in occasional travel to support customer engagements and silicon bring-up activities. The Impact You Will Have: Enhancing the usability and adoption of Synopsys Interface IP products by providing expert technical support. Facilitating successful integration of IP into customer designs, contributing to their product development timelines. Improving customer satisfaction by resolving technical issues efficiently and effectively. Driving innovation by working with cutting-edge technologies and industry specifications. Strengthening Synopsys market position through successful customer engagements and support. Contributing to the development of next-generation products that leverage high-speed protocols and advanced IP. What You ll Need: Bachelors and/or Masters Degree in Electrical Engineering or similar with a focus on VLSI design. At least 10 years of design, verification, or application engineering experience. Proficiency in RTL coding using Verilog/VHDL. Experience with high-speed protocols such as Ethernet, DDR, and PCIe. Hands-on experience with simulation, synthesis, and static timing analysis (STA). Familiarity with UNIX environments and ASIC/SoC tape-out processes. Knowledge of CDC, RDC, Lint, DFT, STA, and LEC is a plus. Who You Are: Creative and results-oriented, capable of managing multiple tasks concurrently. Strong verbal and written communication skills in English. Ability to work collaboratively across teams to deliver solutions to customers. Strong analytical, reasoning, and problem-solving skills. Willingness to travel occasionally to support customer engagements.

Working with Synopsys customers to understand their needs and define verification scope and activities. Understanding the complexity and requirements of verification and proposing resource requirements to complete the activities. Leading a team of engineers to perform various pre-silicon verification activities on IPs/Subsystems. Anticipating problems and risks and working towards a resolution and risk mitigation plan. Assisting and mentoring the team in day-to-day activities and growing the capabilities of the verification team for future assignments. Reviewing various results and reports to provide continuous feedback to the team and improve the quality of deliverables. Reporting status to management and providing suggestions to resolve any issues that may impact execution. Collaborating with architects, designers, and pre and post-silicon verification teams to accomplish your tasks. Adhering to quality standards and good test and verification practices. Ramping up on new Verification tools and methodologies using Synopsys Products to enable customers. Working with other Synopsys teams including BU AEs and Sales to develop, broaden, and deploy Tool and IP solutions. The Impact You Will Have: Driving the success of customer projects by ensuring robust and thorough verification of SoC designs. Enhancing Synopsys reputation as a leader in verification through high-quality deliverables and customer satisfaction. Mentoring and growing the verification team, building a strong foundation for future projects. Identifying and mitigating risks early, ensuring smooth project execution and delivery. Improving verification methodologies and practices, contributing to the overall efficiency and effectiveness of the team. Collaborating with cross-functional teams to achieve seamless integration and execution of verification activities. Providing valuable feedback and insights that drive continuous improvement in verification processes and tools. What You ll Need: B.E/B. Tech/M.E/M. Tech in electronics with a minimum of 12+ years experience in SoC/IP/Subsystems verification domain. Technical expertise in various aspects of pre-silicon Verification (UVM, Coverage Analysis, Verification plan creation, debugging, etc). Good knowledge of various protocols (PCIe, Ethernet, USB, DDR, etc) and/or processor/interconnect/debug architecture. Hands-on experience with verification tools such as VCS, waveform analyzers, and third-party VIP integration (such as Synopsys VIPs). Ability to lead a team to perform verification on complex SoC/IP/Subsystems. Experience with planning and managing verification activities for SoC/Subsystems/IPs. Strong understanding of design concepts, ASIC flows, and stakeholders. Good communication skills. Who You Are: A proactive and detail-oriented leader who can guide and mentor a team. An excellent communicator who can collaborate effectively with cross-functional teams. A problem-solver who can anticipate challenges and develop effective mitigation strategies. A continuous learner who stays updated with the latest verification tools and methodologies. A team player who values quality and strives for excellence in deliverables

• Physical Design of blocks & handle Complex block implementation. • Floorplan optimization for area, Power & Timing. • Block-level PnR & close Design to meet Timing, area & Power constraints. • Implement ECOs to fix timing, noise & EM-IR violations. Required Candidate profile * Exp in RTL Synthesis for PnR using small geometry FinFET. * Strong in Physical Design incl. physically aware Synthesis, floor-planning, PnR * Logic equivalency RTL2Synthesis & Synthesis2APR netlist.

Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Emulation Good to have skills : NA Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, you will analyze, design, code, and test multiple components of application code across one or more clients. You will perform maintenance, enhancements, and/or development work in a dynamic environment, contributing to the success of the projects. Roles & Responsibilities: Expected to be an SME, collaborate, and manage the team to perform. Responsible for team decisions. Engage with multiple teams and contribute on key decisions. Provide solutions to problems for their immediate team and across multiple teams. Lead and mentor junior team members. Conduct code reviews to ensure code quality and adherence to coding standards. Professional & Technical Skills: Must To Have Skills: Proficiency in Emulation platform like Palladium/Zebu/Veloce/HAPS. Strong understanding of SOC Architecture Experience with debugging using any Emulation Palladium/Zebu/Veloce/HAPS platform. Hands-on experience with ARM (A/M) architecture. Knowledge of C language. Additional Information: The candidate should have a minimum of 5 years of experience in Emulation. This position is based at our Bengaluru office. A 15 years full-time education is required. Qualification 15 years full time education

Full chip or block-level synthesis using tools Constraints development, STA & timing closure, low power checks Work closely with PD team for floorplan, placement & timing reviews Good understanding of front-end implementation flows ,concepts

ROLE & RESPONSIBILITIES Engineer will be responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal integrity, Power grid analysis atc in ASIC PNR Flow Engineer will be responsible for executing the block level place and route assignments from Netlist through GDS flow Should be able to do full chip implementation of complex SoCs (RTL-to-GDSII), but it is not must. To close STA timing across all corners and modes for blocks and should be able to generate ECO independently. Will be responsible to Work with design teams for closing CTS, IO timing, DFT timing. Responsible for digital design automation, flow-automation and regression across RTL-to-GDSII. To ensure successful delivery of his block(s) to customers ESSENTIAL SKILLS & EXPERIENCE Minimum Experience required is 5 Years in Physical Design Strong fundamentals on Physical design including Floorplan, power grid analysis, placement, cts, routing, DRC-LVS closure, timing closure, antenna fixing, signal integrity on 65nm, 45nm, 28nm, 16nm geometry. Sound expertise in Tcl, Perl, Shell scripting. Technically sound & good team player Hands-on experience with Place and Route tools (Synopsys - ICC, Cadence – Innovus / Encounter) is a must. Experience on latest technology (28nm,16nm,7 nm) EDUCATION BACKGROUND B.E./ B.S./ B.Tech/ M.S./ M.Tech in VLSI/Electronics/Electrical/Computer/Instrumentation Engineering.

Walk-in-Interview Role & responsibilities: About the Role: Engineer Digital Design The position involves development of digital subsystems in a complex SoC with multi-core, multi-threaded processor subsystems, AI accelerators, interconnects, memory architecture with multi-level caches, multiple clocks and resets, high-speed interfaces and peripherals. The chosen candidate would do the architecture, microarchitecture and design and verification and would be responsible for the entire design flow and sign-off, including synthesis, LEC, Formality and STA, and be able to deliver reusable and robust digital IP. Prior Experience Hands-on experience or Academic Projects involving one or more high end digital designs like multi-core, multi-threaded processor subsystems, high speed interfaces (PCIe, Ethernet, LPDDR, HBM), high performance digital accelerators (Tensor Processing units, Convolution engines, other high performance digital accelerators) Exposure to design sign-off flows including Lint, CDC, Synthesis, LEC, STA, and Timing Closure . Familiarity with low-power design methodologies. Skills Required Technical Expertise: Verilog, SystemVerilog, and scripting languages (Python, Perl, Tcl, Shell). Processor Knowledge: RISC-V, ARM architectures, and protocols like AXI, APB, AHB. Design Tools: Experience with ASIC and FPGA design flows, DFT (Scan, MBIST, BScan), and UVM methodology. Analytical Skills: Strong problem-solving abilities with attention to detail. Low Power Design: Techniques like clock gating, power gating, and dynamic voltage/frequency scaling. Communication: Good teamwork and collaboration skills, eager to learn and grow Walk-in Interview Details Dates: April 5, 6, 12, 13, 19, 20 Time Slots: Please select your preferred timeslot for the interview via the link provided: https://calendly.com/careers-ceremorphic Location: Ceremorphic Technologies Interview Process: The walk-in interview will include a 1-hour written test . Eligibility Criteria : Education: B.Tech/BE or M.Tech/MS in Electronics or Electrical Engineering Aggregate: 70% or above Experience: 0-2yrs What to Bring : An updated resume A valid govt ID for verification We look forward to meeting you and discussing how you can contribute to our dynamic and innovative team at Ceremorphic Technologies . Regards Ceremorphic Hiring Team

Skills : Functional specifications of the IPs, subsystems and SOC, Reviewing and Revising, System Verilog, UVM, Performing RTL simulations using Synopsys and Cadence simulators, Performing UPF

This role is based in Bangalore. But youll also get to visit other locations in India and globe, so youll need to go where this job takes you. In return, youll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. We are passionate about innovations that mean real progress, and we are curious about technologies that still need to be developed. Design, develop, modify, and implement software programming for products (both internal and external) with focus on surpassing customer expectations. Ability to understand sophisticated products, solutions, and problems. Creates, documents, and performs software designs which may involve significant re-architecture of important systems, defining and coordinating implementation of wide-reaching impacts. Acts as technical lead of major projects within one area of a product. Frequently collaborates with customers regarding future upgrades and products. Influences the technical direction for at least one area of a product. Promotes innovation through the ability to introduce new technology/knowledge into at least one area of a product and to our people. Provides high-level technical expertise, including performing in-depth and complex software systems programming and analysis. Provide problem resolution and technical leadership for the group. Possesses broad knowledge of internal operating systems, applications implications and customer areas. Technical Lead in guiding junior engineers. Works without supervision on highly complex projects with complete latitude for independent judgment and technical expertise. Extensive knowledge of the field. What Part will you play? This is your role : Working on 7nm and 5nm designs with various customers for deployment of Aprisa place and route tools. Responsible to develop flow and methodology for doing placement, CTS, and routing. Expertise in solving customer's problems for critical designs to achieve desired performance, area and power targets & provide training and technical support to customers using Aprisa tools We don't need Defenders, just super minds! Typically requires proven 8-12 years of experience in Physical Design with mainstream P&R tools Relevant experience in Physical Design (floorplan, placement, CTS, and routing) and timing closure of complex blocks and/or Full Chip designs. Good to have hands-on experience with commercial place & route tools like Synopsys-lCC2, Cadence-lnnovus or Aprisa Tape out experience of 2 or more projects is required. Good understanding of timing, power, and area trade-offs. Ability to pick up new flows, learn on the job and influence QOR is a must. Experience delivering designs with multiple voltage islands and top-level floor planning & chip-assembly is a plus. Strong verbal and written communication skills; good presentation skills. Good problem solving and debugging skills Academics: BE/B.Tech in Electronics and Communication (E&C) or Electrical or Telecom Engineering. ME/M.Tech in VLSI or Microelectronics is a plus.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and detail-oriented engineer with a deep understanding of Static Timing Analysis (STA). You thrive in a collaborative environment, working closely with cross-functional teams to solve complex technical challenges. Your expertise in Synopsys PrimeTime and related technologies allows you to diagnose issues and propose innovative solutions that enhance product quality. You are self-motivated, with a proven track record of executing comprehensive validation plans and delivering high-quality results. Your exceptional debugging skills and proficiency in scripting languages like Perl, Tcl, and Python enable you to streamline processes and improve efficiency. You are committed to continuous learning and staying up-to-date with the latest industry trends and advancements. What You'll Be Doing: Execute and lead product validation of Synopsys's PrimeTime tool by understanding requirements specifications and functional specifications, customer use cases. Perform in-depth customer incoming root cause analysis to understand the product weak areas and hot spots and execute proactive testing to reduce customer incoming thereby improving product quality. Collaborate with cross-functional teams such as R&D, Product Engineering, Field and Customers, recommend improvements in implementation and validation. Use product expertise to provide technical recommendations, identify, diagnose and troubleshoot issues and propose solutions to ensure quality and readiness of the product/solution for customer deployment. Demonstrate a high level of attention to detail and accuracy in all tasks. Perform risk assessments and develop mitigation strategies to address potential product validation issues. Analyze validation data to identify trends, discrepancies and areas for improvement. Prepare detailed validation reports to present to multi-functional teams and management. The Impact You Will Have: Ensure the high quality and reliability of Synopsys's PrimeTime tool, contributing to its success in the market. Enhance customer satisfaction by proactively identifying and addressing potential issues before they impact users. Collaborate with R&D and Product Engineering teams to drive continuous improvements in product design and functionality. Provide valuable insights and recommendations that influence the development and validation of future product releases. Contribute to the overall success of Synopsys by ensuring that our tools meet the highest standards of performance and reliability. Support the deployment of cutting-edge technologies in high-performance designs, shaping the future of the semiconductor industry. What Youll Need: Deep domain knowledge in Static Timing Analysis. BSEE or equivalent and a minimum of 2 years of related experience or MSEE or equivalent and a minimum of 1 year of related experience. Experience with Synopsys PrimeTime, timing analysis, ECO flows, Extraction, power, SDC constraints, advanced OCV concepts, derates, PBA timing, distributes, hierarchical STA flows, and/or physical design closure. Exceptional debugging skills. Proficient in software and scripting skills (Perl, Tcl, Python). Detail-oriented with a focus on maintaining high standards of product quality. Who You Are: Collaborative team player with excellent communication skills. Analytical thinker with a problem-solving mindset. Proactive and self-motivated individual. Adaptable and flexible in a fast-paced environment. Strong attention to detail and accuracy. The Team You’ll Be A Part Of: You'll be part of the product validation team for Synopsys's PrimeTime tool. This team works closely with R&D and product engineering to solve complex technical challenges in areas of static timing analysis. The team is dedicated to ensuring the high quality of the tools, enabling customers to accurately validate and deploy these technologies on their high-performance designs. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Responsibilities for this role include: We are working on the next generation RTL-to-GDSII solution. You should be able to completely own and drive the design and development of various pieces of the RTL synthesis technology, logic optimizations and low power synthesis. Experience and Qualifications: 5-8 years of proven experience in software development. B.Tech or M.Tech in CSE/EE/ECE from a reputed engineering college. Good knowledge of C/C++, algorithm and data structures. Good problem solving and analytical skills. Ability to guide and lead others, towards project completion. Desirable: We are looking for an individual with previous experience in RTL synthesis tool development. Knowledge of Verilog, VHDL, and formal verification. Expertise in RTL and gate-level logic, area, timing, and power optimizations. Familiarity with parallel algorithms and job distribution techniques. Proficiency in scripting languages like Python and Tcl. Communication Proficiency in English with strong interpersonal and excellent oral and written communication skills. Ability to collaborate as part of globally distributed team. Also, Self-motivated and able to work independently. We thrive on building a multi-functional team environment, and we look for individuals who are eager to contribute and grow with us!

Hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, programming in Tcl/Tk/Perl, Synopsys/Cadence tools, , STA and timing closure. Required Candidate profile Notice Period: Immediate Joiners EducationBE, B.Tech, ME, M.techLocation Bangalore, Hyderabad, Kochin, Pune

Were proud to have been helping our clients build better financial futures for over 50 years. How have we achieved this? By working together - and supporting each other - all over the world. So, join our technology engineering testing team and feel like youre part of something bigger. About team Technology and engineering testing team is evolving at a fast pace to cater to strategic technology drivers and to meet end customer experience demands. Here experienced technologists drive this space with dedicated energy, passion, and inspiration and delivery quality solution with faster pace. About role The role would focus on services, functional, test automation and cover for key capability gaps and give this a shape of a programme with clear prioritized / agreed scope and agenda. The role will leverage/guide the existing automation experts to get this prioritized backlog delivered on time. The key outcomes shall be (but not limited to) to create services and functional automation suite keeping DevOps principle of speed and quality in mind. The role shall be responsible for managing the day-to-day activities of the team along with tech guidelines, best practices and reference implementations for the existing and new automation assignments. About Candidate Experience and Qualifications 2-4 years B.E./B.Tech/M.C.A Essential Skills Expert level experience on Core Java and J2EE development. Experience of test automation framework design for service layer/API. (SoapUI knowledge) Expert in at least one functional test automation tool like Selenium, Test Complete etc. Relevant experience in Application development tools and frameworks like maven, Jenkins, Git Experience with Oracle (preferably Oracle 10G), queries Experience of using source code management tools, e.g., GitHub Candidate needs to have rich experience around engineering skills, CI/CD, and build/ deployment automation tools. Good soft skills Skill Matrix Sample Skill/Experience STA Must Have Should Have Could Have Technical Skills Java (Core) Yes Java/JavaScripts Yes Cloud Computing (AWS) Yes Implementing Selenium/Testing frameworks on Cloud/Test Pyramid Understanding Implementation Yes API knowledge, Automation Framework Development Yes Selenium Yes Test Complete Yes SoapUI, Groovy Yes CI-CD Implementation -Maven, Git, Jenkins Yes Database Testing Yes Soft Skills Excellent Communication Yes Innovative/Good Analytical/Motivated Yes

As an STA (Static Timing Analysis) Engineer at Nsemi, you ll play a crucial role in ensuring our digital designs meet timing requirements and performance standards. You will be responsible for performing timing analysis, identifying critical paths, and optimizing designs for timing closure. Your expertise in STA tools and methodologies will be essential in delivering high-quality, reliable semiconductor solutions. Join us to contribute to cutting-edge projects and advance your career in a dynamic and innovative environment. Qualification Required: Typically requires minimum of 3+ years of experience. Bachelors / Master Degree in E&E and E&C Strong communication & team work skills Roles And Responsibilities: Timing Constraint Generation: Work with design and architecture teams to define and generate timing constraints that specify the desired timing requirements for the design. STA Setup: Set up and configure STA tools (e.g., Cadence Encounter, Synopsys PrimeTime) for the analysis, including library characterization, delay models, and clock definitions. Timing Analysis: Perform static timing analysis to evaluate setup and hold times, clock-to-q delays, and other timing metrics. Ensure that the design meets timing requirements for various corners and operating conditions (e.g., process, voltage, temperature variations). Clock Domain Crossing (CDC) Analysis: Identify and analyze asynchronous signals crossing between different clock domains to ensure proper synchronization and to avoid metastability issues. Multicycle Paths (MCP) and False Paths: Define and analyze multicycle paths and false paths to accurately capture the designs timing constraints. Timing Closure: Collaborate with RTL and physical design teams to achieve timing closure by optimizing the design or constraints. Perform incremental and formal ECO (Engineering Change Order) analysis to address timing issues. Clock Tree Synthesis (CTS): Work with CTS engineers to ensure that the clock tree meets timing requirements and minimizes clock skew and jitter. Post-Layout STA: Perform post-layout STA to account for parasitic capacitance and resistance effects introduced during the physical design phase. Identify and resolve timing violations and sign-off on the final timing closure. Timing Margins: Analyze timing margins to account for variability and manufacturing process variations, ensuring robust operation. Report Generation: Prepare detailed timing analysis reports, including timing paths, violations, and suggestions for timing optimization. Cross-Functional Collaboration: Collaborate closely with RTL designers, physical designers, DFT (Design for Test) engineers, and verification teams to resolve timing-related issues. Methodology Development: Contribute to the development and improvement of STA methodologies and flows to enhance efficiency and accuracy.

The candidate must have thorough knowledge of DFT basics such as DFT RTL insertion. scan insertion, fault models, ATPG, BIST techniques, and on-chip compression techniques that reduce test time and tester memory. Need to work with product engineering team for Silicon Bring-up and also support post-silicon debug. Interfacing with the design teams to ensure DFT design rules and guidelines are met Interact with PD and Front End Integration team for Scan Insertion Generating high quality manufacturing test patterns for stuck-at, transition fault models and CA model Simulating and verifying the ATPG and LBIST patterns Working with the product engineering teams on the delivery of manufacturing test patterns Developing, enhancing and maintaining scripts as necessary Able to technically guide and mentor junior folks in the team PREFERRED EXPERIENCE: Experience in creating and implementing complex chip-level DFT architecture Proficient in logic design using Verilog Experience in DFT implementation including Scan insertion, ATPG and Simulations Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression Experience in debugging low coverage and DRC fixes Experience of debugging test pattern issues Support the Silicon bringup activities to guarantee highest stability of the test pattern Knowledge of MBIST is a plus. Knowledge of synthesis is a plus Experience with post-silicon debug Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc Any Tessent Scan/ATPG certifications is a plus Excellent presentation and inter-communication skills. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Prior experience as DFT engineer

About The Role Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high-quality integration of the GPU block. As a principal engineer, recognized as a domain expert who influences and drives technical direction across Intel and industry. Develops and mentors other technical leaders, grows the community, acts as a change agent, and role models Intel values. Aligns organizational goals with technical vision, formulates technical strategy to deliver leadership solutions, and demonstrates a track record of relentless execution in bringing products and technologies to market. Qualifications Minimum Qualifications:BS+15 Years of relevant experience in the semiconductor I industry. experience15+ years of experience in/withVerilog and system verilog, synthesizeable RTL Modern design techniques and energy-efficient/low power logic design and power analysis. 10+ years of experience in/withHaving achieved multiple tape-outs reaching production with first pass silicon. Hands on experience with FPGA emulation, silicon bring-up, characterization and debug Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.