929 Sta Jobs - Page 27

is a Gurgaon based Placement Consultancy that specializes in providing Placement Services, Manpower Recruitment, HR Consultancy, Placement Consultancy and Staffing Solutions. We are looking for Our Esteemed Client in Gurgaon Industry HR Recruitment Administration IR Training & Development Operations Qualification Other Bachelor Degree Key Skills HR HR Analyst HR Assistant HR Associate HR Consultant HR Coordinator HR Head HR Incharge HR Generalist

Responsible for Memory Compiler layout development and verification. Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM. Perform layout verification like LVS/ DRC/ Latchup, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Guide junior team-members in their execution of Sub block-level layouts & review their work. Contribute to effective project-management. Effectively communicate with engineering teams in the India & Korea teams to assure the success of the layout project.

Experienced in rtl design using verilog / system Verilog Asic designers with experiences in all aspects of rtl design flow from specification/microarchitecture definition to design and verification, timing analysis, dft and implementation Integration, rtl signoff tools, upf/low power signoff and cdc/rdc, lint Strong domain knowledge of clocking, system modes. Power management, debug, interconnect, safety, security and other architectures

Physical Design Engineer Lead - InSemi Tech Physical Design Engineer Lead Bangalore | 8 Years Key Responsibilities Technologies Below 14nm 10nm,7nm,latest one ..3nm Block level floor planning and IR drop analysis Block level timing closure with sign off STA Proficient in physical Design methodology which include logic synthesis, placement ,clock tree synthesis, routing

Experience in Static Timing Analysis (STA) for ASIC designs Experience in developing timing constraints Experience in timing closure and optimization Proficiency in using scripting languages such as Perl and TCL Familiarity with EDA tools such as PrimeTime and Design Compiler Experience in Physical Design and/or DFT is a plus Bachelor s or Master s degree in Electrical/Electronics/Computer Science Engineering or related field

Minimum qualifications: Bachelor's degree in Computer Science, IT, a related field, or equivalent practical experience 5 years of experience with static timing analysis, synthesis, physical design & automation Experience in physical design tool automation such as synthesis, P&R and sign-off tools Preferred qualifications: Experience in extraction of design parameters, QoR metrics, and analyzing data trends Knowledge of RTL languages (e g , Verilog and SystemVerilog) Knowledge of timing constraints, convergence and sign-off Knowledge of STA, EMIR and PDV sign-off methodologies Understanding of parasitic extraction tools and flow About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products You'll contribute to the innovation behind products loved by millions worldwide Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration Google's mission is to organize the world's information and make it universally accessible and useful Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful We aim to make people's lives better through technology Responsibilities Work with Post-Si teams to improve and debug Vmin and yield related issues Explore specific new custom circuit opportunities for optimized Power, Performance, and Area (PPA) for high-performance, low-power subsystems Work with the testchip teams on latest process nodes to build, validate and characterize custom Intellectual Property (IPs) Schedule and plann for custom IP for product interception Work on early prototyping of subsystems to deliver optimized PPA recipes Google is proud to be an equal opportunity workplace and is an affirmative action employer We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status We also consider qualified applicants regardless of criminal histories, consistent with legal requirements See also Google's EEO Policy and EEO is the Law If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form

In-depth knowledge and hands-on experience on Netlist2GDSII Implementation . Must have hands-on experience on Synopsys/Cadence tools. Should have experience on PD Methodologies and submicron technology of 28nm and lower technology nodes.

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more efficiently. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Position presents an opportunity to join the award winning and market leading Tessent team, India. The focus of the role is advanced design-for-test (DFT) insertion and automatic test pattern generation (ATPG) for semiconductor designs. It will involve understanding and supporting the latest DFT ATPG electronic design automation (EDA) technologies such as Tessent TestKompress and Streaming Scan Network (SSN). Someone in this role will gain a deep understanding of scan design, on-chip clock controls, and IJTAG infrastructure in support of scan testing. They will support the worldwide application engineering team on complex ATPG issues and build testcases for advanced DFT methodologies. This role is based in Noida. But youll also get to visit other locations in India and globe, so youll need to go where this job takes you. In return, youll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. Responsibilities for this role include: Build and deliver in-depth technical presentations, develop training material, white papers, supplied articles, and application notes. Work with customers as well as Siemens stakeholders such as regional application engineers, global support engineers, and marketing. Are you expertized in working through complex technical issues and independently building solutions and new methodologies! Explain complex principles in simple terms to broad audiences. Some travel, domestic and international. Successful deployment of existing and new Tessent DFT products in customer designs by enabling AEs. Working closely with our key customers on deployment challenges. Working with PEs and R&D to ensure new product readiness testcase in form of testcases, documentation and trainings. Architecture reviews of customer designs. Closely working with AEs to gather top issues blocking their engagement's success. Deep learning opportunities for Tessent DFT products including opportunities to present at various conferences worldwide including ITC and Siemens U2U. We dont need hard workers, just superminds! BS degree (or equivalent) in Electrical Engineering, Computer Science or related field is required with 8 - 12 years of experience. Knowledge of design logic design languages, tool usage, design flow steps required. We are looking for someone that has exposure to DFT or SoC design for complex ASICs / SOCs. ATPG, IEEE 1687 IJTAG, boundary scan (BSCAN), hierarchical DFT implementation. Knowledge of a scripting language like TCL. We need someone self-motivated and dedication to improvement with strong problem-solving skills. Excellent organizational skills, written and verbal English language communication skills. Proficiency in LINUX and Windows environments. The role presents many opportunities to build specialized DFT and ATPG knowledge. Publications and other promotions of methodologies is encouraged. A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! Transform the everyday #LI-EDA #LI-HYBRID

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Questa Simulation Product It is a core R&D team working on multiple verticals of Simulation. A very energetic and enthusiastic team of motivated individuals. This role is based in Noida. But youll also get to visit other locations in India and globe, so youll need to go where this job takes you. In return, youll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. We make real what matters! Key Responsibilities : We are looking for a highly motivated software engineer to work in the QuestaSim R&D team of the Siemens EDA Development responsibilities will include core algorithmic advances and software design/architecture. You will collaborate with a senior group of software engineers contributing to final production level quality of new components and algorithms and to build new engines and support existent code. Self-motivation, self-discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success. Are you excited to know more about this Role Job Qualification: An ideal candidate should have skills below: B.Tech or M.Tech in Computer Science & Engineering (CSE), Electrical Engineering (EE), or Electronics & Communication Engineering (ECE) from a reputable engineering institution having 5-7 years of experience. Strong knowledge of C/C++, algorithms, and data structures. Familiarity with compiler concepts and optimizations. Experience with UNIX and/or LINUX platforms is essential. Excellent problem-solving and analytical skills. Self-motivated with the ability to work independently and guide others towards successful project completion. We are not looking for superheroes, just super minds! Having the below skills will be an added advantage: Strong understanding of basic digital electronics concepts. Familiarity with machine learning (ML) and artificial intelligence (AI) algorithms, particularly their implementation in data-driven tasks. Proficiency in hardware description languages such as Verilog, SystemVerilog, and VHDL. Experience with parallel algorithms and job distribution techniques. Exposure to simulation or formal verification methodologies is a plus. A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! Transform the everyday #LI-EDA #LI-Hybrid #DVT

Responsibilities: Promptly attend site problems arriving at customer premises in low voltage motors. Carry out overhauling of motors at customer premises. Maintain excellent relationship with the customers & Authorized Repair Center. Help in generating service business e.g. motor overhauling, AMC, spare parts, complete motor retrofitting, Motor rewinding etc. Analyze site problems & give suitable solutions to customer. In some cases, co-ordinate with HO for offering solution. How do I Qualify Diploma/Degree in Electrical engineering field with excellent knowledge of Low & Medium Voltage Motors. At least 7 Years experience in servicing of Electrical motors. Having knowledge in service business development area. Capable in identifying customer end maintenance process improvement need. Excellent communication & team-work skill. Problem solving attitude.

What do I need to qualify for this job - Graduate / Diploma in Electrical /Electronic engineering with min 5-7 years of experience. - Experience of working in Low Voltage Products manufacturing. - Maintenance of automation setup WEVE GOT QUITE A LOT TO OFFER, HOW ABOUT YOU Were Siemens. A collection of over 379,000 minds building the future, one day at a time in over 200 countries.

As a member of DFT team , you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, Hardware Bring-up and Silicon Debug Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5-9 years experience in DFT on complex designs involving scan insertion, compression, MBIST, ATPG, simulations and IP integration and validation. Proven expertise in analysing and resolving DRCs/TSVs . Hands-on experience in pattern generation for various fault models, pattern retargeting and debugging techniques to address low coverage issues. Hands-on experience with DFT verification, both with and without timing annotations. Well versed with industry standard test techniques and advanced DFT features like SSN, IJTAG, IEEE 1500, Boundary scan , LBIST and STA constraint delivery . Hands on experience on industry standard tools used for DFT features. Proficiency in scripting languages such as TCL, Perl or Python to automate design and testing tasks. Worked with cross functional teams like design, STA & tester teams for ensuring top quality of DFT deliverables and DFT support and hand offs. Excellent analytical and problem-solving skills, with a keen attention to detail. Strong communication and collaboration skills, with the ability to work effectively within cross-functional teams Preferred technical and professional experience Fundamentals in micro controller architecture, embedded firmware, functional verification and RTL design Experience working with ATE engineers for silicon bring up, silicon debug and validation. Experience in processor flow and post silicon validation

Responsible for high performance microprocessor blocks RTL to GDSII implementation Perform block level synthesis, floor-planning, placement and routing. Close the design to meet timing, power budget and area. Implement ECO's to address functional bugs and timing violations. Team player, with good problem solving and communication skills. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 4-7 years industry experience in physical design methodology. Good knowledge and hands on experience in physical design methodology which include logic synthesis,placement, clock tree synthesis, routing . Should be knowledgeable in physical verification ( LVS,DRC. etc), Noise analysis, Power analysis and electro migration . Team player with good problem solving skills, communication skills and leadership skills. Preferred technical and professional experience Automation skills in PYTHON, PERL , and/or TCL

Responsible for high performance microprocessor blocks RTL to GDSII implementation Perform block level synthesis, floor-planning, placement and routing. Close the design to meet timing, power budget and area. Implement ECO's to address functional bugs and timing violations. Team player, with good problem solving and communication skills. Required education Bachelor's Degree Required technical and professional expertise 5-8 years industry experience in physical design methodology. Good knowledge andhands on experience in physical design methodology which include logic synthesis,placement, clock tree synthesis, routing . Should be knowledgeable in physical verification ( LVS,DRC. etc), Noise analysis, Power analysis and electro migration . Team player with good problem solving skills, communication skills and leadership skills. Preferred technical and professional experience Automation skills in PYTHON, PERL , and/or TCL

-Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -12+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Urgent Opening for Sr Engineer- Physical Design Posted On 06th Oct 2017 11:52 AM Location Bangalore Role / Position Sr Engineer- Physical Design Experience (required) 3- 9 yrs Description : Responsible for all aspects of physical design and implementation. Responsibilities include chip floor plan, power / clock distribution, chip assembly and P&R, timing closure, power and noise analysis and back-end verification across multiple projects. High level of expertise in complete physical implementation tool chain; Good working knowledge and experience of netlist to GDSII flows Hands-on technical experience with deep sub-micron technology ASIC design, STA and physical implementation; Expertise in Synthesis, Static Timing Analysis and Timing Closure of High Performance Hard-Macros and/or Full Chip Physical Designs Should be independent, self-driven and a strong team player. Thorough understanding and knowledge of the entire Back end flow Netlist to gdsii Must be familiar with Industry standard tools like ICC / Encounter / Talus / Olympus Should have expertise in Timing analysis and closure Should have Tcl and perl scripting skills Should have work experience in the latest technology nodes like 16nm/14nm Should be familiar with low-power design and their impact on Back end flow (power switches / Level shifter / Isolation cell / retention cells / Back biasing / Forward biasing Send Resumes to girish.expertiz@gmail.com -->Upload Resume

Urgent Opening for Physical Design Sr Engineer / MTS / SMTS Posted On 27th Jun 2017 01:05 PM Location Bangalore / Hyderabad Role / Position Physical Design Sr Engineer Experience (required) 2-7 Years Description Designation :Physical Design Sr Engineer / MTS / SMTS Experience: 2 to 7 Years Location :Bangalore /Hyderabad : Responsible for all aspects of physical design and implementation.Responsibilities include chip floor plan, power/clock distribution, chip assembly and P&R, timing closure, power and noise analysis and back-end verification across multiple projects. High level of expertise in complete physical implementation tool chain; Good working knowledge and experience of netlist to GDSII flows Hands-on technical experience with deep sub-micron technology ASIC design, STA and physical implementation;Expertise in Synthesis, Static Timing Analysis and Timing Closure of High Performance Hard-Macros and/or Full Chip Physical DesignsShould be independent, self-driven and a strong team player. Thorough understanding and knowledge of the entire Back end flow Netlist to gdsii Must be familiar with Industry standard tools like ICC/Encounter/Talus/Olympus Should have expertise in Timing analysis and closure Should have Tcl and perl scripting skills Should have work experience in the latest technology nodes like 16nm/14nm/10nm Should be familiar with low-power design and their impact on Back end flow (power switches/Level shifter/Isolation cell/retention cells/Back biasing/Forward biasing) Qualifications:B.Tech / M.Tech or equivalent from a reputed University Send Resumes to girish.expertiz@gmail.com -->Upload Resume

Responsibilities: Should have good understanding of SoC design flow Hands-on expertise in writing RTL in Verilog and System Verilog (optional VHDL) language, SoC level RTL integration ,Linting, CDC checks, STA ,constraints, UPF

Skills Ability to lead a team size of minimum of 10 members who can handle Subsystem PNR Subsystem timing closure and Subsystem physical verification Experience 10-15years Job Location Bangalore, Hyderabad, Noida, Coimbatore Job Type Full Time

Job Details: Skill: SAP BODS Location: - PAN INDIA Notice Period: Immediate Joiners Employee type : C2H/FT Job Description: 1.Open to Hire/Work from any city 2.People with Total Exp of 6 + and mandatory 4 + exp in BODS will be considered 3.Notice : 2/3 weeks will be considered not more than that 4.Knowledge & Exp on SQL and PL/SQL along with BODS is required. Should have experience in Data Migration. 5.Open to Freelancers without any complications in the future (minimum 30 hrs support). 6.Work timings : 1pm to 10pm.

Immediate Openings on SAP BW Native HANA _ Bangalore_Contract Experience: 6+ Years Skill: SAP BW Native HANA Notice Period: Immediate . Employment Type: Contract Job Description 5 to 7 years experience in both BW and HANA Good skills in SQL and ABAP Well versed in Data warehousing concepts Expertise in both BW and ECC back end object development and support Extractors , experience using various SAP & other sources, ADSOs, Composite Providers, DSOs, info cubes, Multi providers, etc. Hands on and technical concepts with focus on HANA modelling. Proficient in design & development of HANA models Calculation views, procedures, Table functions etc ABAP Experience in writing & debugging ABAP code, user exits, extractors etc Shift timings - 2 PM to 11 PM IST.

Synthesis and Timing engineer to participate in the development of large SOCs with multiple physical blocks and 300+ clock domains. He/She must be high energy candidate with strong written and verbal communication skills, technically strong to find solutions and help the team both inside and outside the organization. REQUIRED SKILLS: RTL Design Quality checks, mainly Lint Automation using Python and TCL 5years+ experience, so not an NCG KEY RESPONSIBILITIES: Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff Drive the effort to maintain RTL quality metrics in complex, hierarchical designs and automating that process for improved efficiency. Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Work with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) flows Requires a mix of SDC knowledge, EDA tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts) PREFERRED EXPERIENCE: Worked with EDA tools that enable RTL quality checks Hands on experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows. Experience with analyzing the timing reports and identifying both the design and constraints related issues. Ability to multitask and grasp new flows/tools/ideas Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc. ACADEMIC CREDENTIALS: Bachelor's degree or Masters degree with 5years+ experience.

We are seeking a talented and detail-oriented Physical Backend Design Engineer to join our IC (Integrated circuit) development team. The role involves key aspects of physical design, including automated place and route, floorplanning, clock tree synthesis (CTS), static timing analysis (STA), power analysis, and physical verification (DRC/LVS). The ideal candidate will have a strong knowledge of physical design methodologies, experience with industry-standard tools, and a passion for delivering high-quality semiconductor solutions. You have: Bachelors Degree in Electrical Engineering, Computer Engineering, or a related field (Masters preferred) 3+ years of experience in physical backend design for ICs. Complex chip designs through all stages of physical implementation Experience with tape-out of designs for advanced nodes is highly desirable Strong knowledge of physical design concepts, including place and route (PnR), clock tree synthesis (CTS), static timing analysis (STA) and power grid design Experience with physical verification tools like Cadence Pegasus or Mentor Calibre Familiarity with parasitic extraction tools (e.g., StarRC, Quantus, Calibre xRC) Scripting skills in Python, Tcl, Perl, or Shell for automation Required ToolsCadence Innovus, Cadence Quantus, Cadence Tempus, Cadence Pegasus suite It would be nice if you also had: Experience with advanced process nodes (e.g., 7nm and below) Knowledge of low-power design techniques, such as multi-Vt, multi-Vdd, or clock gating Familiarity with DFT concepts and tools, Chip packaging and thermal analysis considerations, FinFET technology and 3D IC design methodologies Perform floorplanning, partitioning, and optimization to achieve area, power, and performance targets. Execute automated place and route (PnR) using industry-standard tools to generate physical layouts. Implement clock tree synthesis (CTS), ensuring low skew and efficient clock distribution. Conduct static timing analysis (STA) to verify timing closure and ensure the design meets performance requirements. Perform power analysis, including IR drop and electromigration (EM) checks, to optimize power distribution networks. Conduct physical verification tasks, including design rule checks (DRC) and layout vs. schematic (LVS) checks, to ensure manufacturability and compliance with foundry standards. Collaborate with design, verification, and DFT teams to resolve physical design challenges and improve chip performance. Work closely with foundry teams to address process technology issues and implement best practices.

5 to 7 years experience in both BW and Native HANA Good skills in SQL and ABAP Well versed in Data warehousing concepts Expertise in both BW and ECC back end object development and support Extractors , experience using various SAP & other sources, ADSOs, Composite Providers, DSOs, info cubes, Multi providers, etc. Hands on and technical conceptswith focus on HANA modelling. Proficient in design & development of HANA models Calculation views, procedures, Table functions Shift timings : 2 PM to 11 PM

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Design For Testability - DFT. Experience3-5 Years.