404 Sta Jobs - Page 15

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. General Summary PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains"“ LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux "“ Perl/TCL fundamentals/scripting Principal Duties and responsibilities: Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications: "¢ 12+ years Hardware Engineering experience or related work experience. "¢ 12+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Additional About The Role : 7-14 yrs experience in Physical Design and timing signoff for high speed cores. Should have good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology. Masters/Bachelors Degree in Electrical/Electronics science engineering with at least 7+ years of experience in IC design. Experience in leading block level or chip level Physical Design, STA and PDN activities. Work independently in the areas of RTL to GDSII implementation. Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.) Circuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.) Tcl/Perl scripting Willing to handle technical deliveries with a small team of engineers. Strong problem-solving skills.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. General Summary PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains"“ LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux "“ Perl/TCL fundamentals/scripting Principal Duties and responsibilities: Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications: "¢ 8+ years Hardware Engineering experience or related work experience. "¢ 8+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Services Group, Engineering Services Group > Program Management General Summary: Develops, defines, and executes plans of record, including:schedules, budgets, resources, deliverables, and risks. Monitors and drives the program from initiation through delivery, interfacing with internal and external stakeholders across functions on technical matters, as needed. Monitors budget/spending, on-time delivery, and achievement of program milestones. Represents the program and drives alignment across stakeholders. Minimum Qualifications: "¢ Bachelor's degree in Engineering, Computer Science, or related field. "¢ 5+ years of Program Management or related work experience. 12+ years experience in the semiconductor industry with 3+ years in Project/Program Management Good experience in Microsoft Tools like Excel, Power point, Word Must have strong interpersonal skills and be able to effectively communicate at all levels Sound knowledge and understanding of SOC design cycle, Development Process, and customer deployment Track record of proven leadership/management experience Process definition & implementation Minimum Qualifications: "¢ Bachelor"™s degree in engineering, Computer Science, or related field."¢ 3+ years of Program Management or related work experience."¢ 3+ years of working with operating budgets, resources, and/or project financials. Preferred Qualifications: "¢ Master's degree in Engineering, Computer Science, or related field. "¢ PMP Certification. "¢ 10+ years of Program Management or related work experience. "¢ 5+ years of work experience in a role requiring interaction with senior leadership (e.g., Director level and above). "¢ 3+ years of experience working in a large matrixed organization. "¢ 2+ years of experience with program management tools such as dashboards, Gantt charts, etc.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm Chennai is looking for a STA and Synthesis Engineer who is passionate in to work with cross-functional engineering teams. In this position, the engineer will be involved in all stages of the design and development cycles "¢ Synthesis, Static Timing Analysis and LEC of SoC/Cores "¢ Full chip and block level timing closure, IO budgeting for blocks "¢ Logical equivalence check between RTL to Netlist and Netlist to Netlist "¢ Knowledge of low-power techniques including clock gating, power gating and MV designs "¢ ECO timing flow "¢ Proficient in scripting languages (TCL and Perl). Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Bachelors / Masters degree in electrical or electronics engineering with 3-6 yrs of experience is preferred

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Be a member of the team that plays a significant role in ensuring the quality of Connectivity SoCs through structured DFT, Automatic Test Pattern Generation (ATPG) and Memory Built-In Self-Test (MBIST) techniques. Primary responsibilities will include,– Interface with design team to ensure DFT design rules and coverages are met. – Generating high quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models through the use of on-chip test compression techniques.– MBIST verification (including repair), test pattern generation through Mentor tool.– ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations.– Work with the Product/Test engineering teams on the delivery of manufacturing test patterns for ATE.– Responsible for supporting post silicon debug effort, issue resolution.– Responsible for Diagnostic Tool generation for ATPG, MBIST and bring-up on ATE.– Developing, enhancing and maintaining scripts as necessary Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 2-6 years"™ experience in ASIC/DFT "“simulation and Silicon validation– Detailed knowledge on DFT concepts, pattern simulation, Silicon debug and yield enhancement– In depth knowledge and hands-on experience in ATPG -coverage analysis.– In depth knowledge of Memory verification, repair and failure root-cause analysis.– Experience with any of these tools is required– ATPG - TestKompress– MBIST - Mentor ETVerify– Simulation - VCS (preferred), modelsim.– Expertise in scripting languages such as Perl, shell, etc. is an added advantage– Ability to work in an international team, dynamic environment with good communication skills– Ability to learn and adapt to new tools, methodologies.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. General Summary PNR implementation for Qualcomm Hexagon DSP IP's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains"“ LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux "“ Perl/TCL fundamentals/scripting Principal Duties and responsibilities: Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space. Job Responsibilities: Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications 2+ years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Minimum 3+ years of experience in PD Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. General Summary PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains"“ LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux "“ Perl/TCL fundamentals/scripting Principal Duties and responsibilities: Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications: "¢ 5+ years Hardware Engineering experience or related work experience. "¢ 5+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. General Summary PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains"“ LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux "“ Perl/TCL fundamentals/scripting Principal Duties and responsibilities: Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications: "¢ 3+ years Hardware Engineering experience or related work experience. "¢ 3+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. General Summary PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains"“ LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux "“ Perl/TCL fundamentals/scripting Principal Duties and responsibilities: Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications: "¢ 2+ years Hardware Engineering experience or related work experience. "¢ 2+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm Chennai is looking for a STA and Synthesis Engineer who is passionate in to work with cross-functional engineering teams. In this position, the engineer will be involved in all stages of the design and development cycles "¢ Synthesis, Static Timing Analysis and LEC of SoC/Cores "¢ Full chip and block level timing closure, IO budgeting for blocks "¢ Logical equivalence check between RTL to Netlist and Netlist to Netlist "¢ Knowledge of low-power techniques including clock gating, power gating and MV designs "¢ ECO timing flow "¢ Proficient in scripting languages (TCL and Perl). Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Bachelors / Masters degree in electrical or electronics engineering with 1-3 yrs of experience is preferred

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Responsibilities: STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs. Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus. Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. Evaluate multiple timing methodologies/tools on different designs and technology nodes. Work on automation scripts within STA/PD tools for methodology development. Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment Experience in design automation using TCL/Perl/Python. Familiar with digital flow design implementation RTL to GDS :ICC, Innovous , PT/Tempus Familiar with process technology enablement:Circuit simulations using Hspice/FineSim, Monte Carlo. Education :B.Tech or MTech/MS in Electrical/Electronics/Microelectronics/VLSI. Preferred Qualification/Skills Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling Hands-on experience with STA tools - Prime-time, Tempus Have experience in driving timing convergence at Chip-level and Hard-Macro level In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling, Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus) Knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation. Proficient is scripting languages "“ TCL, Perl, Awk Basic knowledge of device physics

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. General Summary PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains"“ LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux "“ Perl/TCL fundamentals/scripting Principal Duties and responsibilities: Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications: "¢ 1+ years Hardware Engineering experience or related work experience. "¢ 1+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 3+ years"™ experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG -In depth knowledge of DFT concepts. -In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. -Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors. -Knowledge of equivalence check and RTL lint tool (like spyglass). -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem-solving skills

Matillion Requirement/Skill Mandatory Skill combination Matillion, Python, SQL Experience 5 to 12 Yrs JR No 22022 Grade 5A Location All BSL Shift (Please specify Zone/timings) 2:30 PM to 11:30 PM IST Levels of interviews 2 Demand Immediate to 15 days CTC Bracket Upto 28 Lpa Mode of Work (Hybrid/Remote) Hybrid Location - Chandigarh,Dadra & Nagar Haveli,Daman & Diu,New Delhi,Goa,Lakshadweep,Puducherry,Sikkim,North Tripura

Key Responsibilities: Perform block-level STA and ensure timing closure at various design stages. Work with Synopsys Primetime, Cadence Tempus, or equivalent timing closure tools for analysis and optimization. Analyze and refine timing constraints at both pre-layout and post-layout stages. Collaborate with PD HM owners to provide timing feedback during placement, CTS, and routing phases. Generate timing ECOs for final timing closure using DMSA/Tweaker . Conduct MPW/MP/TDRC analysis and work with Infinisim tools as required. Analyze timing reports, debug violations, and propose fixes for efficient sign-off. Work closely with PD and STA engineers to meet design sign-off criteria. Preferred Skills: Expertise in Primetime/Tempus scripting and timing report analysis . Strong understanding of clock tree synthesis (CTS), routing strategies, and timing convergence . Experience in multi-corner, multi-mode (MCMM) timing analysis . Familiarity with low-power design techniques and constraint optimizations . Strong problem-solving and debugging skills in STA and PD workflows . Interested candidates can share their resumes to shubhanshi@incise.in

You will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology. In this position, you will be responsible for timing analysis and convergence of complex partitions. Your responsibilities will include but not limited to: 1. Responsible for timing execution and convergence including setup and hold for over 5GHz Freq and low-power digital designs. 2. Deep understanding of Static timing analysis concepts 3. Timing Convergence across all HVM targets4. Closely work with SD, Integration and Floor plan teams Qualifications You must possess a Masters Degree in Electrical or Electronics Engineering with at least 4 or more years of experience in related field or a Bachelor's Degree with at least 6 years of experience. Technical Expertise in Static Timing Analysis is preferred. Preferred additional skills :- Experience of handle complex core design, high-speed designs - Timing signoff flows/tools experience both/either Synopsys/Cadence tools - Very good knowledge on Timing tools, flows and methodology - Ability to handle new feature feasibility studies - SD flow knowledge would be plus- Familiarity with Verilog/VHDL - Tcl, Perl, Python scripting - Strong verbal and written communication skills

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Automatic Test Pattern Generation (ATPG) Good to have skills : NA Minimum 7.5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your day will involve overseeing the application development process, coordinating with team members, and ensuring project milestones are met. Roles & Responsibilities: Expected to be an SME Collaborate and manage the team to perform Responsible for team decisions Engage with multiple teams and contribute on key decisions Provide solutions to problems for their immediate team and across multiple teams Lead the application design and development process Coordinate with stakeholders to gather requirements Ensure project milestones are met Professional & Technical Skills: Must To Have Skills:Proficiency in Automatic Test Pattern Generation (ATPG) Strong understanding of software development lifecycle Experience in application architecture design Knowledge of database management systems Hands-on experience in application testing Additional Information: The candidate should have a minimum of 7.5 years of experience in Automatic Test Pattern Generation (ATPG) This position is based at our Bengaluru office A 15 years full-time education is required Qualifications 15 years full time education

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Automatic Test Pattern Generation (ATPG) Good to have skills : NA Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your day will involve overseeing the application development process, coordinating with team members, and ensuring project milestones are met. Roles & Responsibilities: Expected to be an SME Collaborate and manage the team to perform Responsible for team decisions Engage with multiple teams and contribute on key decisions Provide solutions to problems for their immediate team and across multiple teams Lead the application development process effectively Coordinate with team members to ensure project milestones are met Professional & Technical Skills: Must To Have Skills:Proficiency in Automatic Test Pattern Generation (ATPG) Strong understanding of software development lifecycle Experience in application design and configuration Knowledge of project management methodologies Hands-on experience in leading application development projects Additional Information: The candidate should have a minimum of 5 years of experience in Automatic Test Pattern Generation (ATPG) This position is based at our Bengaluru office A 15 years full-time education is required Qualifications 15 years full time education

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Automatic Test Pattern Generation (ATPG) Good to have skills : NA Minimum 12 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your day will involve overseeing the application development process, coordinating with team members, and ensuring project milestones are met. Roles & Responsibilities: Expected to be an SME Collaborate and manage the team to perform Responsible for team decisions Engage with multiple teams and contribute on key decisions Provide solutions to problems that apply across multiple teams Lead the application development process effectively Coordinate with team members to ensure project milestones are met Provide guidance and support to team members Professional & Technical Skills: Must To Have Skills:Proficiency in Automatic Test Pattern Generation (ATPG) Strong understanding of software development lifecycle Experience in leading application development projects Excellent communication and leadership skills Ability to analyze complex technical requirements Additional Information: The candidate should have a minimum of 12 years of experience in Automatic Test Pattern Generation (ATPG) This position is based at our Bengaluru office A 15 years full-time education is required Qualifications 15 years full time education

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Automatic Test Pattern Generation (ATPG) Good to have skills : NA Minimum 3 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. You will be responsible for overseeing the application development process and ensuring successful project delivery. Roles & Responsibilities: Expected to perform independently and become an SME. Required active participation/contribution in team discussions. Contribute in providing solutions to work-related problems. Lead the application development team in designing and building applications. Act as the primary point of contact for all application-related queries. Ensure timely delivery of high-quality applications. Provide technical guidance and mentorship to team members. Collaborate with stakeholders to gather requirements and define project scope. Professional & Technical Skills: Must To Have Skills:Proficiency in Automatic Test Pattern Generation (ATPG). Strong understanding of software development lifecycle. Experience in leading application development projects. Knowledge of programming languages and frameworks. Hands-on experience in application configuration and deployment. Additional Information: The candidate should have a minimum of 3 years of experience in Automatic Test Pattern Generation (ATPG). This position is based at our Bengaluru office. A 15 years full-time education is required. Qualifications 15 years full time education

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Automatic Test Pattern Generation (ATPG) Good to have skills : NA Minimum 12 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your day will involve overseeing the application development process, collaborating with teams, and making key decisions to ensure project success. Roles & Responsibilities: Expected to be an SME Collaborate and manage the team to perform Responsible for team decisions Engage with multiple teams and contribute on key decisions Provide solutions to problems that apply across multiple teams Lead the application development process effectively Ensure timely delivery of projects Mentor junior team members for their professional growth Professional & Technical Skills: Must To Have Skills:Proficiency in Automatic Test Pattern Generation (ATPG) Strong understanding of software development lifecycle Experience in leading application development projects Knowledge of Agile methodologies Excellent communication and leadership skills Additional Information: The candidate should have a minimum of 12 years of experience in Automatic Test Pattern Generation (ATPG) This position is based at our Bengaluru office A 15 years full-time education is required Qualifications 15 years full time education

PD Weekend Drive at Ahmedabad / Bangalore/Hyderabad 4-10 years experience with Bachelors degree in Electronics Engineering or equivalent Knowledgeable in all aspects of deep submicron ASIC design flow. Knowledgeable in Static Timing Analysis, Power Analysis and Physical Verification. Hands-on experience in developing and modifying PD-flow/EDA-tools scripts/recipes using TCL/SHELL/PYTHON programming languages. Experience in developing PD metrics dashboard scripts for QOR tracking is a plus Experience in modifying STA constraints to check timing closure feasibility Experience in various clock implementation strategies (Multi-point CTS, Flex-H, Custom-CTS) for meeting block level and full chip level latency and skew targets Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5/3nm Please forward your updated profile to below details to chakradhar.marupuru@quest-global.com.

Job Description In this position, you will be responsible for managing and working on all aspects of SOC Physical design flow, STA and timing closure activities of Intel SoCs in lower technology nodes. Your tasks will include but not limited to:Design and Architecture understanding. Interaction with FE/DFT/Verification teams. Synthesis, floor planning, placement, routing, clocking, Constraints development. Understanding on synchronous and asynchronous paths, Clock domain crossing issues, deciding timing signoff modes and corners, Design margins. Hierarchical timing including IO budgeting for partitions. Drive the designs to timing and physical design closure. Performs physical design implementation of SOC from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, and power and noise analysis. Qualifications Education: B.Tech. or M.Tech. in Electrical/Electronics Engineering with 6-12 years' of experience. Key skills: In-depth knowledge and hands-on experience in all aspects of physical design flow in SOC such as synthesis, place, clock tree synthesis, route and signoff. Good understanding and exposure of overall Timing closure cycle in SoC. Experience in deep submicron process technology nodes is strongly preferred Solid understanding industry standard tools for synthesis, place and route(Fusion Compiler) and timing flows. Good scripting skills in TCL/Perl/Shell. Expertise in STA signoff tools (PT). Solid understanding of the process and design interactions as they relate to target frequency and interaction with timing paths and resulting leakage and power trade-offs. Solid technical and good communication skills.