1617 Sta Jobs - Page 13

As Logic Lead, you will be responsible for design and development of Compression, Security, and sustainability features for high performance Processors chips. Lead the Development of features - propose enhancements to existing features, new features, architecture in High level design discussions Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW, Research teams to develop the feature Guide and mentor junior engineers. Represent as Design Lead in various forums. Signoff the Pre-silicon Design that meets all the functional, area and timing goals Participate in silicon bring-up and validation of the hardware Estimate the overall effort to dev...

We are looking for a skilled SAP DRC Consultant with 19 years of experience to join our team at Forward Eye Technologies. The ideal candidate will have a strong background in SAP DRC and be able to work effectively in a fast-paced environment. Roles and Responsibility Collaborate with cross-functional teams to design and implement SAP DRC solutions. Provide technical expertise and support for SAP DRC projects. Develop and maintain documentation for SAP DRC implementations. Troubleshoot and resolve complex technical issues related to SAP DRC. Conduct training sessions for end-users on SAP DRC functionality. Work closely with stakeholders to understand business requirements and develop solutio...

Role Overview We are expanding our team in India and seeking a Staff Digital Design Engineer to lead the micro-architecture and implementation of advanced digital subsystems for automotive Ethernet communication systems You will collaborate across analog and digital teams to deliver high-performance, reliable solutions for next-generation automotive networks Required Skills + BS/MS/BTech/M Tech in Electrical Engineering or related field + 8+ years of experience in digital design for communication systems + Expertise in Verilog/SystemVerilog, Ethernet or similar protocols, and PHY layer design + Strong understanding of PLLs, clocking schemes, and timing closure + Experience with analog IP int...

In your new role you will: Implement high-performance, low-power, and area-efficient digital designs. Write and implement block level and top-level constraints for Synthesis, Static Timing Analysis . Optimize designs for power, performance, and area, and meet PPA goals. Power analysis using PT-PX or equivalent flow. Logic Equivalence Check (LEC) and Low Power Checks (CLP) at block and SoC level designs. Define and evaluate constraints and signoff Test/DFT mode timing requirements. Knowledge on Power analysis and PT-PX flow Your Profile You are best equipped for this task if you have: Bachelors or Masters in Electrical/Electronics Engineering with 8+years of relevant experience. Delivery orie...

1. RTL development and Verification for Digital subsystems, Memory Subsystems including BIST. 2. DFT Insertion and Verification signoff for IO, ARM-PNR, Memory Digital Subsystems with Tessent/Embedded MBIST 3. MBIST, ATPG, RSQ Verification and sign-off. 4. Formal verification, Cross Clock Domain checks, Power/Timing sign off 5. Verify complex Digital subsystems through OVM, UVM methodology, creating the Verification Suit Independently. Skillset: 1. Hands on Experience with RTL, Synthesis, 2. Hands on experience in defining ICC/Synthesis constraints that meets timing closure needs 3. Familiarity with DFT flows includes MBIST, ATPG, RSQ and Verification methodologies and best practices for the...

We are looking for a skilled Senior Manager - Physical Design with 10-15 years of experience to lead our team in Bangalore, Hyderabad, Noida, Coimbatore. The ideal candidate will have a strong background in physical design and excellent leadership skills. Roles and Responsibility Manage and lead a team of physical design engineers to achieve project goals. Develop and implement automation scripts for physical design methodologies. Collaborate with front-end engineers to resolve timing and power issues. Evaluate new tools and drive power reduction of designs. Perform floorplanning and time budgeting for successful project execution. Ensure timely completion of projects by managing resources e...

What You''ll Do Cisco SiliconOne team is looking for an expert and talented ASIC Engineer. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products. Responsibilities Looking for a Front-end Design ASIC Engineer. Architectural work: in-depth understanding of the architecture, and identification of problems and solutions. All aspects of implementation: specification, design, timing-analysis, power-optimization, flow automation, optimization of the logic for ...

Join Optical Networks division, where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, weve united two industry leaders to create an optical networking powerhousecombining cutting-edge technology with proven leadership to redefine the future of connectivity. Infinera is now part of the Nokia Corporation and its subsidiaries. When you apply, the information you share will be handled with care and used only for recruitment purposes within the group. Work as part of a world class ASIC design team, building leading edge chips for the Coherent Optics market. Hold a Bachelor or masters degree in electrical or computer engineering Have a minimum 2 ye...

Experience with low-power ASIC design techniques and clock domain crossing Knowledge of AMS verification methodologies Exposure to silicon bring-up and lab validation Familiarity with EDA tools from Synopsys, Cadence, or Mentor Bachelors or Masters degree in Electronics Engineering, Computer Engineering, or related field 8+ years of experience in ASIC digital design, with couple of years of technical leadership role Strong expertise in RTL design, CDC, synthesis, STA, LEC.. Proven experience in mixed-signal ASICs for deep sub-micron and understanding of analog-digital interfaces Familiarity with any scripting languages Excellent problem-solving, communication, and leadership skills Key Respo...

We are seeking highly motivated DFT Engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation and delivery of DFT patterns for IBM’s chip design team. As a member of DFT team, you will be required but not restricted to insertion, pattern generation, simulation, validation, characterization, delivery to TAE, IBM’s Hardware Bring-up and Silicon Debug. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Hands-on experience in DFT on complex designs involving scan insertion, compression, MBIST, ATPG, simulations and IP integration and validation. Proven expert...

We are seeking highly motivated individuals with a BS, MS, or PhD degree in Computer Science, Computer Engineering/ECE, ready to handle the challenging problems in future technologies and designs. We are seeking energetic, highly motivated individuals willing to go the extra mile with the aim of helping the overall IBM development team. Our dynamic global team is looking to enlist enthusiastic professionals to join world-class hardware design teams responsible for developing the most challenging and complex systems in the world. We are looking for a passionate & experienced EDA Methodology Engineer to join our timing team focusing on timing methodology using IBM Einstimer, Cadence & Synopsys...

This Position reports to: Global Product Marketing Manager ABB Smart Power provides energy distribution solutions for data centers, industrial and manufacturing plants, critical infrastructure and commercial buildings. The Divisions technical teams work closely with industry partners, delivering advanced solutions that support rapid growth, energy transition, and sustainability objectives. The Divisions portfolio includes industrial circuit breakers, low-voltage systems, motor starting applications, and safety devices like switches and relays. Its Power Protection unit supports the worlds largest data center companies with advanced energy-efficient UPS solutions. The Divisions ABB Ability En...

Role & responsibilities To Contributes to policy discussions and is responsible for implementing policy decisions in administration areas. Responsible for the delivery of a full range of administrative services. Responsible for overseeing and managing all aspects of the following: Communication Telephone Board Mobile / Landline Housekeeping Office & Plant Disposal of waste Security Miscellaneous Service Office Administration Company Vehicle Mgmt Administration Policy Employee Welfare Open Communication Family Day Sports Activities

Location: Bangalore, Hyderabad, Noida, and Coimbatore. Skills: Soc level floorplanning, partitioning, timing budget generations, power planning, SOC PnR, CTS, block integration Handling timing closure of high frequency blocks. Expertise in signoff closure Timing with SI and OCV, Power, IR and physical verification at both block and chip level. Understanding constraints and fixing techniques. Experience in physical verification Understanding SI prevention, fixing methodology and implementation. Proficient in Synopsys ICC or Cadence or Mentor Olympus and Atoptech tool set. Experience in Design Automation and UNIX system. Experience in Tcl/ PERL is a plus. Primary Skills: Able to handle Soc PNR...

As a RTL Design Engineer at Qualcomm India Private Limited, you will be part of the Qualcomm modem team working on cutting-edge wireless technology for industry-leading devices. Your responsibilities will include: - Contributing to RTL design and integration of flagship Modem core IPs. - Developing microarchitecture specifications from high-level exploration to detailed specifications. - Owning RTL development to meet power, performance, area, and timing goals. - Collaborating with cross-functional teams for issue resolution and timely project execution. - Debugging, identifying issues, providing workarounds, and recommending bug fixes. The ideal candidate should have: - 1 to 4 years of fron...

As an ASIC STA Engineer at NVIDIA, you will be an integral part of the outstanding Networking Silicon engineering team, contributing to the development of cutting-edge high-speed communication devices for AI platforms. Your role will involve the following key responsibilities: - Be responsible for full chip and/or chiplet level STA convergence from the early stages to signoff. - Participate in top-level floor plan and clock planning activities. - Collaborate with CAD signoff flows and methodologies to optimize performance. - Integrate timing for digital partitions and analog IPs, providing feedback to PD/RTL and driving convergence. - Define and implement constraints for various work modes i...

Role Overview: You will be responsible for leading the architecture, design, and verification of digital blocks for mixed-signal ASICs. Your role will involve collaborating closely with Analog and System teams, guiding RTL design, optimizing power, performance, and area, and contributing to IP reuse strategy and design methodology improvements. Additionally, you will provide technical leadership across cross-functional teams and support post-silicon validation. Key Responsibilities: - Lead the architecture, design, and verification of digital blocks for mixed-signal ASICs - Collaborate closely with Analog and System teams to define specifications and ensure seamless integration - Drive RTL d...

We are looking for Physical Design Engineers for Tranzium Semi Pvt.Ltd. An experienced Physical Design Engineer who has knowledge of STA/Synthesis/Floor Planning/ Place and Route/Timing Closure/Physical Layout/Automation/Power and Signal Integrity.

Role Overview: As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will play a crucial role in planning, designing, optimizing, verifying, and testing electronic systems. Your responsibilities will involve working on a variety of systems, including circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment, packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge products. Collaborating with cross-functional teams, you will develop solutions to meet performance requirements and contribute to the digital transformation of future technologies. Key Responsibilities: - Front-End/Digital design implementation of Sensor/Mixed signal digital blocks...

As a Synthesis & STA engineer, you will be responsible for performing RTL Synthesis to optimize the Performance/Power/Area of the designs. Your role will involve DFT insertions such as MBIST and SCAN, setting up Timing Constraints for functional and Test Modes, and Validation. You will be expected to create Power Intent for the designs, verify power intent on RTL, run static Low-Power checks on gate level netlists, and ensure Logic Equivalency Checks between RTL to Gates and Gates to Gates. Collaborating with the Design/DFT/PD teams, you will set up signoff Static Timing Analysis and ECO flows to achieve timing closure. Additionally, you will be involved in Power Analysis, estimating power a...

Role Overview: You will be working as a Fellow Silicon Design Engineer at AMD to develop world-class Server products. Your main responsibility will be to define and drive PPA uplift methodologies, develop power optimization methodology for Physical Design Implementation, define PVT corners and frequency targets for next-generation Servers, and have a deep knowledge of micro-architecture, power optimization methodologies, and timing closure. You are expected to have very strong problem-solving skills, broad experience in methodology, and a self-motivated work ethic to provide a cohesive technical vision for PPA improvement methodology. Key Responsibilities: - Define and drive PPA uplift metho...

Meet the Team Join the Cisco Silicon One team in developing a unified silicon architecture for web-scale and service provider networks. Cisco''s silicon team provides an outstanding, unique experience for ASIC engineers by combining the resources offered by a sizable multi-geography silicon organization and a large campus (with an on-site gym, healthcare, caf, social interest groups, and philanthropy) with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact Write micro-architecture specifications and participate in reviews. Implement Verilog RTL to meet timing, performance, and power requirements. Contribute to full chip integr...

Responsible for meeting agreed market metrics - Fill rate (Line & Piece), Inventory Turns, Back orders etc. Perform all daily/weekly/monthly processes diligently without any backlog thereby meet key deliverables. Work closely with sources for schedule adherence and ensure timely receipt of parts at warehouse. Handle Vehicle off road orders promptly and provide accurate information to dealers. Select parts for A/F based on its function code and its criticality. Maintain Inventory at optimal level and thereby meet inventory turn targets. Perform denial analysis and work towards implementing the containment actions. Review forecast changes, stock order suggestions and validate Ensure all open i...

Role : Senior STA Engineer Experience Required : 4-5 YEARS Job Location: HYDERABAD Bachelors or Masters degree in Electrical/Electronics Engineering. Preferred Qualifications: Experience with full-chip STA closure. Exposure to low-power design techniques and multi-mode/multi-corner analysis. Knowledge of timing integration for third-party IPs. Required Skills: Strong understanding of STA fundamentals and timing closure methodologies. Proficiency in tools like PrimeTime, Tempus, Tweaker, Timevision, Fishtail. Experience with scripting languages (TCL, Perl, Python) for automation. Familiarity with advanced nodes (e.g., 7nm, 5nm, FinFET). Good grasp of physical design flow and constraints manag...

Responsible for leading Physical Design and Timing Closure of low power SoCs. Responsible to achieve die area, performance, power goals for hierarchical blocks and top. Drive physical design implementation which includes package co-design , floor planning, power grid design and signoff, place and route, timing closure, physical verification checks. Influence tools, flows and methodology activities to improve upon QoR. Interact with cross-functional team members to improve design, methodology and process aspects. Enable next generation of place and route engineers via mentoring and thought leadership. Your Profile You are best equipped for this task if you have: Hands-on experience in physica...