1617 Sta Jobs - Page 10

Responsible for mobilizing youth for training programs and ensuring successful placement through employer engagement and community outreach. Mobilize youth and conduct outreach Counsel and enroll candidates Coordinate placements and employer interactions Maintain placement records and follow-ups Support training and center operations

Responsible for mobilizing youth for training programs and ensuring successful placement through employer engagement and community outreach. Mobilize youth and conduct outreach Counsel and enroll candidates Coordinate placements and employer interactions Maintain placement records and follow-ups Support training and center operations

Job Summary: We are looking for a proactive and detail-oriented STA Engineer (Supplier Technical Assistance Engineer) to manage and support supplier development and performance. You will be responsible for ensuring that suppliers meet the companys quality, technical, and delivery standards across all phases of the supply chain, from sourcing to production. Key Responsibilities: Evaluate and approve new suppliers through audits, assessments, and technical reviews Monitor and improve supplier performance in terms of quality, cost, delivery, and compliance Provide technical support to suppliers to ensure part quality and manufacturability Work closely with suppliers on PPAP (Production Part App...

Role Overview: Looking for experienced Physical Design Engineer with 4+ years in block-level implementation. The role emphasizes PnR, STA, and logic implementation, driving designs that meet PPA requirements while ensuring sign-off quality. Key Requirements: *Hands-on in floor planning, placement, CTS, routing, and optimization. *Strong background in PnR flows, resolving timing, congestion, power, and SI challenges. *Skilled in STA analysis, ECO handling, and top-level support. *Tool expertise with Synopsys / Cadence and logic equivalence checks. *Proficient in design rule checks (DRC/LVS) and PPA-driven optimizations. *Familiarity with low-power techniques and scripting (TCL, Perl, Python).

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

Job Title: Physical Design Engineer Experience: 4+ Years Location: Banglaore/Hyderabad Employment Type: Full-time Industry: Semiconductors / VLSI / ASIC Design Job Summary: We are looking for a skilled and motivated Physical Design Engineer to join our backend implementation team. The engineer will be responsible for RTL-to-GDSII implementation of complex SoC blocks or full-chip designs, targeting performance, power, and area (PPA) optimization and signoff closure. Key Responsibilities: Own block-level or full-chip implementation from RTL to GDSII. Perform: Floorplanning and placement Clock tree synthesis (CTS) Routing and optimization Run and close timing (STA), IR drop, EM, DRC, LVS, and a...

As a CAD Applications Engineer at Micron Technology, Inc., you will be working in a collaborative, production support role evaluating, improving EDA and debugging both in-house and commercial Electronic Design Automation (EDA) tools and flows for Static Timing Analysis (STA). You will work closely with the Design teams to increase their productivity and work efficiency. Responsibilities and Tasks include, but are not limited to: - Deliver methodology and tool solutions for static timing closure and power optimization. - Deploy innovative modeling and optimization approaches to achieve globally optimal targets. - Prudently apply best-in-class algorithms and ECO techniques for value-adding des...

Department FIL India Technology - WPFH - Testing About team Technology and engineering testing team is evolving at a fast pace to cater to strategic technology drivers and to meet end customer experience demands. Here experienced technologists drive this space with dedicated energy, passion, and inspiration and delivery quality solution with faster pace. About role The role would focus on services, functional, test automation and cover for key capability gaps and give this a shape of a programme with clear prioritised / agreed scope and agenda. The role will leverage/guide the existing automation experts to get this prioritised backlog delivered on time. The key outcomes shall be (but not li...

Work with design and architecture teams to define and generate timing constraints that specify the desired timing requirements for the design.Set up and configure STA tools (e.g., Cadence Encounter, Synopsys PrimeTime) for the analysis, including library characterization, delay models, and clock definitions. Perform static timing analysis to evaluate setup and hold times, clock-to-q delays, and other timing metrics. Ensure that the design meets timing requirements for various corners and operating conditions (e.g., process, voltage, temperature variations). Identify and analyze asynchronous signals crossing between different clock domains to ensure proper synchronization and to avoid metasta...

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills.

Key Responsibilities : Lead and manage RTL design activities for complex ASICs, ensuring high performance and low power consumption. Integrating RTL components into System-on-Chip (SoC) designs Integrating RTL components into System-on-Chip (SoC) designs Architect and implement RTL for digital circuits (such as processors, communication systems, or custom IP cores). Mentor and guide junior RTL engineers in best practices for design, coding standards, and optimization techniques. Develop and refine RTL code in Verilog/SystemVerilog for ASIC development. Collaborate with cross-functional teams (Verification, Physical Design, and Software) to ensure successful integration of the ASIC design. Pe...

Job Description: . Required Skills and Experience: Bachelor or Masters degree in Electrical or Computer Engineering 4-7 years of experience in developing timing & power models (NLDM, CCS, etc.) for standard cell, I/O and custom circuits preferably in 12nm and below nodes Hands on experience with running PrimeTime, extracting timing data for custom PnR blocks In depth knowledge of electrical engineering fundamentals including CMOS device operation and characteristics, including understanding of advancing modeling techniques Hands on experience with simulation using HSPICE, Hsim or Finesim Experience with scripting tools such as Python/Perl/Shell etc. Initiative (self-motivated, self-confident...

Key Responsibilities Work with system and micro-architects to define high-level, implementable specifications Develop RTL and run front-end flows such as lint, CDC, low-power checks, Conformal, and DFT checks Collaborate with verification teams on test plan development and debugging Run synthesis, manage timing constraints, and deliver synthesized netlists to physical design teams Write and manage UPF files; perform power-aware equivalence and low-power checks Coordinate with DFT, physical design, and emulation teams to meet project goals Support post-silicon validation teams in bring-up and debug

Key Responsibilities Lead STA and PNR efforts for large, multi-interface, or mixed-signal subsystems Develop and refine STA and PNR methodologies tailored to complex subsystem challenges Drive automation and validation of timing and physical design data across subsystem boundaries Mentor and guide junior engineers, fostering technical growth and knowledge sharing Collaborate cross-functionally to resolve design, timing, and physical implementation challenges Present technical solutions and lead discussions with internal teams and customers on subsystem-level trade-offs and integration

Responsibilities: Lead RTL synthesis and constraints generation/validation for MCU SoCs to meet performance, power, and area targets Develop and implement innovative methodologies and tools to improve design quality and engineering productivity Act as the key interface between frontend and backend design teams, resolving hand-off and timing-related issues Conduct detailed design reviews and provide feedback to peers and junior engineers Collaborate with cross-functional teams to resolve design collateral issues and enhance overall PPA (Power, Performance, Area) Support low power implementation flows and techniques Perform formality checks to ensure RTL vs. netlist equivalence

As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will play a crucial role in planning, designing, optimizing, verifying, and testing electronic systems. Your responsibilities will involve working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. Your collaboration with cross-functional teams will be essential in developing solutions and meeting performance requirements. **Key Responsibilities:** - Plan, design, optimize, verify, and test electronic systems - Work on circuits, mechanical systems, Digital/Analog/RF/optical systems, test systems, ...

RTL2GDS flow creation and qualification for Synthesis, Place and Route, Extraction, Timing and Physical Verification Will be closely collaborating with EDA vendors and PDK to define, implement, customize, and qualify digital design flows Uses TCL, Python, Pandas and Google APIs to create automation for flow regressions, to collect and compare flow errors, warnings and key design metrics to ensure good quality PDK release and released flow backward compatibility to PDK Use reference flows to perform cross tool and PDK PPA benchmarking Define and generate design testcases to target and measure specific aspects of GLOBALFOUNDRIES PDK and technology changes Work independently in an international...

We are seeking highly motivated, energetic, and team-oriented individual contributors who can work on synthesis, LEC, and constraints for NXPs digital IPs, working in close collaboration with the RTL team. Key Responsibilities Work closely with the architects and RTL team on synthesis, LEC, and constraints of NXP digital IPs Carry out floor planning, and physically aware synthesis on high-performance IPs Perform timing and power analysis on the design database (db), improve the recipe, and provide timing feedback to the RTL team Leads or solo owners are expected to work with minimal micro-management needs. They should be able to communicate with other project members to manage task divisions...

Seeking an experienced Delivery Lead to oversee the overall service delivery management for our Oracle Managed Services project. The Delivery Lead will ensure adherence to Service Levels described in the agreement and collaborate closely with the client's Service Delivery management personnel. The role involves managing the compilation of metrics around open tickets, backlog, aging, etc., and driving metrics-driven continuous improvement and customer satisfaction. Responsibilities: Oversee overall service delivery management Ensure adherence to Service Levels Collaborate with client Service Delivery management personnel Manage the compilation of metrics around open tickets, backlog, aging, e...

Seeking an experienced Delivery Lead to oversee the overall service delivery management for our Oracle Managed Services project. The Delivery Lead will ensure adherence to Service Levels described in the agreement and collaborate closely with the client's Service Delivery management personnel. The role involves managing the compilation of metrics around open tickets, backlog, aging, etc., and driving metrics-driven continuous improvement and customer satisfaction. Responsibilities: Oversee overall service delivery management. Ensure adherence to Service Levels. Collaborate with client Service Delivery management personnel. Manage the compilation of metrics around open tickets, backlog, aging...

Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Emulation Good to have skills : NA Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, you will analyze, design, code, and test multiple components of application code across one or more clients. You will perform maintenance, enhancements, and/or development work in a dynamic environment, contributing to the success of the projects. Roles & Responsibiliti...

Lead a team of 5-10 resources Understand the design specification , PowerOn Specification Understand boot firmware and reset flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise 8+ years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and in...

Job Title: Lead DFT Engineer Experience: 7+ Years Location: Bangalore Employment Type: Full-time Industry: Semiconductors / ASIC / SoC Design Job Summary: We are looking for a Lead DFT Engineer to drive DFT architecture, planning, and implementation across complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with cross-functional teams, and ensure world-class testability and manufacturability of silicon products. Key Responsibilities: Define and drive DFT strategy and architecture for multiple ASIC/SoC projects. Lead implementation and verification of DFT features like: Scan insertion and compression (e.g., EDT) ATPG pattern generation and fault grad...

Skills requried: In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience on Physical Design Methodologies and sub-micron technology of 16nm and lower technology nodes. Should have experience in Analog and Mixed Signal Design Should have experience in handling >5M instance count , 1.5GHz frequency designs. Should have experience on programming in Tcl/Tk/Perl to automate design process and improve efficiency. Must have hands-on experience on PnR Suite from Cadence & Synopsys (Innovus & ICC2) Strong experience on Static T...

Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, IP integration, Extraction, Physical Verification, and taking blocks to the closure. Job Description In your new role you will: Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, IP integration, Extraction, Physical Verification, and taking blocks to the closure. Design Application Engineering (DAE) will be responsible for supporting project teams using Infineon Design System (Flows, Design Package & Design assistance). You will be the first point o...