Microcircuits technology is looking for DFT Engineers to join our dynamic team and embark on a rewarding career journey. Research and draft blueprints, engineering plans, and graphics. Develop test prototypes. Identify solutions to improve production efficiency. Use design software to develop models and drawings of new products. Maintain existing engineering records and designs. Assess all engineering prototypes to determine issues or risks. Estimate cost limits and budgets for new designs. Supervise the manufacturing process of all designs. Coordinate with other engineers, management, and the creative department.

Key Responsibilities Work closely with design team to review the design spec and define/participate detailed testplan Strategy and verification plan Develop testbench at SOC level for complex ASIC System-On-Chips Develop and maintain verification environment in UVM Implementation verification including Scan, JTAG related logic. Develop and improve the verification flow and methodology Maintain regression and debug test failures with designers Requirements : B. Tech /BE/ME/M Tech in Computer Science, Electronics/Electrical Engineering or related fields with 2 - 10 years of relevant hands-on experience. Hands-on experience on using Verilog, System Verilog and UVM (Universal Verification Methodology) Experience in Unit and SoC Verification, JTAG insertion. Deep understanding of modern verification concepts. Good scripting skills in languages such as Perl, Tcl, or Python. Programming skills in System Verilog, C, C++ Working knowledge of RTL coding in Verilog, Synthesis STA Self-motivated team player with strong problem-solving skills to collaborate with various teams to achieve desired goals. Excellent written and verbal communication skills.

About The Role About The Role As a SoC Micro-Architect, you will be responsible to work on feasibility of feature requests, partitioning them effectively and proposing an effective implementation which meets the desired Power, Performance and Area targets. You will need to work with cross functional teams and will be responsible for defining Micro-architecture specifications. Work with SoC Architecture, Platform, Firmware, Logic, Validation, Physical and DFT teams in defining and guiding SoC design implementationResponsibilities and duties:* Work with SoC Architecture to interpret high level architecture specs* Drive feature analysis and scoping* Define micro-architecture specifications.* Perform feasibility study on different third-party IP and drive integration* Drive RTL Implementation team, work closely with Backend team on floorplan, Constraints definition and timing analysis.* Closely work with Verification team and help define test plan and debug design.* Participate in design reviews.* Participate and drive timing convergence for high-speed designs including micro- architecture optimizations* Collaborate with internal and external team members on architectural decisions, development flows and methodologies* Lead end to end feature implementation and enablement.* Responsible for meeting SoC design quality, performance and power goals Qualifications Required qualifications:Educational requirements for this position are a BSEE/CE minimum, MS preferred.Also required 18 plus years' experience in IC/SoC Design and Micro Architecture* Experience in all phases of logic development lifecycle from high-level specification to tape-out and production* Expertise in one or more of the following domains* AI server Micro Architecture* Power Management* Cache Management* Inter die IOs Micro Architecture* HBM IOs Micro ArchitectureBehavioral Traits* Excellent communication and documentation skill.* Must be skilled to influence in heavily matrixed environment.* Capable to operate in ambiguity where roles may not be clearly defined or teams across multiple/functions and IP/SOC must be pulled together.In this role you will be part for the Data center group (XEG - India) design team, working on next-generation Server and AI products. Inside this Business Group Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap. Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

1. Hands on work on custom layout for analog blocks like High Speed SerDes and General purpose IO designs with Cadence Virtuoso on latest technologies like 5nm and below and also take leadership roles in delivery of IPs 2. Work on Floor planning, power design, signal routing strategy, EMIR awareness andparasitic optimisations 3. Understand and apply analog Layout techniques to ensure the design meets performance with minimum possible area and good yield. 4. Participate in building and enhancing layout flow for faster, higher quality design process. 5. Checking physical verifications like DRC/LVS/ERC/ANT/DFM and other IBM internal checks 6. Collaborate with Circuit Designers to solve challenging problems 7. Writing SKILL/PYTHON scripts to automate repetitive tasks 8. Work with Place and Route engineer to integrate custom macros into top level. 9. Able to perform design reviews across global team 10. Work closely with required global teams to ensure the success of the whole product. 11. Leadership in delivery of macros we plan to own from India Job requirements: 1. Experience in doing layouts for analog blocks like SerDes, ADCs, DACs, LDOs, PLLs, BGAP & amplifiers etc. 2. Experience in designing layouts for high-speed circuits is a plus. 3. Layout experience in the following technology nodes3nm, 5nm and 7nm FinFET. 4. Good team worker with multi-discipline, multi-cultural and multi-site environments 5. Strong fundamental knowledge in semiconductor device physics, layout principles, IC reliability and failure mechanisms 6. Good problem-solving skills are essential where problems are analysed upfront, identifying gaps, and providing optimum solutions 7. Knowledge in Skill/perl/tcl/Python scripting is a plus. Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise The Analog layout design engineer with experience in next generation Ultra high speed serial IO link (HSS) interface for Cognitive, ML,DL, and data center applications. The engineer needs to have knowledge in the design and development full custom analog layouts for ultra high speed 32G/50G/112G IO link interfaces. Preferred technical and professional experience Experience in 7 and 14 nm analog layout design. Working on Cutting edge technology and HSS domain . Quick learner, deep layout design knowledge, problem solving skills and good communication skills with cross teams across the Geos.

About The Role Looking for enthusiastic, motivated and self-driven engineer in area of Power Analysis and Signoff who can take care of Understanding and Defining Chip Power & Performance Targets Analyzing FSDBs for various design power scenarios and extracting the right activity windows Running Power Estimation and Analysis at block level and roll-up total power for SoC Working with Architecture, Design and Implementation teams for power optimization Running LP checks at block and full chip level, analyzing the logs/reports and deliver quality results Work closely with the FE & BE teams for overall Power Convergence and Low-Power Sign-off of the design for Tape-out Qualifications BE/ME in Electrical Engineering with 8+ years of experience in Logic Design, Synthesis and Low Power Design/Implementation for complex multi-million gate SoCs Expertise in power analysis using PT-PX/Prime Power Experience in Verdi tool for FSDB analysis Experience in power analysis using Power Artist tool is a plus Experience in industry standard tools LP checks, PTPX for power estimation etc. Strong analytical and problem-solving skills Expertise in Tcl, Perl/Python is required Inside this Business Group Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

About The Role In this position, you will be responsible for managing and working on all aspects of STA and timing closure activities of Intel SoCs in lower technology nodes. Your tasks will include but not limited to: Design and Architecture understanding, Interaction with FE/DFT/Verification teams, Clocking, Constraints development, ACIO Timing, Understanding on synchronous and asynchronous paths, Clock domain crossing issues. Understanding and debugging extraction issues, deciding timing signoff modes and corners, Design margins, Hierarchical timing including IO budgeting for partitions. Drive the designs to timing closure, interacting/supporting synthesis and APR team during timing closure cycle, timing ECOs, Timing model build, Timing signoff and quality checks. You will also be part of debug/troubleshoots for a wide variety of tasks up to and including difficult/critical design issues and proactive intervention, as required. Qualifications EducationB.Tech. or M.Tech. in Electrical/Electronics Engineering with 10-14 years' of experience.PreferenceMaster's Degree in Electrical/Electronics Engineering with VLSI/microelectronics specialization, with 10+ years of experience in STA.Key Skills: In-depth knowledge and hands-on experience with the overall silicon implementation flows and methodologies such as STA, Synthesis, Clocking is required. Good understanding and exposure of overall Timing closure cycle in SoC. Good scripting skills in TCL/Perl/Shell. Expertise in STA signoff tools (PT/ETS). Skill in Synopsys tools (PT/DC) and exposure to ICC will be an added advantage. Solid understanding of the process and design interactions as they relate to target frequency and interaction with timing paths and resulting leakage and power trade-offs. Solid technical and good communication skills. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

About The Role The Graphics hardware IP team , within the CGAI Client Compute Group and AI, is responsible for design and development of Graphics, Media and Display IPs as well as discrete Graphics SoCs GPUs, targeting both Client Device and Datacenter markets. The XSE organization is at the center of Intel's push into the discrete Graphics SoCs ARC GPUs market segment targeting next-generation applications such as High-performance computing, Deep learning / training, Cloud Graphics, Media analytics, High-end gaming. Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure highquality integration of the GPU block. Qualifications You must possess the below minimum qualifications to be initially considered for this position. Experience listed below would be obtained through relevant schoolwork, internships, jobs and/or research experience. Minimum skills and Experience: Bachelors in Electrical/Computer Engineering or related field with 9+ years of academic or industry experience. Or a Masters in the same fields with 8+ Years of academic or industry experience. Your experience should be in the following: Experience across all the DFT features such as TAP/JTAG, SSN, Scan/ATPG or Array DFT (MBIST/PBIST), Silicon bring-up, DFT micro-architecture. SoC IP DFT design integration or verification. EDA tools such as ATPG tools, Mentor Tessent shell, VCS simulation and/or debug tools, Synopsys tool. Silicon enabling debug or test pattern development experience Structural design flows, including timing, routing, placement or clocking analysis SOC architecture, RTL coding and post silicon debug. Experience in handling DFT timings constraints. Additionally: RTL insertion and integration will be a plus. Knowledge of UVM and OVM will be added advantage. Knowledge of system verilog is must. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

In your new role you will: Contribute to the implementation of highly complex automotive SoC designs in a multi-site organization covering all aspects of Physical Design. Work independently in different phases of the RTL 2GDS flow with focus on Synthesis and Constraining for efficient Timing Closure, Equivalence check, PnR closure, IR/EM analysis and fixing along with physical checks cleanup sign-off Work with industry standard tools for physical design and signoff with good understanding of scripting languages (shell, perl, tcl) and Make flow. Focus on PPA , define the Partition shapes, pins and feedthrough along with IP integration guidelines are followed (reviewed along with IP owners) to suit the requirements. Analyze and solve problems of high complexity using your global expert network Drive the PnR closure of multimillion gate designs in lower technology nodes, perform SoC level IR/EM analysis, debugging and fixing. Running SoC level Physical verification, debugging and fixing including Chip finishing, metal fill, Sealring and Tapeout checks Be a member of an expert network and drive innovation, methodology for the RTL to GDS2 development cycle of next generation automotive SoCs. Your Profile You are best equipped for this task if you have: A degree in Electrical Engineering, Microelectronics or a similar field. At least 6 of experience in Physical Design of highly complex SoCs. Experience in RTL coding , IP issues and handling is plus. Programming skills and knowledge in scripting languages like Tcl, Perl or Python. Experience in working as a member of SoC design teams with high cost and quality awareness. Fluent English language skills with German being an added plus. Understanding of industry standard tools for physical design and signoff Be a quick learner and team player while taking and acting on responsibilities

Urgent Hiring for Lead DFT Design Engineer Experience - 5+ Years to 15 Years CTC - Upto 80LPA Location - Bangalore, Hyderabad, India Roles and Responsibilities Experience with owning chip level DFT and Post Silicon debug / analysis Understanding of DFT architectures like JTAG, Scan Compression Techniques (XOR, Adaptive, OP-MISR etc.), scan chain insertion and verification. Must have experience generating scan patterns and coverage statistics for various fault models like stuck at(Nominal and VBOX), IDDQ, Transition faults, JTAG BSDL, pattern generation for Memories(E-fuse etc.). Experience debugging tester failures of scan patterns, diagnosis and pattern re-generation. Understanding generation of functional patterns for ATE Knowledge of at least any one of an industry standard DFT tools (Cadence Modus, Synopsys Tetramax, Mentor Tessent Tools, etc) Design experience in MBIST / LBIST is an added advantage. Good understanding of constraints development for Physical Design Implementation / Static Timing Analysis. Preferred Skills/ Experience Experience with TCL / Perl is preferred. Understanding of IC design with Analog circuits and its design cycles is an added advantage. Effective communication skills to interact with all stakeholders. Team and People Skills: The candidate should have good people skills to work closely with the systems, analog, layout and test team Must be highly focused and remain committed to obtaining closure on project goals If interested or have any reference then call us at 9560379526 or email us at bkirad@reqres.com

Experience with STA using Primetime and PTPX required Proficient in constraint generation. Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl scripting is required Strong problem solving and ASIC development/debugging skills. Experience with CPU micro-architecture and their critical path. Low power implementation techniques experience. High speed CPU implementation. Place and route tool experience. Constraint management tool and Verilog coding experience Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

In this position, the candidate will be responsible for design of soft IP cores for Intel's next generation chips (including SOCs) for the different market segments.The engineer will be responsible for the execution and quality of at least 2 IPs and will sign off all design checks and interact with SOC for all integration issues Qualifications Qualification : Master of Science (or a Master of Technology) degree in Electrical Engineering with more than 12 years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than 14 years of relevant industry experience. Experience : Relevant ASIC design/validation experience in front end processes including RTL development, functional and performance verification Expertise in design, development and integration of design blocks (IP) for system-on-chip (SoC) componentsExpertise in verilog and system verilog based logic design Experience in all design tools like linting, DC, CDC, LEC Experience in one/more of the following areas PCI_Express, USB, SATA, SDIO,MIPI and /or AMBA standards (OCP, AXI, AHB etc..) Knowledge of SVAKnowledge of RAS domain is a bonusKnowledge of considerations for performance, power and cost optimization is desirable

About The Role Seize the opportunity to work with the team responsible for RTL logic design and microarchitecture of chipsets for PCs millions of people around the world will use. The Chipsets Logic Team, CLIPS is responsible for developing soft IPs, subsystems and gaskets for client and server chipsets.Candidate will be responsible for logic design and development, responsibilities including but not limited to: Develops the logic design, register transfer level (RTL) coding, and simulation for an IP design. Participates in the definition of microarchitecture features of the block being designed. Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for meet the design specification requirements. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Follows secure development practices to address the security threat model and security objects within the design. Supports SOC to integrate and validate the IP on need basis. Drives quality assurance compliance for smooth IPSoC handoff. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Qualifications : BE/ME/Btech/Mtech in computer science eng or electronics and Communications. The candidate must possess a minimum of Bachelor Degree in Electronics Engineering, Computer Engineering, Computer Science or equivalent. The candidate should have successful track record of hardware development experience and demonstrated technical leadership skills. The candidate must have demonstrated the ability to solve highly complex technical problems with excellent communication skills. The candidate must also have demonstrated strong ethical standards. Must also be able to perform in a highly ambiguous and dynamic business environment. Skills : Relevant experience with skills in ASIC IP design flows, RTL coding and Globals (Clocking, Boot/Reset/Fabrics, DfD, Fuse, etc) with experience in CDC, linting, spyglass, micro-architecture. Experience in subsystem design and IO protocols such as AMBA, USB, PCIe, UCIe, UFS, SATA, UART, SPI, I2C, I3C etc is a plus. Other technical requirements: 3 to 8 years of relevant pre-silicon logic design experience in ASIC domain. Experienced with various tools and methodologies including but not limited toSystem Verilog, Python/Perl/Shell scripting, Synopsys tools, RTL model build, design-for-test, design-for-verification. Experienced in EDA tools & flows such as Spyglass VCLINT, VCLP, VC-CDC, SG-DFT, Design Complier, Calibre, Fishtail, FEV, ATPG etc. Experienced in developing micro-architecture based on High Level Architecture specifications. Experienced in VLSI or Structural and Physical design flow and methodology. Experienced in Power-aware design and reviewing validation flows. Strong Chipset or CPU level understanding required on power consumption, power estimation and low power design methods. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intels offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.

We are looking for highly experienced Senior ASIC Engineers to lead and contribute to complex ASIC projects. This role requires expertise in advanced physical design, verification, and tapeout processes. The ideal candidate will have a proven track record of delivering high-quality ASIC designs in advanced technology nodes. Responsibilities: Lead and execute complex physical design implementations, including block-level low power aware floorplanning, placement, CTS, routing, RC extraction, STA, IR/EM analysis, and DRC/LVS/ERC. Manage hierarchical physical verification and signoff closures. Develop and implement advanced UVM verification environments for IP and full-chip verification. Verify complex high-speed protocols (SERDES, UNIPRO, PCIE, UFS, DDR). Drive STA closure at block and chip levels. Manage and contribute to tapeout activities, with experience in multiple tapeouts. Work with advanced process technology nodes (7nm, 6nm, 5nm). Utilize Cadence (Innovus, Tempus) and Mentor Caliber tools effectively. Guide and mentor junior engineers. Collaborate with global teams to ensure project success. Contribute to project planning, scheduling, and risk management. Develop and maintain comprehensive documentation. Required Skills: Extensive experience in physical design and verification. Expertise in advanced UVM verification methodologies. Strong understanding of high-speed protocols. Proven track record of successful tapeouts. Proficiency in Cadence and Mentor tools. Strong analytical and problem-solving skills. Excellent communication and leadership skills. Experience with advanced process technology nodes. Knowledge of digital electronics and microprocessors. Experience: 5+ years of relevant experience, with a preference for 7+ years.

Job Title: ASIC Engineer (Entry to Mid-Level) Job Description: We are seeking motivated ASIC Engineers to join our dynamic team. This role encompasses a range of responsibilities from foundational verification to physical design and synthesis. The ideal candidate will have a solid understanding of Verilog and SystemVerilog, with a keen interest in expanding their knowledge in ASIC design and verification. Responsibilities: Develop and verify ASIC designs using Verilog, SystemVerilog, and UVM methodologies. Perform RTL design and SOCC verification. Execute RTL synthesis to optimize performance, power, and area. Develop and implement timing constraints for functional and test modes. Participate in physical design activities, including RTL2GDS implementation (Synthesis, Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification). Debug complex designs and high-speed interfaces (DDR, PCIe, ONFI). Utilize lab equipment like Logic Analyzers and Oscilloscopes for debugging. Develop and maintain test benches and verification environments. Write and debug scripts in Tcl/Tk/Perl. Work with Cadence tools (Innovus, Genus, Tempus) and Mentor Caliber. Collaborate with cross-functional teams to achieve project milestones. Contribute to the development and improvement of ASIC design and verification methodologies. Required Skills: Proficiency in Verilog, SystemVerilog, and UVM. Strong debugging skills. Experience in RTL design and SOCC verification. Knowledge of ASIC design and verification flows. Understanding of physical design concepts (RTL2GDS). Experience with synthesis and STA. Ability to work with Cadence and Mentor tools. Good communication and teamwork skills. Scripting experience (Tcl/Tk/Perl) is a plus. Experience: 0-7 years of relevant experience.

Working experience of Physical Design Implementation Working experience of Physical Verification, Timing Signoff. Good attitude to learn and deliver. Work from office only. Lower technology node experience. Experience in writing scripts and automation. Working knowledge of Low Power ASIC

* Perform Sub system level floor planning, placement, and routing for high-performance microprocessor design. * Collaborate with cross-functional teams to achieve design goals. * Close the design to meet timing, power, and area requirements. * Implement engineering change orders (ECOs) to rectify functional bugs and timing issues. * Ensure the quality and efficiency of the RTL to GDS2 implementation process. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8+ years of industry experience Good knowledge and hands on experience in physical design , timing and methodology which include logic synthesis, placement, clock tree synthesis, routing , post route closure. Should be knowledgeable in physical verification ( LVS,DRC. etc) ,Noise analysis, Power analysis and electro migration . Good knowledge and hands on experience in static timing analysis (closing timing at chip level) good understanding of timing constraints . Should have experience in handling asynchronous timing, multiple corner timing closure. Preferred technical and professional experience Automation skills in PYTHON, PERL ,SKILL and/or TCL

About The Role In this role, you will be responsible for Timing methodology definition and closure of designs using industry standard tools for chiplet designs for custom and domain specific products. The chiplets will be leveraged to enable modular design and support multiple products. As part of this team, the candidate will work with leading edge technologies and solutions across multiple domains including SoC multi-die implementations (2.5 and 3D), power delivery, leading edge memory technologies, innovate thermal solutions, on die clocking, and fabrics. The team will also look at options to enhance product power/performance/area/cost thru improved tools and methodologies. The successful candidate would be expected to:Responsibilities1. Drive PV convergence/signoff, including static timing, ERC checks, ECO flows and power analysis2. Defining clock frequencies, PV guard-banding, signoff PV corners, ERC checks, Clock/Reset domain crossing design constraints3. Develop and recommend design methodologies to enable more efficient and faster design convergence4. Scripting in an interpreted language (TCL, py)5. Ability to work independently and at various levels of abstraction6. Strong analytical ability and problem solving skills7. Ability to work effectively with both internal and external teams/customers is expected.8. Strong written and verbal communication skills9. Ability to mentor other engineers and technically guide them."" Qualifications Minimum Qualifications:1. Bachelor/Master degree in CS, CE or EE or equivalent experience2. 10+ years of Physical design experience with a strong understanding of digital circuits and proficiency in static timing analysis (STA) tools like PrimeTime or Innovus.3. Experience with signoff corner selection, PV guard-banding, PV convergence, including static timing and power analysis4. Strong experience in SoC and ASIC design flows on taped out designs5. Expertise in timing closure at block/chip level and ECO flows6. Experience with scripting in an interpreted languagePreferred Qualifications:1. Experience with full chip integration, die-to-die and package integration level timing signoff 2. Hands-on experience with synthesis, block and chip level implementation with industry standard PnR flows and tools 3. Strong experience in CPU and GPU design flows on taped out designs4. Design tools and methods development 5. Capable of working in a high performing team to deliver the results required from the organization. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world. Other Locations IN, Hyderabad Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

About The Role Architects, develops and integrates layered Verification IPs, testbenches, testplans and test suite to validate the integrity and quality of Verification IPs and compliance with standards and SoC architecture & micro-architecture requirements. Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and conform to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, micro-architects, full chip architects, RTL developers, post-silicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from post-silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience. Related technical experience should be in/withSilicon Design and/or Validation/Verification. Preferred Qualifications: Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. Proficiency in UVM/SV constrained-random coverage based design verification. UVM/SV Verification IP architecture, development and validation experience. Robust understanding of fundamental principles of cache coherency in multi-processor SOCs, and experience with layered protocols - transaction layer, data link layer, and PHY layer. Experience with one or more scripting languages to facilitate automation. Strong debug skills and self-reliance in taking an issue to closure with internal and external partners. Takes ownership of assigned tasks. Keen problem solver, strong communicator, quick learner, effective team player and open to learning and teaching new and more efficient validation execution techniques to meet time-to-market. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation testbenches and test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world.

About The Role Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the AI SOC / CPU IP block for integration in full chip designs. Participates actively in the definition of architecture and microarchitecture features of the AI SOC/CPU being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Documents micro architectural specs (MAS) of the CPU features being designed. Supports SoC customers to ensure high quality integration of the CPU block. Qualifications Minimum Qualifications: Bachelor's with 13+ Years and Master's with 10+ Years of relevant experience in the semiconductor industry. 10+ years of experience in/withVerilog and system Verilog, synthesizable RTL Modern design techniques and energy-efficient/low power logic design and power analysis. 5+ years of experience in/withHaving achieved multiple tape-outs reaching production with first pass silicon. Hands on experience with FPGA emulation, silicon bring-up, characterization and debug. Inside this Business Group Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

About The Role You will be part of ACE India, in the P- Core design team driving Intel's latest CPU's in the latest process technology. In this position, you will be responsible for timing analysis and convergence of complex partitions. Your responsibilities will include but not limited to: 1. Responsible for timing execution and convergence including setup and hold for over 5GHz Freq and low-power digital designs. 2. Deep understanding of Static timing analysis concepts 3. Timing Convergence across all HVM targets 4. Closely work with SD, Integration and Floor plan teams Qualifications Qualifications You must possess a master's degree in electrical or Electronics Engineering with at least 8 or more years of experience in related field or a bachelor's degree with at least 10 years of experience. Technical Expertise in Static Timing Analysis is preferred. Should have minimum of 2 years experience in leading the Team of at least 3-4 people Preferred additional skills Experience of handle complex core design, high-speed designs Timing signoff flows/tools experience both/either Synopsys/Cadence tools Very good knowledge on Timing tools, flows and methodology Ability to handle new feature feasibility studies SD flow knowledge would be plus Familiarity with Verilog/VHDL Tcl, Perl, Python scripting Strong verbal and written communication skills Inside this Business Group The Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core „¢, and critical IPs that power Intel's leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies.

About The Role Come join Intel's highly regarded Devices Development Group, responsible for creating Client SOCs. We envision the future of computing and design for the next generation of laptop and desktop computers. We are looking for a SoC Physical Design Engineer, who is ready to research, design, develop, and test lead Intel designs as we reimagine how to build SoCs at Intel and in the semiconductor industry. Our bold purpose as a company is to create world-changing technology that enriches the lives of every person on earth and this role is instrumental in furthering our mission to shape the future of technology. Your responsibilities may include but not be limited to: Performing physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Physical Synthesis, Floor planning, Place and Route, Clock Tree Synthesis with Synopsys and/or Cadence EDA tools. Multiple Power Domain analysis and handling using standard Power Formats UPF or CPF. Verification and Signoff including Formal Equivalence Verification, Static Timing Analysis, Reliability Verification, Static and Dynamic power integrity, Layout Verification, Electrical rule checking, Noise analysis and Structural Design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Participating in the development and improvement of physical design methodologies and flow automation. Driving performance optimization, including co-optimization, work with process teams, to create best-in-class designs. The ideal candidate should exhibit behavioral traits that indicate: Self-motivator with strong problem-solving skills. Excellent interpersonal skills, including written, verbal, and presentation communications. Attention to detail and organizational skills. Ability to work as part of a team and collaborate in a high-paced atmosphere. Qualifications BS/BTech degree with 12 years of experience, or MS/MTech degree with 10 years of experience, in Electronics Computer Engineering, or a related field. Preferred Qualifications: At least 10+ years of experience in physical design using industry EDA tools. Experience in Python/Perl/TCL programming languages Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

About The Role Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications: 2+ years' experience on AMBA protocols. Strong background and experience on Coherent Protocols (IDI, CHI). Strong coding experience in perl, python (one of the programming languages). Strong in coherency architecture. Preferred Qualifications: Bringing up coherent protocols from 0 to1. 2 + years of Experience on Network on Chip verification. 2+ years of experience developing protocol checkers, bridge checkers, VIP integration, Configurable IP verification. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world.

About The Role Come join Intel's highly regarded Devices Development Group, responsible for creating Client SOCs. We envision the future of computing and design for the next generation of laptop and desktop computers. We are looking for a SoC Physical Design Engineer, who is ready to research, design, develop, and test lead Intel designs as we reimagine how to build SoCs at Intel and in the semiconductor industry. Our bold purpose as a company is to create world-changing technology that enriches the lives of every person on earth and this role is instrumental in furthering our mission to shape the future of technology. Your responsibilities may include but not be limited to: Performing physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Physical Synthesis, Floor planning, Place and Route, Clock Tree Synthesis with Synopsys and/or Cadence EDA tools. Multiple Power Domain analysis and handling using standard Power Formats UPF or CPF. Verification and Signoff including Formal Equivalence Verification, Static Timing Analysis, Reliability Verification, Static and Dynamic power integrity, Layout Verification, Electrical rule checking, Noise analysis and Structural Design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Participating in the development and improvement of physical design methodologies and flow automation. Driving performance optimization, including co-optimization, work with process teams, to create best-in-class designs. The ideal candidate should exhibit behavioral traits that indicate: Self-motivator with strong problem-solving skills. Excellent interpersonal skills, including written, verbal, and presentation communications. Attention to detail and organizational skills. Ability to work as part of a team and collaborate in a high-paced atmosphere. Qualifications BS/BTech degree with 8 years of experience, or MS/MTech degree with 6 years of experience, in Electronics Computer Engineering, or a related field. Preferred Qualifications: At least 8+ years of experience in physical design using industry EDA tools. Experience in Python/Perl/TCL programming languages Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

About The Role About The Role : Come join Intel's highly regarded Devices Development Group, responsible for creating Client SOCs. We envision the future of computing and design for the next generation of laptop and desktop computers.We are seeking a highly skilled and motivated STA (Static Timing Analysis) Engineer to join our team specializing in timing analysis for cutting-edge and complex SoC projects. This role offers a unique opportunity to work on high-level designs and collaborate with multidisciplinary teams in a dynamic and challenging environment. Your responsibilities may include but not be limited to: STA setup, convergence, reviews and sign-off for Multi-Mode and Multi-corner Multi voltage domain designs. Timing analysis and Timing Closure at Partition/Sub-system/FC level. Develops and defines methodologies to ensure highest quality of timing models that enable the physical design team to operate efficiently. Defines the right process, voltage, and temperature (PVT) conditions to be used for timing analysis for a given design based on the product plans such as operating conditions and binning. Collaborates with architecture, clocking design, and logic design teams to deliver flow development for chip integration and validates high performance low power clock network guidelines. Familiar with Constraint Generation, development and clean up. Good at Timing ECO Implementation strategy development/convergence. Should have an experience in enabling the Tweaker/Prime Time based ECO flows. Work on Automation scripts with in STA tools for Methodology development. Familiar with digital design Implementation RTL to GDSII Synopsys/Cadence tools. Familiar with LVF/POCV variation formats and understanding of deep sub-micron topics. Participate in and lead cross-functional meetings to drive project progress and resolve timing-related challenges. Act as a liaison between timing analysis and physical design teams, ensuring alignment and high-quality deliverables. The ideal candidate should exhibit behavioral traits that indicate: Self-motivator with strong problem-solving skills. Excellent interpersonal skills, including written, verbal, and presentation communications. Attention to detail and organizational skills. Ability to work as part of a team and collaborate in a high-paced atmosphere. Qualifications Educational Qualifications: BS/BTech degree with 8 years of experience, or MS/MTech degree with 6 years of experience in Electronics/VLSI/Computer Science or a related field. Preferred Qualification: At least 8+ years of experience in STA Timing Analysis using industry EDA tools. Experience in Python/Perl/TCL programming languages. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

As a DFT Engineer, you will be responsible for developing and implementing Design for Test methodologies for complex VLSI designs. You will ensure the testability and manufacturability of our products by working closely with design, verification, and physical design teams. Responsibilities: Develop and implement DFT architectures and strategies for complex SoC designs. Insert and verify DFT features such as scan chains, Built-In Self-Test (BIST) for memory and logic, and boundary scan (IEEE 1149.1/1149.6). Perform ATPG (Automatic Test Pattern Generation) and analyze coverage metrics to ensure high fault coverage. Collaborate with RTL designers to ensure seamless integration of DFT features into the design. Debug and resolve test-related issues in simulation, silicon validation, and production. Work closely with the physical design team to implement scan and clock constraints for timing closure. Optimize test time, power, and cost without compromising coverage and quality. Participate in silicon bring-up and post-silicon validation activities. Generate and maintain DFT documentation, including test plans, methodologies, and results. Requirements: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 4 to 10 years of experience in DFT for VLSI designs. Strong knowledge of DFT methodologies, including ATPG/MBIST/Scan Insertion Verilog/ System Verilog and scripting languages (Python, TCL, Perl). Solid understanding of STA concepts and constraints related to DFT. Experience in debugging silicon and ATE test patterns. Excellent problem-solving skills and ability to work in a collaborative environment. Familiarity with fault diagnosis and yield improvement methodologies. Exposure to advanced nodes (7nm, 5nm, or below) and FinFET technologies. Knowledge of machine learning or AI techniques for test optimization.