5 Sta Constraints Jobs

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9.0 - 11.0 years

0 Lacs

bengaluru, karnataka, india

On-site

Job Requirements 9-10 years experience with Bachelor's degree in Electronics Engineering or equivalent Good experience in Physical Design with innovus tool Hands-on experience in developing and modifying PD-flow/EDA-tools scripts/recipes using TCL/SHELL/PYTHON programming languages. Experience in developing PD metrics dashboard scripts for QOR tracking is a plus Experience in modifying STA constraints to check timing closure feasibility Experience in various clock implementation strategies (Multi-point CTS, Flex-H, Custom-CTS) for meeting block level and full chip level latency and skew targets Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5/3nm Strong leadership skills to ...

Posted 2 days ago

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4.0 - 9.0 years

0 - 0 Lacs

hyderabad, bengaluru

Work from Office

Semiconductor STA Design Engineer Desired experience 3-10 Years TSMC Certification Yes/No Role You will be responsible for analyzing digital and analog circuits used in the development of memory products. Responsibilities • Doing STD cells characterization work (max up to 40% of time) , Static timing analysis (60%) • Writing constraints , analyzing the STA reports • Performing verification processes with modeling and simulation using industry standard simulators • Able to characterize basic STD Cells Writing ARC for STD cell char (using primeLib , Silicon smart) QA check Circuit understanding block wise , Full chip level Static timing Analysis of DRAM block wise , top level analysis , cell l...

Posted 2 weeks ago

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3.0 - 7.0 years

0 Lacs

hyderabad, telangana

On-site

As a Design Engineer at Micron Technology, Inc., you play a crucial role in the design and analysis of digital and analog circuits for cutting-edge memory products. You are part of a dynamic team dedicated to creating innovative silicon-to-systems solutions. Collaboration is key as you work closely with various design and verification teams globally. Your efforts support Product Engineering, Test, Probe, Process Integration, Assembly, and Marketing to ensure proactive product design. Your responsibilities include: - Understanding DRAM building blocks for circuit design - Conducting Static Timing Analysis - Writing STA constraints - Performing STA Analysis - Providing feedback on setup/hold f...

Posted 1 month ago

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3.0 - 10.0 years

0 Lacs

karnataka

On-site

As a DFT Verification Engineer, your role involves developing and executing pre-silicon verification test plans for DFT features of the chip. This includes verifying DFT design blocks and subsystems using complex SV or C++ verification environments. You will also be responsible for building test bench components, composing tests, assertions, checkers, and validation vectors to ensure verification completeness. Additionally, debugging regression test failures and addressing areas of concern to meet design quality objectives are key responsibilities. Key Responsibilities: - Develop and execute pre-silicon verification test plans for DFT features of the chip - Verify DFT design blocks and subsy...

Posted 1 month ago

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2.0 - 6.0 years

0 Lacs

karnataka

On-site

The ideal candidate for this role should possess a Bachelor's degree or equivalent practical experience along with a minimum of 2 years of experience in developing and maintaining STA constraints and scripts. It is essential to have prior experience working collaboratively in a team of DFT engineers, specifically with Register-Transfer Level (RTL) and Physical Designer Engineers. Preferred qualifications for this position include a Bachelor's or Master's degree in Electrical Engineering or Computer Science, or relevant practical experience. The candidate should have at least 6 years of experience in Static Timing Analysis with exposure to mixed signal design. Proficiency in flow methodology ...

Posted 1 month ago

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