7 Sta Constraints Jobs

As a Design Engineer at Micron Technology, Inc., you will play a crucial role in the design and analysis of digital and analog circuits that are utilized in the development of cutting-edge memory products. You will be part of a dynamic team dedicated to creating innovative silicon-to-systems solutions, spanning from technology development and advanced memory designs to product development, systems design, and validation, all aimed at delivering world-class memory solutions. Collaboration will be a key aspect of your role as you work closely with various design and verification teams across the globe. Your efforts will support groups such as Product Engineering, Test, Probe, Process Integrati...

Job Description You are required to be an experienced DFT Engineer with a strong background in Scan, ATPG, and MBIST for SoC/ASIC designs. Your main responsibilities will include implementation, pattern generation, and verification of DFT features to ensure high test coverage and silicon readiness. Key Responsibilities - Implement and verify Scan, ATPG, and MBIST for complex SoCs. - Perform pattern generation, coverage analysis, and debug. - Integrate and validate MBIST with appropriate memory test algorithms. - Coordinate with RTL and Physical Design teams for smooth DFT integration and signoff. - Develop automation scripts to streamline DFT flows. Qualification Required - Minimum 4 years o...

Job Requirements 9-10 years experience with Bachelor's degree in Electronics Engineering or equivalent Good experience in Physical Design with innovus tool Hands-on experience in developing and modifying PD-flow/EDA-tools scripts/recipes using TCL/SHELL/PYTHON programming languages. Experience in developing PD metrics dashboard scripts for QOR tracking is a plus Experience in modifying STA constraints to check timing closure feasibility Experience in various clock implementation strategies (Multi-point CTS, Flex-H, Custom-CTS) for meeting block level and full chip level latency and skew targets Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5/3nm Strong leadership skills to ...

Semiconductor STA Design Engineer Desired experience 3-10 Years TSMC Certification Yes/No Role You will be responsible for analyzing digital and analog circuits used in the development of memory products. Responsibilities • Doing STD cells characterization work (max up to 40% of time) , Static timing analysis (60%) • Writing constraints , analyzing the STA reports • Performing verification processes with modeling and simulation using industry standard simulators • Able to characterize basic STD Cells Writing ARC for STD cell char (using primeLib , Silicon smart) QA check Circuit understanding block wise , Full chip level Static timing Analysis of DRAM block wise , top level analysis , cell l...

As a Design Engineer at Micron Technology, Inc., you play a crucial role in the design and analysis of digital and analog circuits for cutting-edge memory products. You are part of a dynamic team dedicated to creating innovative silicon-to-systems solutions. Collaboration is key as you work closely with various design and verification teams globally. Your efforts support Product Engineering, Test, Probe, Process Integration, Assembly, and Marketing to ensure proactive product design. Your responsibilities include: - Understanding DRAM building blocks for circuit design - Conducting Static Timing Analysis - Writing STA constraints - Performing STA Analysis - Providing feedback on setup/hold f...

As a DFT Verification Engineer, your role involves developing and executing pre-silicon verification test plans for DFT features of the chip. This includes verifying DFT design blocks and subsystems using complex SV or C++ verification environments. You will also be responsible for building test bench components, composing tests, assertions, checkers, and validation vectors to ensure verification completeness. Additionally, debugging regression test failures and addressing areas of concern to meet design quality objectives are key responsibilities. Key Responsibilities: - Develop and execute pre-silicon verification test plans for DFT features of the chip - Verify DFT design blocks and subsy...

The ideal candidate for this role should possess a Bachelor's degree or equivalent practical experience along with a minimum of 2 years of experience in developing and maintaining STA constraints and scripts. It is essential to have prior experience working collaboratively in a team of DFT engineers, specifically with Register-Transfer Level (RTL) and Physical Designer Engineers. Preferred qualifications for this position include a Bachelor's or Master's degree in Electrical Engineering or Computer Science, or relevant practical experience. The candidate should have at least 6 years of experience in Static Timing Analysis with exposure to mixed signal design. Proficiency in flow methodology ...