Physical Design Engineer, Sr/Lead/Staff Qualcomm

4.0 - 10.0 years

0 Lacs

hyderabad, telangana

On-site

As a Hardware Engineer at Qualcomm India Private Limited, you will be responsible for the physical design aspects of ASICs, including Place and Route (PnR) flow and methodology. Your key responsibilities will include: - Executing complete PD ownership from netlist to GDS2, encompassing HM level PV, LEC, low-power checks, PDN, and STA closure - Implementing Voltage Islands and low power methodologies, flows, and implementation - Debugging Congestion and Clock Tree Synthesis (CTS) issues - Utilizing PnR tools such as Innovus/Fusion compiler and flow - Familiarity with Sign-off methodologies and tools (PV/PDN/STA/FV/CLP/Scan-DRC(tk)) - Enhancing existing methodologies and flows - Proficiency in...

Posted 1 month ago

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STA Timing Engineer Advanced Micro Devices (AMD)

11.0 - 15.0 years

11 - 15 Lacs

bengaluru, karnataka, india

On-site

Lead and develop timing methodologies, establish SDC constraints, and automate processes for special timing checks, ensuring design convergence and managing ECOs effectively. Perform static timing analysis setup and sign-off for multi-corner, multi-voltage processes to align with PPA targets, initially at the hierarchical level and subsequently at the top-level, reviewing the timing arcs for the .lib generation. Collaborate closely with RTL, DFT, and IP teams to ensure smooth integration and address physical design concerns affecting scan shift and scan capture modes for DFT. Identify opportunities to optimize clock skew and insertion delay across various corners and modes. Evaluate the cloc...

Posted 2 months ago

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Lead Physical Designer HCLTech

7.0 - 11.0 years

0 Lacs

karnataka

On-site

As a Physical Design Engineer at HCLTech, you will be responsible for performing Timing analysis, timing convergence, SI/Noise analysis, and ensuring Signoff quality in the designs. With a minimum of 7 years of experience, you will demonstrate proficiency in handling multi-voltage scenarios design and STA closure on Low power designs. Your familiarity with industry standard EDA tools like Primetime will be essential for success in this role. Hands-on experience in Physical Design implementation will be a valuable asset. You will be expected to utilize your skills in scripting languages such as Perl and Tcl for automation purposes. Knowledge of 16/14/10/7/5nm nodes, along with an understandin...

Posted 2 months ago

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ASIC Design Engineer, RTL, Silicon Google

3.0 - 7.0 years

0 Lacs

karnataka

On-site

As an Electrical Engineer or Computer Science professional with a Bachelor's degree and 3 years of experience in design, multi-power domains with clocking, and SoCs with silicon, you will have the opportunity to contribute to the innovation behind Google's direct-to-consumer products. Your expertise will be crucial in shaping the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Your responsibilities will include defining the microarchitecture of IPs, Subsystems, or SOCs, working with cross-functional teams to ensure quality, schedule compliance, and PPA optimized design. You will collaborate with Verification, Design for Test, Physica...

Posted 3 months ago

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