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Cadence Design Systems logo

Sr Principal Software Engineer

10 - 18 years

2 - 11 Lacs

Bengaluru / Bangalore, Karnataka, India

Posted:1 day ago| Platform: Foundit logo

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Skills Required

Rtl Design VHDL FPGA Architecture (

Work Mode

On-site

Job Type

Full Time

Job Description

Job Summary: We are looking for 14+ years of experience having the following skillset: Strong RTL design fundamentals using HDLs like VHDL/Verilog/System verilog Strong understanding of AMD (Xilinx) ultrascale, versal FPGAs architecture and use of vivado for FPGA place and route. Constraints definitions for FPGAs. Doing Static Timing Analysis. Familiarity with FPGA prototyping or emulation is a plus. Passionate to learn and explore new technologies and demonstrates good analysis and problem-solving skills. Good written and verbal communication skills, should be a quick learner and a team player.

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