You are an experienced and dynamic professional with over 15 years of experience in IP design or management, particularly in foundational IP/Interface IP across multiple process technologies up to 3nm. Your background includes significant experience in IP program management, working with cross-functional teams, and engaging with external SOC customers. You excel in presenting status updates to senior management and possess knowledge in SOC design and architecture, product qualification, signal and power integrity, and package design. You hold a BS or MS degree in Electrical or Computer Engineering. What You ll Be Doing: Leading and managing IP design and development projects from initiation through to delivery. Coordinating with cross-functional teams to ensure project milestones and deliverables are met on time. Engaging with external SOC customers to understand their requirements and ensure their needs are met. Presenting project status updates and reports to senior management and stakeholders. Ensuring adherence to quality standards and regulatory requirements throughout the project lifecycle. Driving continuous improvement initiatives within the program management processes. The Impact You Will Have: Ensuring the successful delivery of high-quality IP products that meet customer expectations. Contributing to the strategic goals of Synopsys by effectively managing complex projects. Enhancing cross-functional collaboration and communication within the organization. Driving innovation in IP design and development through effective program management. Building strong relationships with external SOC customers, enhancing customer satisfaction and loyalty. Improving the efficiency and effectiveness of program management processes and practices. What You ll Need: 15+ years of experience in IP design or management in multiple process technologies up to 3nm. Experience in IP program management or working with cross-functional teams. Experience in working with external SOC customers and presenting to senior management. Knowledge of SOC design and architecture, product qualification, signal and power integrity, and package design. BS or MS degree in Electrical or Computer Engineering

Collaborate with cross-functional teams to drive product success. Develop and execute product engineering strategies. Serve as the technical interface between teams. Engage with sales and pre-sales teams to align product goals. Build and manage time plans and schedules for product development. Ensure seamless communication and coordination across different levels of the organization. The Impact You Will Have: Drive innovation in VLSI product engineering, influencing the development of cutting-edge technology. Enhance product quality and performance through strategic engineering initiatives. Foster collaboration and knowledge sharing across cross-functional teams. Contribute to the successful execution of complex projects, meeting organizational goals. Enhance customer satisfaction by delivering high-quality, reliable products. Support the growth and development of the Synopsys product portfolio. What You ll Need: Minimum 8 years of experience in VLSI product engineering. Exposure to analog and digital SOC design flows and methodologies. Experience in RTL Development, RTL Verification, and RTL to GDS flow. Proven track record of working on different technology nodes and driving product innovation. Strong customer-centric approach with the ability to manage multiple projects. Who You Are: Excellent communicator with strong written and verbal skills. Adept at interfacing with various organizational levels. Proficient in database management and ensuring data cleanliness. Knowledgeable about industry trends and emerging technologies in VLSI. Motivated and experienced professional looking for a new challenge

Design and develop software for interface IP systems Perform Device level and System level, validation and debug, in post-silicon Software Development for new validation methodologies Customer interface to capture requirement and post release support Maximize software productivity and faster time to knowledge Qualifications: Qualification: B.Tech in ECE/CS or equivalent with 4+ year of relevant experience ECE background with experience is software is preferred Skills: Excellent programming and testing skills using C/C++ Experience with embedded or resource-constrained environments Development experience on Unix, Linux and Windows Ability to pick up new flow, learn on the Job MATLAB & PYTHON programming exposure is plus Excellent verbal and written communication skill

* Collaborate with cross-function al teams to develop and implement layout designs for analog and mixed-signal (A&MS) integrated circuits. * Create and optimize layout designs using industry-stand ard EDA tools. * Perform physical verification and design rule checks to ensure design integrity and manufacturabil ity. * Participate in design reviews and provide feedback to improve design quality. * Work closely with circuit designers to understand design specifications and constraints. * Contribute to the development and enhancement of layout design methodologies and best practices. * Stay updated with the latest industry trends and advancements in A&MS layout design. The Impact You Will Have: * Ensure the delivery of high-quality layout designs for PVT Sensor IP development, integral to SOC subsystems. * Enhance the manufacturabil ity and reliability of our silicon lifecycle monitoring solutions. * Drive innovation in layout design methodologies and best practices. * Collaborate effectively with circuit designers to meet design specifications and constraints. * Contribute to the overall success of the rapidly expanding PVT IP group. * Support Synopsys leadership in the market for process, voltage, temperature, current, and droop sensors. What You ll Need: * Bachelor s or master s degree in electrical engineering or a related field. * 5+ years of experience in A&MS layout design for integrated circuits. * Proficiency in industry-stand ard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler. * Exceptional knowledge of layout design methods, techniques, and methodologies. * Experience with physical verification tools, such as Calibre or Assura. * Understanding of semiconductor process technologies and their impact on layout design. * Excellent problem-solvin g and systematic skills. * Ability to work effectively in a team-oriented environment. * Good communication and interpersonal skills.

An experienced Verification Engineer who is passionate about technology and innovation. You are a problem-solver at heart with a strong foundation in digital design concepts and hands-on experience in programming with C++ and HDL languages. You thrive in collaborative environments and are comfortable taking on individual contributor or tech-lead roles. You are eager to work on cutting-edge technology, particularly in the field of emulation mode development and deployment for Zebu. Your technical expertise is complemented by excellent communication skills and a team-oriented mindset. What You ll Be Doing: * Developing and deploying emulation models for Zebu, focusing on bus protocols like PCIe, USB, CSI, and DSI. * Implementing designs in C++, RTL, and SystemVerilog-DPIs. * Collaborating with cross-functional teams to ensure seamless SoC bring-up and software development in pre-silicon environments. * Creating and optimizing use models and applications for various emulation projects. * Conducting thorough verification and validation processes to ensure the highest quality of emulation models. * Providing technical guidance and mentorship to junior team members when necessary. The Impact You Will Have: * Enhancing the efficiency and effectiveness of our emulation models, significantly reducing time-to-market for new technologies. * Contributing to the development of high-performance silicon chips that power a wide range of applications, from consumer electronics to advanced computing systems. * Ensuring the reliability and robustness of our verification processes, thereby improving the overall quality of our products. * Driving innovation within the team, pushing the boundaries of what is possible in emulation and verification. * Playing a crucial role in the successful bring-up of SoCs, enabling software development in pre-silicon environments. * Fostering a collaborative and inclusive team culture that values continuous learning and improvement. What You ll Need: * Strong programming skills in C++ and a solid understanding of object-oriented programming concepts. * 5+ years of experience in relevant domain * Proficiency in HDL languages such as System Verilog and Verilog. * Familiarity with digital design concepts and verification methodologies. * Experience with scripting languages like Perl or TCL is a plus. * Knowledge of protocols such as ENET, HDMI, MIPI, AMBA, and UART is advantageous. Who You Are: * An excellent communicator who can articulate complex technical concepts clearly and effectively. * A proactive team player who is flexible, resourceful, and responsible. * An innovative thinker who is always looking for ways to improve processes and outcomes. * A detail-oriented professional who values quality and precision in their work. * A lifelong learner who stays updated with the latest industry trends and technologies.

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: Strong desire to learn and explore new technologies. Demonstrates good analysis and problem-solving skills. Prior knowledge and experience in tools like DC, ICC2, PT-SI,FC is a definite advantage. Should be a strong team player, excellent communicator as the role involves daily technical interaction with local, US counter parts. What You ll Be Doing: He/She will be part of SNPS DDR/HBM/Ucie IP implementation team and responsible for the implementation and integration of world class DDRs at the cutting-edge technology nodes. Timing closure above ~4GHz, mixed signal had macro IP integration, Building the efficient clock trees with very tight skew balancing are some of the challenges as part of day-to-day job. Prior working knowledge in the DDR/HBM/HBI timing closure, implementation would be an added advantage. Should be very hands-on and able to technically lead a team of 4-6 junior engineers towards successful completion of project on-time and with top quality. Who You Are: Typically requires a minimum of 6+ years of related experience after the post graduation. Possesses a full understanding of specialization area plus working knowledge of multiple related areas. A team player Independently resolves a wide range of issues in creative ways on a regular basis. Customarily exercises independent judgment in selecting methods and techniques to obtain solutions. Performs in project leadership role. Contributes to complex aspects of a project. Determines and develops approach to solutions. Work is independent and collaborative in nature. Provides regular updates to manager on project status. Represents the organization on business unit and/or company-wide projects. Guides more junior peers with aspects of their job.

As a RTL Design lead, first time bug free RTL from requirement or specification gives you a dopamine rush. Finding an alien life is a complex challenge, however, millions of bug free lines of RTL gives much more satisfaction. We are looking for an expert like you, having done multiple tape-outs, driven the design effort for complex IP/Subsystem/SoC blocks. Verification Lead: As a Verification lead, it is always a fun to catch bugs and ensuring that the design intent is met. Imagine your chip on a space telescope and sending beautiful images of galaxy - verification is the key to avoid white spots mixing with stars. We are looking for an expert like you, having lead multiple tape-outs, closed the verification of complex IP/Subsystem/SoC blocks. Job role and Skill set - Design role: Senior RTL Subsystems Designer Lead role. With 8+ years of experience. Must be able to drive the Subsystem life cycle from requirement to final release(s) phase(s), crafting the functional specification, defining the micro-architecture, coding the RTL with best practices, driving RTL quality checks and working with Verification and implementation teams, and, all the way to release(s). Proficiency with standard protocols like PCIe, DDR, UFS, USB, AMBA etc., Hands-on experience with low power design. Understanding of DFT requirements and architecture. Working with cross-functional teams and driving the projects to completion. Job role and Skill set - Verification role: Senior Verification lead role. With 8+ years of experience. Must be able to drive the complete Verification cycle : crafting the test plan, architecting the verification environment, developing the test infrastructure and executing the plan, driving to closure with coverage. Proficiency with Functional Verification of standard protocols like PCIe, DDR, UFS, USB, AMBA etc., Power aware Verification with UPF. Gate Level Verification hands-on experience is a value add. Working with cross-functional teams and driving the projects to completion.

Our Silicon IP business is all about integrating more capabilities into an SoC faster. We offer the world s broadest portfolio of silicon IP predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk. Responsibilities: DDR I/O Circuit design Requirements- Qualification: BTech/MTech Skills/Experience: MTech+3years / BTech+5years Knowledge of CMOS processes and issues in deep submicron process technologies. CMOS circuit design and layout methodology & flow; basic understanding of analog/mixed signal circuitry, familiarity with basic ESD concepts is an advantage. Familiarity with ASIC design flow. Knowledge of JEDEC requirements for DDR interfaces & standards, DDR Timing, ODT and SDRAM functionality would be a plus. Ability to execute assigned circuit design tasks with best product quality and efficiency. Good written and verbal communication skills in interactions with internal development teams.

You are a highly motivated and experienced professional with a deep understanding of VLSI design and a strong background in high-speed protocols such as Ethernet, DDR, and PCIe Your technical expertise is complemented by your hands-on experience in simulation, synthesis, and static timing analysis (STA) With a Bachelors and/or Masters Degree in Electrical Engineering or a related field, you bring at least 10 years of design, verification, or application engineering experience to the table You thrive in a UNIX environment and are proficient with ASIC/SoC tape-out processes from concept to full production Your ability to work across teams, coupled with strong analytical, reasoning, and problem-solving skills, sets you apart as a creative and results-oriented professional Excellent verbal and written communication skills in English are essential, as you will be collaborating with customers and teams worldwide Occasional travel is something you are comfortable with, and you are ready to take on the challenge of integrating leading Interface IP into next-generation products What You ll Be Doing: Acting as a trusted advisor for our Interface IP customers, providing guidance throughout their SoC flow. Supporting customers in resolving technical challenges and performing integration reviews at key milestones. Assisting with silicon/system bring-up and debugging critical issues. Collaborating with internal teams to deliver tailored solutions to customers. Staying updated with the latest industry specifications and applications in various hot market segments. Participating in occasional travel to support customer engagements and silicon bring-up activities. The Impact You Will Have: Enhancing the usability and adoption of Synopsys Interface IP products by providing expert technical support. Facilitating successful integration of IP into customer designs, contributing to their product development timelines. Improving customer satisfaction by resolving technical issues efficiently and effectively. Driving innovation by working with cutting-edge technologies and industry specifications. Strengthening Synopsys market position through successful customer engagements and support. Contributing to the development of next-generation products that leverage high-speed protocols and advanced IP. What You ll Need: Bachelors and/or Masters Degree in Electrical Engineering or similar with a focus on VLSI design. At least 10 years of design, verification, or application engineering experience. Proficiency in RTL coding using Verilog/VHDL. Experience with high-speed protocols such as Ethernet, DDR, and PCIe. Hands-on experience with simulation, synthesis, and static timing analysis (STA). Familiarity with UNIX environments and ASIC/SoC tape-out processes. Knowledge of CDC, RDC, Lint, DFT, STA, and LEC is a plus. Who You Are: Creative and results-oriented, capable of managing multiple tasks concurrently. Strong verbal and written communication skills in English. Ability to work collaboratively across teams to deliver solutions to customers. Strong analytical, reasoning, and problem-solving skills. Willingness to travel occasionally to support customer engagements.

At One Identity we know that companies with a strong positive culture perform so much better. That is why every day we strive to create a collaborative and inclusive working environment where our people can feel empowered to succeed. One Identity is an award-winning IT management software provider offering a broad selection of solutions that solve some of the most common and most challenging IT problems. We are looking for a talented and experienced Database Administrator (DBA) to join our engineering team. As a DBA supporting OneLogin , you will be responsible for the performance, reliability, and scalability of our database systems, particularly PostgreSQL, which is central to our data architecture. This role will involve administering large-scale PostgreSQL databases, optimizing performance, ensuring high availability, and providing support for database migrations, backups, and disaster recovery. You will collaborate closely with developers, DevOps, and other technical teams to ensure the smooth operation of our critical systems and data pipelines. If you are passionate about database management, enjoy solving complex problems, and want to contribute to an innovative and fast-growing SaaS company, wed love to hear from you! Responsibilities -Manage, maintain, and optimize PostgreSQL databases in production, test, and development environments -Ensure high availability, reliability, and scalability of databases -Implement and maintain automated database monitoring, backups, and performance-tuning processes -Troubleshoot and resolve database issues related to performance, capacity, and availability -Perform proactive performance analysis and tuning of queries, indexes, and schema design to ensure optimal database performance -Design and implement database partitioning, indexing, and optimization strategies for large-scale datasets -Continuously monitor database performance and make recommendations for improvements to system and query efficiency -Implement and enforce database security policies and best practices, including encryption, access control, and user management -Work with security and compliance teams to ensure databases meet regulatory standards (e.g., GDPR, SOC 2, etc.) -Maintain database disaster recovery plans and backup strategies, perform regular database backups, and ensure quick recovery in the event of failure -Provide on-call support and troubleshooting for production database issues -Assist in the migration of databases to new environments, patching to maintain database integrity and security, and upgrading PostgreSQL versions as necessary -Work closely with development, Quality Assurance, DevOps, and other teams to support application deployments, infrastructure changes, and strategic initiatives Qualifications 8+ years of hands-on experience as a PostgreSQL Database Administrator or in a similar database management role -Expertise in PostgreSQL database architecture, performance tuning, and query optimization. -Experience with high-availability setups, replication, failover, and disaster recovery strategies in PostgreSQL. -Strong understanding of database security, backup/recovery strategies, and data integrity principles. -Familiarity with cloud-based databases (AWS Aurora, RDS) -Experience with database migration and version upgrade strategies. -Proficiency with Linux/Unix-based systems and shell scripting. -Excellent problem-solving skills and the ability to troubleshoot complex issues effectively under pressure -Good team collaboration skills with a pragmatic and positive attitude -Excellent written and verbal communication skills in English Nice-to-have -Bachelor s degree in a technology related field or equivalent work experience -Familiarity with other database systems like MySQL, MariaDB, and/or NoSQL databases such as DynamoDB and Redis -Experience with monitoring tools (e.g., Datadog, CloudHealth, Sumologic) and PostgreSQL extensions (e.g., pg_stat_statements, pg_partman) is a plus. -Experience with infrastructure as code (IaC) tools such as Terraform, CloudFormation, Puppet and managing code via a Git version control system -AWS certifications such as AWS Certified Database Specialty, or AWS Certified Solutions Architect, AWS Certified Cloud Practitioner -Exposure to continuous integration/continuous deployment (CI/CD) pipelines, and database script execution tools like Liquibase Company Description One Identity enables organizations of all sizes to better secure, manage, monitor, protect, and analyze information and infrastructure to help fuel innovation and drive their businesses forward. With team members around the globe, we intend to continue to grow revenues and add value to customers. When you join our team, you will have the opportunity to build and develop products at a scale few others can provide. Our product portfolio serves a large base of customers and we are addressing the strategic imperatives for enterprise businesses. Working with some of the most talented employees the industry has to offer, we provide enhanced career opportunities for team members to learn and grow in a rapidly changing environment. Why work with us? -Life at One Identity means collaborating with dedicated professionals with a passion for technology. -When we see something that could be improved, we get to work inventing the solution. -Our people demonstrate our winning culture through positive and meaningful relationships. -We invest in our people and offer a series of programs that enables them to pursue a career that fulfills their potential. -Our team members health and wellness is our priority as well as rewarding them for their hard work. One Identity is an Equal Opportunity Employer and Prohibits Discrimination and Harassment of Any Kind: One Identity is committed to the principle of equal employment opportunity for all employees and to providing employees with a work environment free of discrimination and harassment. All employment decisions at One Identity are based on business needs, job requirements and individual qualifications, without regard to race, color, religion or belief, national, social or ethnic origin, sex (including pregnancy), age, physical, mental or sensory disability, HIV Status, sexual orientation, gender identity and/or expression, marital, civil union or domestic partnership status, past or present military service, family medical history or genetic information, family or parental status, or any other status protected by the laws or regulations in the locations where we operate. One Identity will not tolerate discrimination or harassment based on any of these characteristics. One Identity encourages applicants of all ages. Come join us. For more information, visit us on the web at One Identity Careers | Explore Opportunities with the OI Team Job seekers should be aware of fraudulent job offers from online scammers and only apply to roles listed on quest.com/careers using our applicant system. Note: We do not use text messaging or third-party messaging apps like Telegram to communicate with applicants, so please exercise caution if you are approached in this way and only interact with people claiming to be Quest employees if they have an email address ending in @quest.com or @oneidentity.com #LI-SR1

Minimum 8+ years of relevant experience in Security Operations, Threat Detection, or Incident Response. JD- NBAD (Network Behavior Anomaly Detection): Monitor and analyze network traffic to identify anomalies indicating potential threats or breaches. Work with network and SOC teams to investigate and respond to suspicious network behavior.\ SIEM (Security Information and Event Management): Configure, manage, and fine-tune SIEM tools for log ingestion, correlation rules, alerting, and reporting. Perform threat hunting, incident analysis, and security event investigations. Develop and maintain custom use cases to detect advanced threats. Required Qualifications: Education: B.E./ B.Tech/MCA/M.Sc . in Computer Science or Information Technology. Certifications: Certified Ethical Hacker (CEH) mandatory.

We are seeking a highly skilled Security Operations Center (SOC) Analyst with expertise in user case management ( detection engineering ) and dark web monitoring to join Renault Group dynamic cybersecurity team. The ideal candidate will have a deep understanding of cybersecurity principles, threat detection methodologies, and hands-on experience in managing security incidents and monitoring the dark web for potential threats. Key Responsibilities: Utilize security information and event management (SIEM) tools to monitor, analyze, and respond to security events and incidents. Develop and maintain use cases, correlation rules, and alerts to enhance the detection capabilities of the SOC. Investigate security incidents, conduct root cause analysis, and provide recommendations for remediation and risk mitigation. Implement and fine-tune detection mechanisms, including signature-based detection, anomaly detection, and behavioral analysis. Collaborate with cross-functional teams, including threat intelligence analysts, incident responders, and system administrators, to identify and prioritize security use cases based on Renault Groups risk and threat landscape. Document use case logic, implementation details, and testing procedures to ensure consistency and repeatability. Analyze security events and incidents to identify patterns, trends, and potential indicators of compromise (IOCs). Conduct research on emerging threats, vulnerabilities, and attack techniques to inform the development of new use cases and improve existing ones. Monitor the dark web for mentions of the organizations assets, sensitive information, or potential threats. Analyze dark web intelligence to identify emerging threats, malicious actors, and security vulnerabilities relevant to the organization. Create and maintain documentation related to incident response procedures, playbooks, and standard operating procedures (SOPs). Stay current with emerging threats, vulnerabilities, and attack techniques to continually improve the Renault Group security posture. Qualifications Bachelors degree in Computer Science, Information Technology, Cybersecurity, or related field. Strong understanding of security information and event management (SIEM) concepts, log analysis, and security analytics. Experience in developing use cases, correlation rules, and alerts for SIEM platforms Knowledge of security frameworks and standards (e.g., MITRE ATT&CK framework, NIST Cybersecurity Framework, ISO 27001). Familiarity with scripting and programming languages (e.g., Python, PowerShell) for automation and tool development is a plus. Experience with dark web monitoring tools and techniques.

Design, develop and maintain high quality services, adhering to best practices and coding standards Proficiency in services development frameworks and technologies such as Java or Node.js Experience in .NET/C# is preferred Collaborate with other team members to contribute to the design and evolution of the services architecture, ensuring security, scalability, reliability and performance Managing deployments as needed Such as software upgrades, hotfixes, or emergency patches. Handling customer escalations and CI issues These are almost always during U.S. business hours, so time zone alignment is important Maintaining the infrastructure Ensuring services like Redis, RDS, Elasticsearch, etc., remain performant and aren t consuming unnecessary resources Supporting compliance and certifications Including Google OAuth, SOC 2, ISO, etc Create robust RESTful APIs and integrate with external services, ensuring data consistency and security Work with various database systems, including SQL or NoSQL, to design efficient data models and access patterns for services Identify and address performance bottlenecks in the services, optimizing code and infrastructure as needed Write unit and integration tests and participate in code reviews to maintain code quality and reliability Investigate and resolve issues reported in production, providing timely solutions to ensure system availability What you bring: Bachelors degree in Computer Science or equivalent from a premier institution. 2+ years of experience as a backend developer, with a strong focus on services development Proficiency in services development frameworks and technologies such as Java or Node.js. Experience in .NET/C# development is preferred. Solid understanding of services architecture principles and best practices Proficiency in RESTful API design and development Familiarity with databases (SQL or NoSQL) and data modeling Must be able to work independently and deliver excellent results in short timelines Experience with containerization and orchestration tools Strong problem-solving and debugging skills Experience with public cloud platform Excellent communication and collaboration skills Ability to thrive in a dynamic, fast-paced environment.

Working with Synopsys customers to understand their needs and define verification scope and activities. Understanding the complexity and requirements of verification and proposing resource requirements to complete the activities. Leading a team of engineers to perform various pre-silicon verification activities on IPs/Subsystems. Anticipating problems and risks and working towards a resolution and risk mitigation plan. Assisting and mentoring the team in day-to-day activities and growing the capabilities of the verification team for future assignments. Reviewing various results and reports to provide continuous feedback to the team and improve the quality of deliverables. Reporting status to management and providing suggestions to resolve any issues that may impact execution. Collaborating with architects, designers, and pre and post-silicon verification teams to accomplish your tasks. Adhering to quality standards and good test and verification practices. Ramping up on new Verification tools and methodologies using Synopsys Products to enable customers. Working with other Synopsys teams including BU AEs and Sales to develop, broaden, and deploy Tool and IP solutions. The Impact You Will Have: Driving the success of customer projects by ensuring robust and thorough verification of SoC designs. Enhancing Synopsys reputation as a leader in verification through high-quality deliverables and customer satisfaction. Mentoring and growing the verification team, building a strong foundation for future projects. Identifying and mitigating risks early, ensuring smooth project execution and delivery. Improving verification methodologies and practices, contributing to the overall efficiency and effectiveness of the team. Collaborating with cross-functional teams to achieve seamless integration and execution of verification activities. Providing valuable feedback and insights that drive continuous improvement in verification processes and tools. What You ll Need: B.E/B. Tech/M.E/M. Tech in electronics with a minimum of 12+ years experience in SoC/IP/Subsystems verification domain. Technical expertise in various aspects of pre-silicon Verification (UVM, Coverage Analysis, Verification plan creation, debugging, etc). Good knowledge of various protocols (PCIe, Ethernet, USB, DDR, etc) and/or processor/interconnect/debug architecture. Hands-on experience with verification tools such as VCS, waveform analyzers, and third-party VIP integration (such as Synopsys VIPs). Ability to lead a team to perform verification on complex SoC/IP/Subsystems. Experience with planning and managing verification activities for SoC/Subsystems/IPs. Strong understanding of design concepts, ASIC flows, and stakeholders. Good communication skills. Who You Are: A proactive and detail-oriented leader who can guide and mentor a team. An excellent communicator who can collaborate effectively with cross-functional teams. A problem-solver who can anticipate challenges and develop effective mitigation strategies. A continuous learner who stays updated with the latest verification tools and methodologies. A team player who values quality and strives for excellence in deliverables

Develop and maintain automation scripts for CAD tools using languages like Python, Perl, or TCL. Collaborate with designers and engineers to identify automation opportunities and implement solutions. Design and implement automation frameworks for design flow of multiple functions using AI. Proficient in troubleshooting and debug automation scripts and CAD tool issues. Develop and maintain documentation for automation scripts and processes. Understanding of DV flow and generating test benches and test cases. Understanding RTL and gate-level SDF-annotated simulations and debug. May perform mixed-signal (digital + analog) simulations and debug. Interact with our application engineers and provide guidance to customers. Participate in the generation of data books, application notes, and white papers. Understanding CAD infrastructure, methodology will help to setup project environment. Contribute to enhance quality assurance methodology by adding more quality checks/gatings. Front End development process understanding and support Internal tools development and automation to help improve productivity across ASIC design cycles. Work with design engineers on new tools/technology and new features evaluation and adoption Perform physical verification and design rule checks to ensure design integrity and manufacturability. Understanding of tools like VC Spyglass, Verdi, & views like SDF, Liberty etc and other frontend views will add value to this position. Writing RTL Code, Solid Verilog, PERL, and Python skills and TCL are good additions. Understanding static timing analysis and synthesis, DFT/ATPG skills would be a plus. Previous knowledge of customer support and/or silicon bring-up is a plus. Drive automation to enhance IP Quality-Assurance flow & Release process. Define and establish a comprehensive QA process for IP development. Integrate new features and functionalities into IPQA scripts with automation team. Streamline the release process to reduce cycle time and improve efficiency. Automate release tasks, such as packaging and documentation, to reduce manual errors. Improve release quality by integrating QA processes into the release workflow. Enhance releasing documentation to ensure completeness and accuracy. Validate the integrity of the release package by checking for corruption, tampering, or other issues (Time Stamp and Locking Source of Release package and Release package itself). Required Skills: Bachelor s or master s degree in electrical engineering or a related field. 3 to 7+ years of experience in A&MS frontend and backend views & collaterals development flows. Proficiency in industry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler. Exceptional knowledge of layout design methods, techniques, and methodologies. Experience with physical verification tools, such as Calibre or Assura. Understanding of semiconductor process technologies and their impact on layout design. Excellent problem-solving and systematic skills. Ability to work effectively in a team-oriented environment. Familiarity with Synopsys Tool set (such as FC/ICC2, Primetime, Formality, ICV). Good communication and interpersonal skills.

Responsible for PCIe/CXL next-gen Controller IP features Customer pre/post sales PCIe/CXL protocol related communication Utilizing advanced design methodologies and tools to achieve high-quality results Mentoring and guiding other engineers, promoting best practices, and fostering a culture of continuous improvement Communicating with internal and external stakeholders to align on project goals and deliverables. What You ll Need: Extensive experience in digital ASIC design and physical aware synthesis. In-depth knowledge of PCIe, CXL , AXI, CHI and similar IO protocols. Proficiency in advanced digital design tools and methodologies. Strong problem-solving skills and the ability to work independently. Excellent communication skills for effective collaboration with diverse teams. Experience of 20+ years in relevant domain. Who You Are: A mentor who fosters talent and encourages innovation. A proactive problem solver who thrives in complex environments. An effective communicator with the ability to convey technical concepts to a broad audience. A team player who values collaboration and diversity.

Carry out in-depth investigation on security events, raise incidents and support the Incident Management process. Provide remote incident response activities and advice to support customers during and immediately after security incidents. Respond to system generated alerts, analyze logs and traffic patterns. Maintain and improve SIEM correlation rules and Endpoint Protection detections. Supporting multiple customer environments concurrently. Provide analysis and trending of security log data and network traffic. Generate customer facing security reports. Integrate and share information with other analysts and other teams. Other duties as assigned. REQUIREMENTS: Has a passion for security and enjoys solving problems. Experience working with SIEM and EDR systems. Good knowledge of Cyber Security Incident Response processes & procedures. Excellent knowledge on the fundamentals of Windows and Unix systems. Good understanding of host forensics, memory forensics and network forensics. In-depth knowledge of the security threat landscape. Knowledge of various security methodologies and processes, and technical security solutions. Knowledge of TCP/IP Protocols, network analysis, and network/security applications. Knowledge of investigation techniques to determine security incidents. Ability to multi-task, prioritize, and manage time effectively. Strong attention to detail. Excellent interpersonal skills and professional demeanor. Excellent verbal and written communication skills. Excellent customer service skills. Industry standard certifications such as: CREST CRT, GCFA, GCFE, GNFA, GREM. 4+ years experience as a Cyber Security Analyst or equivalent. Experience of working in an MSSP/MDR SOC environment. Ability to work a shift rota. In order to be considered for a position at Kroll, you must formally apply via careers.kroll.com Kroll is committed to equal opportunity and diversity, and recruits people based on merit #LI-TM1 #LI-Remote

ANZEN Technologies Private Limited. stands as an unparalleled powerhouse, empowering organizations across industries with our visionary services, cutting-edge solutions, and ground-breaking services in the realm of Cyber Security, IT Governance, Risk Management, and Compliance. As your trusted partner, we offer a comprehensive suite of End-to-End security services and consultancy, tailored to safeguard critical infrastructure installations, elevate the standards of BFSI, eCommerce, IT/ITES, Pharmaceuticals, and an array of other sectors. Position : Analyst - GRC Key Responsibilities: * Track and ensure adequate and timely resolution to all audit and risk assessment findings or issues relating to information security, and never miss a deadline. * Effectively and appropriately communicate audit engagement reports and recommendations to client management and resolve any client concerns or questions. * Ensure 100% certification success rate on ISMS projects. * Grow into a role with increasing responsibility. * Significant experience leading information security audits with a preference for IS0 27001 and SOC 2 audits or assessments. * Experience in leading or knowledge with implementations. * Experience authoring policies and procedures. * Significant experience working as a consultant working in a consulting firm * Significant knowledge of ISO 27001/2 and its derivatives (e.g., HITRUST, Shared Assessment) as much of our consulting and collaboration is around an ISO 27001 Information Security Management System. * Solid knowledge of the NIST 800-171/FISMA framework and is derivatives (e.g., Fed RAMP, CMS Information Security Program) as many of our clients serve government customers. * Enough Information Technology and Information Security experience to contextualize and make their recommendations relevant and valuable. * Experience and knowledge with Governance, Risk Management and Compliance. * Experience with the myriad of regulatory compliance frameworks our client base is subject to (e.g., HIPAA, PII, PCI-DSS, SOX, STARS, NERC-CIP). * Certifications that demonstrate to our clients our commitment to excellence in our craft (e.g., ISO 27001 Lead Implementer, CISA, CISSP, ISO 27001 Lead Auditor, MCSE, CEH, OSCP). * Familiarity with related standards (e.g., SSAE-16 SOC1, SOC2, ISO-22301, ISO-9001). Qualifications & Certifications : Graduated from IT Stream Experience: Candidate with 1 to 2 Years of experience. Excellent communication and interpersonal skills. Technical proficency is must Ability to work in a fast-paced environment Preferred Skills & Location Experience in Cybersecurity, IT Industry from Navi Mumbai Office Address : ANZEN Technologies Private Limited Akshar Business Park, H - 3025, 3rd Floor, Plot No. 3, Sector-25, Vashi, Navi Mumbai 400703 https://anzentech.com Immediate Joiner may apply for this position

We are seeking a seasoned SoC Architect with expertise or significant interest in System Architecture. You have had significant success driving architecture, product roadmaps and product requirements. You are meticulous about Power, Performance and Area while driving schedule and managing cost. This senior role will stretch you as you lead architecture teams in new directions, network with our world-class, patent-holding think-tank, and negotiate amongst design teams, marketing, and business unit executives. THE PERSON: You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: Define product features and capabilities, close architecture, and micro-architecture requirements, drive technical specifications for SoC and IP blocks to meet those requirements, and provide technical direction to execution teams Comprehend the SOC as a complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features, optimizing for performance and power Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements Knowledge sharing and other contributions to Platform & System Architecture As an overall product owner, responsible for architecture analysis and technical solutions for marketing/feature change requests Work closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets, Emulation plans, Pre-Si bug resolution and Performance/Power Verification sign offs Support Post-Si teams for Product Performance, Power and functional issues debug/resolution PREFERRED EXPERIENCE: Outstanding foundation in Systems & SoC architecture, with expertise in one or more of the following: CPU or GPU, Memory sub-system, Fabrics, CPU/GPU coherency, Multimedia, I/O subsystems, Clocks, Resets, Virtualization and Security Experience analyzing CPU, GPU or System-level Micro-Architectural features to identify performance bottlenecks within different workloads Demonstrated expertise in power management microarchitecture, low power design and power optimization, along with power impact at architecture, logic design, and circuit levels Excellent communication, management, and presentation skills. Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies ACADEMIC CREDENTIALS: bachelors or masters degree in related discipline preferred

The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 12+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

We are looking for an adaptive, self-motivative EMIR engineer to join our growing team. As a key contributor , you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The EMIR team furthers and encourages continuous technical innovation to showcase successes as we'll as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ time zone s . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Good understanding of IR/Power-Domain-Network signoff at SOC & block level Experience in RHSC tool Good at scripting python/perl/tcl Must have knowledge of Physical Implementation (Synthesis and Place&Route) Effective communication ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering with 5+Yrs of exp.

The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc You are meticulous about Power, Performance and Area while driving schedule and managing cost. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 16+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

We are looking for a Fellow-level Engineer to join our team to develop world-class DFT architecture for EPYC Server products. In this role you will be engaged with the SoC Architects, Micro Architects, PD Engineers, Product Engineers, etc, to define and implement the DFT Architecture, guide/technically lead the DFT Team to ensure right pre-si verification is done for the DFT logic, and the highest level of Scan coverage is achieved to hit the product goals. You will also be responsible for driving innovation to continuously improve the execution and also drive TTR (Test Time Reduction) THE PERSON: You will possess very strong DFT knowledge and bring broad experience in with a strong, self-motivated work ethic and leadership qualities. KEY RESPONSIBILITIES: Work closely with the SoC Architecture and uArch teams to define the DFT architecture. Be the Tech Lead driving DFT RTL implementation, DFT functional and Scan capture timing closure, Scan/ATPG implementation to hit the product coverage goals, interactions with the Product Engineering team to ensure on-time and FirstTimeRight pattern delivery and silicon bring-up Drive the required pre-silicon reviews for RTL, DFT DV and ATPG to ensure clean silicon bring-up Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to comprehend and validate all the usage models Work with the post-silicon team on debug support and to help root-cause any failures Be upto date with the industry trends and bring-in the latest to the AMD products Work with DFT Tool Vendors and drive improvements based on our requirements REQUIREMENTS: 15+ years of in-depth DFT experience having driven multiple Tapeouts and silicon bring-ups across different process nodes. Good understanding and exposure to SoC design and architecture Very good understanding of verif and timing concepts having handled DFT timing closure Exposure to all DFT concepts such as JTAG, SCAN, MBIST, BScan, etc Comfortable with VCS/Verdi and Mentor TK. Logical in thinking and ability to gel we'll within a team Good stakeholder management Ability to quickly adapt to changes and handle pressure Good communication and leadership skills ACADEMIC CREDENTIALS: Bachelors or Masters degree in Computer engineering/Electrical Engineering

The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 12+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

We have a team of security compliance leaders overseeing solutions for this complex environment, collaborating with security architects and Cloud DevOps teams internally and around IBM. The security compliance leader’s role is to determine the secure operation of the all computer systems, servers, and network connections in accordance with our policies, procedures, and compliance requirements. A security compliance leader in our team will participate in some or all of the following: Providing subject matter expertise in the creation, implementation, and maintenance of appropriate enterprise programs, policies, and procedures to be compliant with all applicable regulations including ISO, SOC, HIPAA, PCI, FedRAMP/FISMA Having the ability to utilize working knowledge of information security best practices such asNIST 800 series, ISO 27000 series, GDPR, etc Interpreting standards, requirements, and their application to the enterprise Cloud environment in the most reasonable and cost-effective manner Developing, implementing, maintaining, and overseeing enforcement of security policies Collaborating with security architects and technical security teams to define and implement security processes and procedures based on industry-standard best practices and compliance requirements. Defining the requirements and validating the procedures and audit testing methodology Conducting regularly scheduled audits on systems and hosting third-party audits as required in order to maintain certifications and compliance certificates. Working with the DevOps teams to prepare ongoing client reporting, information for prospective clients, and marketing materials Providing training to teams as needed Assisting team members and internal clients in addressing highly complex security issues applicable to enterprise environment Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise Minimum of 12 years of relevant compliance experience and cybersecurity knowledge Compliance leaders do not require dev experience, but it is an advantage. 10+ years of security compliance audit experience is a must Ability to utilize working knowledge of information security best practices such asNIST 800 series, ISO 27000 series, GDPR, etc Experience with compliance programs such as FFIEC or FedRAMP/ FISMA, HIPAA, GDPR, SOC 2, or PCI Experience in risk assessment processes, policy development, proposals, work statements, product evaluations, and delivery of technology Ability to understand enterprise business computing operations/requirements, and in particular, Cloud Ability to stand firm on issues yet be flexible and creative when working with customers to find effective solutions Ability to understand and interpret laws and regulatory requirements related to information protection, and develop and implement appropriate processes to achieve and maintain compliance and reduce risk