Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Experience "“ 4 to 7 Years in EM/IR/PDN Roles and Responsibilities Perform various electrical analyses at block and top levels, including static/dynamic IR, power/signal EM, and ESD Drive block and top-level electrical verification closure Develop power grid specs based on power/performance/area targets of different SOC blocks. Implement power grids in industry standard PnR tool environments. Work closely with the PI team to optimize the overall PDN performance. Work with CAD and tool vendors to develop and validate new flows and methodologies. Preferred qualifications BS/MS/PhD degree in Electrical Engineering; 4+ years of practical experience In-depth knowledge of EMIR tools such as Redhawk and Voltus Experience in developing and implementing power grid Good knowledge of system-level PDN and power integrity Practical experience with PnR implementation, verification, power analysis and STA Proficient in scripting languages (TCL/Perl/Python) Experience with industry standard EMIR tools such as Redhawk and Voltus Basic knowledge of the physical design flow and industry standard PnR tools Experience with scripting languages such as TCL, Perl and Python Ability to communicate effectively with cross-functional teams

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. General Summary PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains"“ LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux "“ Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications "¢ 2+ years Hardware Engineering experience or related work experience. "¢ 2+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. General Summary PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains"“ LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux "“ Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications "¢ 5+ years Hardware Engineering experience or related work experience. "¢ 5+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: Qualcomm is looking for talented and enthusiastic engineers with strong interests in OS, kernel and computer architecture. The Qualcomm Hypervisor team is world-leading, enabling virtualization across multiple chipset products for mobile, automotive, compute and IoT. The team is responsible for the hypervisor software layers that plays a key role in platform security and performance. Qualcomm is industry leading in its adoption of virtualization technology in its Snapdragon mobile products. The team has built hypervisor and SMMU expertise and continues to develop innovative features, enhancements, and use-cases. As a software engineer at Qualcomm, you will help develop SMMU, hypervisor and related software for the latest cutting-edge Application processors, which is embedded in a wide range of chipset products and used by many OEMs in millions of devices. The role will include interfacing with large software stacks such as Bootloaders, Linux and TrustZone "“ which provides the opportunity to interact with teams around the world. -- Responsibilities We are looking for a highly motivated engineer and team player who is passionate to learn new technologies and write low level firmware that drives hardware and SoC. Minimum Qualifications: "¢ Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Software Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience. "¢ 2+ years of work experience with Programming Language such as C, C++, Java, Python, etc. Your responsibilities may include: Design, development and integration of SoC firmware features, diagnostics and test capabilities for QCT boot platforms. Strong coordination and collaboration across wide range of technical areas to include software, hardware, ASIC, integration, architecture, and emulation teams. Paying attention to the details during all phases of firmware design, development, integration, testing and release - Work with Emulation, HW design teams, as necessary, in verifying and debugging firmware, driver and resolving platform issues Efficient and secure (ie. cognizant of not exposing security exploits) coding plus driving code review of firmware logic updates with all required stakeholders On time execution of defined tasks and deliverables, driving dependencies with other teams to closure Triage of software issues, defect investigation and problem resolution. Technical documentation including APIs, manuals, and user guides. "“ Skills and Experience We are looking for engineers from a range of backgrounds and experience, including graduates and experienced kernel and systems developers Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 8+ years of Software Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 6+ years of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 4+ years of Software Engineering or related work experience. Preferred Qualifications: Strong understanding or experience with C. An understanding of computer architecture, operating systems, and kernels. Linux, kernel, bootloader or OS development experience. ARM CPU architecture knowledge. IOMMU and ARM SMMU knowledge Hypervisors and virtualization. Experience with multi-processing or multi-threading, concurrency, and synchronization. Writing device drivers and interfacing hardware. Experience with secure coding. Use of debugging tools such as GDB, Lauterbach Trace32 and understanding assembly. Real-time OS. Toolchains and systems libraries (libc etc). Python, shell scripting and Linux based development environment. Good communication and presentation skills. Test development and test automation. Contributing to open-source projects. Demonstrated independent software design, good analytic and problem-solving skills. Any automotive and functional safety experience may also be relevant.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: The candidate would be joining a team with deep expertise in designing IP for wireless sub-systems for market leading products. In this role, the candidate would be working on connectivity solutions for mobile phones, wearables, IOT and Mobile Infrastructure chips. The candidate would be a part of Bluetooth IP Design team and will be involved in IP and sub-system development. The role requires working on the latest technology nodes on all aspects of the VLSI development cyclearchitecture, micro architecture, RTL design and integration. Close interactions with system architecture, verification, SoC Design, Validation, Synthesis & PD teams are required for design convergence. Skills/Experience 2-6 years of experience in the design of complex ASICs Strong expertise in RTL coding of complex designs using Verilog/SV Exposure to low power design methodology and designs with multiple clock domains Strong debugging, analytical skills and strong communication skills, both verbal and written Hands-on experience in front-end design tools Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Why Join Siemens? At Siemens, you will be part of a global leader committed to innovation, quality, and excellence. This role offers the opportunity to work on challenging projects, develop professionally, and make a significant impact in the electrical and instrumentation domain, particularly within power plant and renewable energy projects. If you are passionate about leading a talented team and driving technical excellence, we encourage you to apply. As Siemens Energy, "We energize society" by supporting our customers to make the transition to a more sustainable world, based on innovative technologies and our ability to turn ideas into reality. We do this by Expanding renewables Transforming conventional power Strengthening electrical grids Driving industrial decarbonization Securing the supply chain and necessary minerals Looking for challenging role? If you really want to make a difference - make it with us Siemens Energy (SE) is a global pacesetter in energy, helping customers to meet the evolving demands of today's industries and societies. SE comprises broad competencies across the entire energy value chain and offers a uniquely comprehensive portfolio for utilities, independent power producers, transmission system operators and the oil and gas industry. Products, solutions and services address the extraction, processing and the transport of oil and gas as well as power generation in central and distributed thermal power plants and power transmission in grids. With global headquarters in Munich in Germany and more than 88,000 employees in over 80 countries, Siemens energy has a presence across the globe and is a leading innovator for the energy systems of today and tomorrow, as it has been for more than 150 years. Your new role "“ challenging and future-oriented You would be responsible for all system administration requirements like installation, upgrades, and updates of DCS Systems (SPPA T3000) before the delivery of components to customers as well as during the after-sales service phase. You would be part of remote service support center and would support customers in troubleshooting of problems faced by customer. As part of your profile there would be requirement of travelling to many project sites during installation as well as service phase of I&C Systems. You have great opportunity to work with global remote support centers and global teams We don't need superheroes, just super minds You're a bachelor's in engineering with 3 to 5 years of experience in system administration of Instrumentation & Control (I&C)/PLC systems. You've great knowledge and experience of DCS & PLC Systems You've great knowledge of SPPA T3000 control system and "˜know-how' on the system administration and troubleshooting would be an added advantage. You've great knowledge of network implementation including switches, firewalls, router etc. You've professional exposure in implementation of cyber solutions like NIDS, Application Whitelisting, Domain Controller, SIEM Solutions would be added advantage. We've got quite a lot to offer. How about you? This role is based in Gurgaon, where you'll get the chance to work with teams impacting entire cities, countries "“ and the shape of things to come. We're Siemens. A collection of over 379,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we welcome applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and imagination and help us shape tomorrow.

Responsibilities: * Design, implement, and maintain secure solutions on AWS cloud platform using IAM and security architecture principles.

Key Responsibilities: - Act as a strategic advisor to the CEO, providing insights and recommendations on key decisions. - Oversee the execution of strategic initiatives, including planning, monitoring progress, and ensuring deliverables are met. - Conduct research and analysis on technology trends and policies for informed decision-making. - Manage cross-functional coordination for high-impact projects and organizational goals. - Prepare detailed reports, presentations, and briefings for internal and external stakeholders. - Serve as a liaison between the CEO and internal teams, streamlining communication and ensuring alignment with organizational priorities. - Build and maintain relationships with industry stakeholders, government bodies, and partner organizations. Core Competencies: Industry Awareness: - Keeps abreast of developments in the technology sector and government policies. Evaluates the consequences of changes in the business environment. Problem Solving: - Leverages past problem-solving experiences to anticipate and proactively prevent future issues. Demonstrates technical acumen in addressing and solving complex issues. Team Collaboration: - Collaborate effectively within the team to builds and fosters a team-based approach to achieving goals and objectives. - Maintains a regular and relevant flow of information up and down the organization. Communication Skills: - Excellent verbal and written communication skills for clear coordination with stakeholders.- Listens and checks understanding to interpret information and create significance.Qualifications:- Bachelor's degree in Technology, Business Administration, or a related field; a Master's degree (MBA/Technology) from premier B School is preferred.- Minimum 3-7 years of experience in a similar role. - Strong understanding of cyber security trends, emerging technologies, and government policies.- Proven ability to handle complex projects, manage multiple priorities, and work under tight deadlines.- Exceptional interpersonal, written, and verbal communication skills.- Demonstrated analytical and problem-solving abilities with a strategic mindset.- Proficiency in using project management tools and technology platforms.- Strong organizational skills with meticulous attention to detail.ApplySaveSaveProInsights

As a Senior Cybersecurity Specialist with an MSSP, you will play a pivotal role in designing, implementing, and managing Security Operations Center (SOC) architecture for multiple client environments while actively monitoring, detecting, and responding to advanced cyber threats You will work with cutting-edge technologies such as SIEM, EDR/XDR, and PAM solutions to provide comprehensive security services to clients This hybrid role requires a combination of SOC architecture expertise, incident response skills, and the ability to deliver tailored solutions in a managed services environment, Key Responsibilities SOC Architecture & Implementation: Design and implement scalable and multi-tenant SOC architectures to support client environments, ensuring compliance with MSSP best practices, Deploy, configure, and maintain SIEM solutions (e-g , Seceon, Splunk, QRadar) for real-time threat monitoring across diverse client infrastructures, Manage and integrate EDR/XDR tools (e-g , CrowdStrike, Sentinel One) and PAM solutions (e-g , CyberArk, Beyond Trust) to secure privileged accounts and endpoints, Customize SOC processes and workflows to address unique client needs, including playbook creation, automation, and escalation pathways, Develop KPIs and metrics to measure the SOCs performance and ensure SLA compliance for MSSP clients, Threat Detection & Incident Response Proactively monitor and analyze security alerts and events for multiple clients using SOC tools like SIEM and EDR, Conduct advanced threat hunting and forensic investigations across client networks to identify vulnerabilities and mitigate risks, Lead incident response efforts for clients, including containment, eradication, and recovery, while documenting root causes and lessons learned, Develop custom correlation rules, dashboards, and reports in SIEM tools to enhance threat detection capabilities for clients, Client Support & Engagement Act as the primary point of contact for clients regarding SOC operations, incident response, and cybersecurity posture, Conduct regular security assessments and provide detailed reports with actionable recommendations tailored to each client, Provide thought leadership and advisory services to clients on emerging threats, regulatory compliance (e-g , GDPR, ISO 27001), and cybersecurity trends, Participate in onboarding and training sessions to educate clients on security best practices and SOC processes, Strategic Planning & Continuous Improvement Stay informed about the latest cybersecurity threats, trends, and technologies to continuously enhance MSSP services, Identify opportunities for process improvement, including the use of automation, AI/ML, and orchestration tools to improve SOC efficiency, Mentor and guide junior analysts and architects, fostering a high-performance MSSP team, Required Skills Proven experience in SOC architecture design, implementation, and multi-tenant management for MSSP clients, Hands-on expertise with SIEM solutions (e-g , Seceon, Splunk, QRadar) and EDR/XDR platforms (e-g , CrowdStrike, Sentinel One), Strong knowledge of PAM solutions (e-g , CyberArk, Beyond Trust) and their role in securing client infrastructures, Advanced skills in threat hunting, log analysis, and incident response, Familiarity with MSSP environments, including SLA management, multi-client support, and customization of security services, Deep understanding of cybersecurity frameworks (e-g , NIST, CIS Controls) and regulatory requirements (e-g , GDPR, PCI DSS), Proficiency in Zero Trust Architecture (ZTA), IAM, cloud security (AWS, Azure, GCP), and hybrid infrastructures, Excellent client-facing communication skills, with the ability to simplify technical concepts and build trust with stakeholders, Qualifications Bachelors or Masters degree in Cybersecurity, Information Technology, or related field, 4+ years of hands-on experience in cybersecurity, including SOC operations, architecture, and multi-client threat management in an MSSP environment, Industry certifications such as CISSP, CISM, CEH, or vendor-specific credentials (e-g , Splunk Certified Architect, CrowdStrike Certified Expert, CyberArk Defender), Why Join Us Opportunity to work with cutting-edge cybersecurity technologies in a fast-paced MSSP environment, Collaborate with industry experts and gain exposure to diverse industries and client challenges, Competitive salary, performance-based incentives, and professional growth opportunities, Apply Now

Role Summary: We are seeking a skilled and motivated Team Manager for our Global Security Services to join our dynamic Group Information Security team The successful candidate will be responsible for supporting the organizations security posture by identifying, analyzing, and mitigating security risks across our organization This role both growing and managing a team of skilled individuals responsible for our global security services You will be assisting and driving the continual improvement, testing, implementation, and monitoring of security measures for the ASSA ABLOY Group, Your work will be focused on improving the Groups security posture through activities including risk assessments, threat monitoring, compliance with security frameworks and regulations, supplier security due diligence and more, Key responsibilities: Growing and managing our Security Services team in India Analysis of the findings from assessments and audits, monitoring control compliance Responsible for the delivery of our Security Services from India, Hosting Security status meetings with various stakeholders in our Global teams, Responsibilities And Authorities List of responsibilities and authorities: No budget responsibilities Personnel responsibilities for 4+ Growing the team based on demands, recruitment, hosting interviews and selecting suitable candidates, Direct Reporting to the Site Manager of our Chennai office, reporting to our Group CISO, Information Security Manager and Head of Cyber Security in a matrix format, Part of relevant programs, projects, councils and forums Key competences: List of key competences Background in Information Security, IT auditing or Cyber security with high integrity Experience of working in a multi-national, complex, or highly regulated environment, Knowledge and experience of working internationally known standards within Information Security such as ISO27000-series, SOC2, NIST frameworks and similar Knowledge and experience of working with Microsoft 365 security features, Microsoft Purview and ServiceNow platforms Proven leadership skills Requirements: Education: Bachelor's or Master's degree in Computer Science, Information Systems, Cyber security or similar Languages: Fluent in English Computer skills: Good, Microsoft 365 suite and ServiceNow platform Other: Certifications such as CISM, CISSP can be of advantage Experience with Microsoft security applications and features is of advantage Experience: 5+ years in information security or a related field, preferably in a global or enterprise environment, Personal qualities : List of personal qualities Proactive and detail-oriented individual Excellent communication skills, with the ability to convey security concepts to non-technical staff, Strong critical thinking, problem-solving, logic, and analytical skills, Ability to work both independently and collaboratively as part of a team, We are the ASSA ABLOY Group Our people have made us the global leader in access solutions In return, we open doors for them wherever they go With nearly 63,000 colleagues in more than 70 different countries, we help billions of people experience a more open world Our innovations make all sorts of spaces physical and virtual safer, more secure, and easier to access, As an employer, we value results not titles, or backgrounds We empower our people to build their career around their aspirations and our ambitions supporting them with regular feedback, training, and development opportunities Our colleagues think broadly about where they can make the most impact, and we encourage them to grow their role locally, regionally, or even internationally, As we welcome new people on board, its important to us to have diverse, inclusive teams, and we value different perspectives and experiences,

About Us At FDJ UNITED, we don't just follow the game, we reinvent it FDJ UNITED is one of Europes leading betting and gaming operators, with a vast portfolio of iconic brands and a reputation for technological excellence With more than 5,000 employees and a presence in around fifteen regulated markets, the Group offers a diversified, responsible range of games, both under exclusive rights and open to competition We set new standards, proving that entertainment and safety can go hand in hand Here, youll work alongside a team of passionate individuals dedicated to delivering the best and safest entertaining experiences for our customers every day Were looking for bold people who are eager to succeed and ready to level-up the game If you thrive on innovation, embrace challenges, and want to make a real impact at all levels, FDJ UNITED is your playing field Join us in shaping the future of gaming Are you ready to LEVEL-UP THE GAME Responsibilities Monitor and analyze security events and alerts Triage alerts and determine their severity and priority Correlate and enrich alerts with threat intelligence and other contextual information Respond to incidents and coordinate with other teams as necessary Continuously improve the incident response process and playbooks by incorporating lessons learned and best practices Participate in regular training and exercises to maintain and improve skills Mentor and provide guidance to less experienced SOC analysts, fostering their growth in technical skills and understanding of security best practices Lead initiatives to enhance security monitoring processes, focusing on automation, efficiency, and proactive threat detection Qualifications 5+ years of experience in a SOC or similar security operations role Strong understanding of the threat landscape and common attack vectors Familiarity with common security tools and technologies Excellent analytical and problem-solving skills Strong communication and collaboration skills Ability to work well under pressure and manage multiple priorities Desirable: knowledge of Splunk and Microsoft Security tools Desirable: Python development knowledge

We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a dynamic engineer with working experience in SOC-level functional verification and strong understanding of AXI and High-speed IO protocols like PCIe and USB You should have a passion for working with the best of the brains in the industry in developing end to end solutions and deploying them at our premier customer base Your technical excellence, analytical skills, coupled with strong communication and interpersonal skills, make you a valuable asset to any team You excel in communication, teamwork, and multitasking, and have experience working in cross-functional, multi-site environments, What Youll Be Doing: Working closely with a world-class R&D team, youll be at the center of developing and bringing an end-to-end solution to our wide variety of customers in the domain of Silicon Lifecycle Management (SLM), Working closely with customers, you will bring the detailed requirements into the factory to enable R&D for a strong, robust, and successful product development, Working closely with product development team, you will validate and end-to-end solution both internally (before shipment) as well as in customer environment, Driving the deployment and smooth execution of SLM solutions into customersprojects, Enabling customers to realize the value of silicon health monitoring throughout the lifecycle of silicon bring-up, validation, through in-field operations, The Impact You Will Have: Enhancing SynopsysSilicon Lifecycle Management (SLM) IP portfolio and end-to-end solution, Driving the adoption of SynopsysSLM solutions at premier customer base worlwide, Influencing the development of next-generation SLM IPs and solutions, What Youll Need: BSEE/MSEE in Electrical Engineering, Computer Engineering, or related field, 4+ years of hands-on experience with SoC-level functional verification or Design-for-Test (DFT) or both, Good knowledge of AXI, APB Background in verification, with at least sub-system level verification Debugging abilities to identify issues in functional verification, Knowledge of DMA, ideally should have verified a sub-system with DMA Knowledge of High-speed IO sub-systems like PCIe and USB A thorough understanding of memory mapping concepts is essential, End to end knowledge of how transactions/data flow between the HSIO interface to/from memory Knowledge and experience with Memory BIST/DFT/ATE/SLT/any other test solutions Ability to evaluate technical suggestions from customers and work with internal teams (product management/R&D) to make decisions Customer facing experience is a plus educating/guiding customer on technical details of a solution Good to have: Hands-on debug experience of silicon is a plus Some programming experience to write/debug simple drivers in C Detailed knowledge of the PCIe and USB protocols Architecture/micro-architecture experience Working with FPGAs The Team Youll Be A Part Of: As part of the Silicon Lifecycle Management (SLM) solutions team, you will collaborate with global R&D teams to develop world-class IPs and end-to-end solutions to address silicon health issues at premier data center, AI, and automotive customers Our team is dedicated to bringing solutions to enhance the life of a silicon anywhere it belongs,

We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a highly experienced and motivated professional with a solid background in SoC RTL Design With over 12 years of experience, you have honed your skills in RTL Design, Lint, CDC, RDC, Synthesis, and Constraints Development You possess a deep understanding of design concepts, ASIC flows, and stakeholder management Your technical expertise allows you to debug and diagnose violations and errors, set up flows and methodologies for RTL Signoff tools, and develop timing constraints You are an effective leader, capable of managing and growing a team, providing continuous feedback, and improving the quality of deliverables Your excellent communication skills help you interact with customers, peers, and management to understand needs, report status, and resolve issues efficiently, What Youll Be Doing: Manage and lead a team of 7-8 SoC/Subsystem RTL Design Engineers for various customer engagements, Work with Synopsys customers to understand their needs and define RTL Signoff and design scope and activities, Lead the team to perform various RTL Design and Signoff activities for SoC Subsystems such as SoC u-Architecture and Integration, RTL Design (Verilog/SystemVerilog), Lint, CDC, RDC, Synthesis, Constraints Development, Assist and mentor the team in day-to-day activities and grow the capabilities of the RTL Design team for future assignments, Review various results and reports to provide continuous feedback to the team and improve the quality of deliverables, Report status to management and provide suggestions to resolve any issues that may impact execution, Understand the complexity and requirements of RTL Quality Signoff and propose resource requirements to complete the activities, Work with peers to improve methodology and improve execution efficiency, Collaborate with other Synopsys teams including BU AEs and Sales to develop, broaden and deploy Tools, Train the team in design concepts and root-cause analysis, The Impact You Will Have: Drive the successful delivery of SoC Subsystems by leading a skilled team of RTL Design Engineers, Enhance the quality and efficiency of RTL Design and Signoff processes through continuous feedback and methodology improvements, Ensure customer satisfaction by understanding their needs and delivering high-quality solutions, Contribute to the growth and development of the RTL Design team, expanding their capabilities for future projects, Support Synopsysreputation as a leader in chip design and verification through successful project execution, Foster collaboration and innovation within the team and across different Synopsys departments, What Youll Need: E/B Technical expertise in various aspects of RTL Design and Signoff: LINT, CDC, RDC, Technical expertise on setting up flows and methodologies for quick deployment of RTL Signoff tools, Technical expertise in debugging and diagnosing violations and errors, Technical expertise in developing timing constraints and running preliminary synthesis for timing constraints check and area estimation, Ability to lead and manage a team to perform RTL Signoff on complex SoC/Subsystem, Experience with planning and managing various activities related to RTL Signoff and Design, Strong understanding of design concepts, ASIC flows, and stakeholders, Good communication skills, Who You Are: A proactive leader with excellent managerial skills, A team player who can mentor and guide engineers, An effective communicator who can interact with customers and stakeholders, A problem-solver with a keen eye for detail, An innovator who continuously seeks to improve processes, The Team Youll Be A Part Of: As part of the System Solutions Group (SSG), you will lead a team of experts in various Synopsys technologies to deliver architecture, design, verification, implementation, tools, and methodology to enable our customers to complete their most challenging SoC Design projects Our work spans from sub-blocks to full turnkey end-to-end SoCs Our customers range from start-ups to industry leaders, commercial companies, and government agencies, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,

Alternate Job Titles: Digital IP Verification Engineer IP Methodology Engineer ASIC Methodology Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a seasoned professional with a strong background in electronics or electrical engineering, holding a Bachelor's or Master's degree from a reputed university With 6-10 years of experience in ASIC/SoC/IP Methodology, you possess a deep understanding of Synopsys implementation and infrastructure tools such as coreConsultant, coreAssembler, SpyGlass/VC-SpyGlass, Fusion Compiler/Design Compiler, Prime Time, Formality, TestMax Manager, TCM, Verdi, and VCS Your proficiency in scripting languages like TCL, Perl, or Python complements your technical expertise You excel in multi-clock designs and understand Clock-Domain-Crossing principles You are an effective communicator, a collaborative team player, and a problem-solver who thrives in dynamic environments, What Youll Be Doing: Create and support innovative Design Methodologies by leveraging feedback from our EDA and Digital IP teams, Integrate Methodologies into the development infrastructures of the Digital IP teams and demonstrate successful results, Support and maintain our regression infrastructure to manage changes and revise methodologies regularly, Test a range of Digital IPs through our Methodologies centered around Synopsys EDA tools, Collaborate with various teams to improve methodologies, enhancing both team and customer experiences, Develop and manage infrastructures, processes, methodologies, and checklists for the SG Digital IP Controllers, The Impact You Will Have: Enhance the efficiency and effectiveness of Digital IP development processes, Ensure high-quality and robust Digital IP products through rigorous methodology testing, Improve customer satisfaction by delivering superior Digital IP solutions, Drive innovation in design methodologies, contributing to Synopsys' leadership in the industry, Facilitate seamless integration of methodologies into development infrastructures, optimizing workflows, Support the continuous improvement of regression infrastructures, ensuring up-to-date methodologies, What Youll Need: Bachelors or Masters degree in electronics or electrical engineering or equivalent from reputed universities, 6-10 years of relevant experience in ASIC/SoC/IP Methodology, Proficiency in Synopsys implementation and infrastructure tools (coreConsultant, coreAssembler, SpyGlass/VC-SpyGlass, Fusion Compiler/Design Compiler, Prime Time, Formality, TestMax Manager, TCM, Verdi, VCS), Familiarity with multi-clock designs and understanding of Clock-Domain-Crossing principles, Proficiency in scripting languages (TCL, Perl, Python), Who You Are: You are an effective communicator with strong collaboration skills You have a knack for problem-solving and possess a systems-level thinking approach Your ability to write code in various scripting languages enables you to develop and manage complex infrastructures and methodologies efficiently, The Team Youll Be A Part Of: You will be joining the Synopsys IP Group Digital Methodology team, a dynamic and innovative group focused on designing, developing, and managing infrastructures, processes, and methodologies for Digital IP Controllers This team thrives on collaboration, continuous improvement, and delivering high-quality solutions to meet the evolving needs of our customers, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,

Job Purpose and Impact The Chartering Vessel Operator is responsible for the coordination and execution of moderately complex freight trade activities In this role, you will ensure the coordination of all ocean going vessel voyage processes in strict compliance with maritime law, including data management, reporting and analysis on profit and loss results You will partner closely with the commercial team internally and external counterparties, including owners, charterers, masters, and agents with a main focus on customer service and relationships, Key Accountabilities Execute end to end freight contracts, applying the defined contractual terms to optimize the profit of the sea voyage, Analyze risk factors when moving shipments and use discretionary authority to evaluate and make reactive changes to maximize profit and loss, follow through with tracking and the direction of vessel movements to optimize speed, product quantity and fuel to maximize voyage results, Monitor vessels within a region for specific customers with a full grasp on specific customer requirements, Support the commercial team on voyage estimates by the evaluation of cargo quantity, consumptions and other costs, analysis of voyage data and the analysis to improve trade activities, Ensure all compliance risks are analyzed and acted proactively to avoid, Ensure review of operational metrics and maintain accurate controls and delivery following the established freight execution processes, Maintain established relationships with customers, clients, suppliers and other business partners, such as ship broker, master, vessel owners, port agents and supervisory companies, Independently solve moderately complex issues with minimal supervision, while escalating more complex issues to appropriate staff, Other duties as assigned Qualifications Minimum Qualifications Bachelor's degree in a related field or equivalent experience Minimum requirement of 2 years of relevant work experience Typically reflects 3 years or more of relevant experience, Preferred Qualifications Deep knowledge of Hague Visby rules Experience managing and planning vessel operations, understanding ship specific and port operations Experience analyzing legal contracts

About the Role : We are seeking a talented Implementation Engineer to join our dynamic team. The successful candidate will be responsible for leading and executing Synthesis and STA for complex AI SOC with multi-mode and multi power domain design, ensuring the quality and reliability of our products.This is what you are responsible for : - Synthesis and STA (static timing analysis).- Ability to optimize designs for best in class in low power and high performance with logically equivalent RTL.- Professional experience with ECO implementation, both functional and timing closure.- Experience with multi-clock, multi-power domain designs and multi-mode timing constraints.- Familiarity with DFT insertion.- Familiarity with simulation, debugging tools, and working closely with Design teams.- Ability to collaborate with different functional teams like RTL Design, DFT and Physical design.- Showcase your deep understanding of the following physical design concepts/constraints: floor-planning, placement, congestion, and setup/hold timing closure. Necessary Qualifications : - Bachelor's or Master's degree in Electronics, Computer Science Engineering, or a related field- Minimum of 5 to 7 years of experience in Implementation flows/ Synthesis and STA.- Experience with Cadence, Synopsys and Mentor tools- Experience with Verilog and VHDL.- Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks (UPF/CPF/CLP)- Formal verification for RTL 2 gates and gates2gates- Conformal ECO for doing complex functional ECOs.- Low power synthesis on smaller blocks and subsystems using DC/Genus- Physical Aware synthesis - Writing Timing Constraints sub-blocks and Top level.- Flow Automation and Scripting using TCL and Python or Perl.

Microcontroller Device Driver Software development and validation for various peripherals of Infineon s microcontrollers based on ARM cortex M0, M4 (eg Ethernet, USB, UART,CAN, SPI, I2C, LIN, Flash, Timers, PWM, Lighting systems, Human Machine Interface, SDMMC etc) Application/UI development in Eclipse environment Author architecture, design, test specifications and customer documents Participate in software requirements analysis and ambiguity resolution Provide technical solutions to customer change requests Conceive and develop validation infrastructure for topics in own responsibility Liaise with Application engineers on a need basis Education: Bachelors / Master Degree in Computer Science, Electrical/Electronic Engineering Experience: 1-2 years industry experience Proficiency in OOPS, C++, STL, data structures, algorithms and programming concepts Experience in developing C++ based models for the virtual platform of a SoC Experience in developing and debugging skills using popular IDEs/debuggers (eg Keil) Experience in SDLC Good in any unit test tools Knowledge about code generation tools from specification using scripts or any tools is desirable Experience in scripts (Python/mako/Perl/Windows) Good at understanding the features from specification and drawing various test scenarios for product specification Excellent analytical Areas of Responsibility: Good understanding of ARM / 80x51 controllers Develop/enhance behavioral/functional models in C++ for 80x51 or ARM based Develop regression test suites using C Debug and fix the change requests/bugs Follow Agile Scrum methodology for the development Automated code generation from the specification Acquire knowledge on new topics and share the knowledge with the team Work with the team members on innovation related activities

Microcontroller Device Driver Software development and validation for various peripherals of Infineon s microcontrollers based on ARM cortex M0, M4 (eg Ethernet, USB, UART,CAN, SPI, I2C, LIN, Flash, Timers, PWM, Lighting systems, Human Machine Interface, SDMMC etc) Application/UI development in Eclipse environment Author architecture, design, test specifications and customer documents Participate in software requirements analysis and ambiguity resolution Provide technical solutions to customer change requests Conceive and develop validation infrastructure for topics in own responsibility Liaise with Application engineers on a need basis Education: Bachelors / Master Degree in Computer Science, Electrical/Electronic Engineering Experience: 1-2 years industry experience Proficiency in OOPS, C++, STL, data structures, algorithms and programming concepts Experience in developing C++ based models for the virtual platform of a SoC Experience in developing and debugging skills using popular IDEs/debuggers (eg Keil) Experience in SDLC Good in any unit test tools Knowledge about code generation tools from specification using scripts or any tools is desirable Experience in scripts (Python/mako/Perl/Windows) Good at understanding the features from specification and drawing various test scenarios for product specification Excellent analytical Areas of Responsibility: Good understanding of ARM / 80x51 controllers Develop/enhance behavioral/functional models in C++ for 80x51 or ARM based Develop regression test suites using C Debug and fix the change requests/bugs Follow Agile Scrum methodology for the development Automated code generation from the specification Acquire knowledge on new topics and share the knowledge with the team Work with the team members on innovation related activities

Candidate should have working experience with AMS Verification on multiple SOC s or sub-systems. One should have proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools. Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as we'll as analog circuit basics, with previous analog design experience a plus. Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus. Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected. Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus. Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment. Job Description Behavioral modeling: Verilog, Wreal or SV-RNM -Full AMS Verification for SoC or IPs -Full Test plan preparation as per the dynamics of product specifications - Full Dealing challenges with AMS methodologies of Cadence: irun/xrun or Synopsys: XA-VCS or Mentor Eldo ADMS -partial Testcase Debug & proposing new scenarios - Partial Handling project dynamics on scope, schedule and effort - coming up with alternative verification plans, Mentoring Junior engineer - Partial Ability to lead MSV projects independently Drive enhancements in known methodologies You are best equipped for this task if you have: Bachelors with 5+ years or Masters with 4+ years of experience Analog: functional spec understanding of standard power management blocks, clock circuits and data converters. Loop analysis is an added advantage HDL/HVL: Verilog/Verilog-ams, SV/UVM added advantage Tools: Cadence Xcelium + spectre/ Synopsys XA-VCS/ Mentor Eldo ADMS Automation: Perl/python/shell Schedule and result oriented execution mindset, flexible in working as per the project scope needs, Exploring and experimentation for continuous methodology improvements Ability to drive projects and debug independently.

KEY EXPERTISE : - Seasoned ASIC Front End leader with 20 years of cross domain experience ranging from architecture, uArch, IP/Sub- systems/SOC/ chiplets design/integration, RTL coding, Synthesis, CDC, timing, power analysis, system/IP verification, Silicon Bring up. - Proven track record of leading the design and development of complex IPs, sub-systems, chiplets for SOCs in the multiple domains like PCIE, USB, UCIE, ARM/x86 CPUs, RISC-V, VPU/NPU, GPU, LSIO, NOC, Fabrics, AMBA buses, DRAM, SD/SDIO/eMMC etc. Responsible for defining the technical direction of ASIC designs and collaborating with cross- functional teams to ensure successful ASIC implementation. - Demonstrated strong leadership, project timelines & resources management and team management skills, and the ability to influence the technical strategy of the organization. - Familiar with ASIC verification methodologies, DFT, Physical design and board design which help in influencing cross functional teams in getting desired results. - Excellent execution capabilities to handle multiple domains in multiple projects simultaneously. - Delivered superior results through team collaboration and diversity of thought. Always open to learn new technologies to grow in technical breadth and depth. - Managed development of multiple sub-systems and IPs designed from scratch for Intel IOT (Elkhart Lake), Edge (Reefbay), dVPU/NPU (Arrow LakeR), GPU (DMR-D), Media (MTL-D), Smart NIC (Altera NIC), Palm Ridge, Mount Morgan IPU SoCs which are executed in advanced technology nodes of both Intel (18A, 3nm, 5nm) and TSMC (N3e, N5, N6). - Have hands on experience in chiplets, Sub-systems and IP development (micro-architecture development, 3rd party IP integration (Synopsys, Verisilicon. SiFive RISCV, ARM cores etc.,), RTL implementation, synthesis, static timing analysis, Power analysis, system/IP level verification, FPGA emulation, Si bring-up) and SoC integration flows and methodologies. - Led 30+ engineer design team and have good experience in working with cross-functional teams and cross BU teams across multiple geos, resulting in good collaboration and accelerated time to market. - Led IP development (RTL design, Lint, CDC, Synthesis, timing, unit level and system level verification) of various IPs in Nvdia Tegra SoC processors (from first generation [APX] to ninth generation [Xavier]) and Cisco NIC chips. - Have good working experience on low power design methodologies (clock gating, power gating, multi-vt and DVFS) used in mobile SoCs. - Designed couple of modules in Tegra SoC like DMA engine, SD/SDIO/eMMC5.2 host controller and bus-bridges for Nvidia proprietary buses. Worked on architecture, micro architecture, RTL design and timing analysis. Familiar with automotive electronics ISO26262 safety requirements. - Was Executive member from Nvidia in SD card org and JEDEC (eMMC) forum. Participated in SD/SDIO4.x, SD host4.x and eMMC5.x specification development. - Working experience with cross functional teams like back end, analog I/O pad and SW teams to ensure IP requirements are met at each stage. Have working experience in developing tree build and regression infrastructure. - Have hands on experience in ASIC verification also - Test Planning, Develop Directed, Random and System-level (soc level) Test Cases; Design Test Bench using System Verilog; Develop Random Test environment; Execute Code Coverage & Analyse Reports, Execute Gate-level Simulations; Execute Functional & Regression Tests. - Good Team Player : Participated and lead the effort of SD4.x/eMMC5.x host controller design and verification. Detail oriented go- getter with Fast Learning Curve and strong analytical, decision making, problem solving, visualizing, negotiating, communication & interpersonal skills. - Mentored engineers, designed IP/SS schedules with proper staging plan with cross team dependencies, identified and solved technical issues, and ensured development of high-quality products.

Performance modelling and evaluation of ACAP workloads to eliminate bottlenecks as early as possible and guide the architecture of future generation devices. This is a challenging role in the FPGA Silicon Architecture Group in AECG business unit of AMD in Hyderabad. ABOUT THE TEAM: AECG group in AMD designs cutting edge FPGAs and Adaptable SOCs consisting of processor subsystems and associated peripherals, programmable fabric, memory controllers, I/O interfaces and interconnect. KEY RESPONSIBILITIES: Modelling and simulation of workload dataflow networks and clock accurate SOC components. Performance analysis and identification of bottlenecks Quick prototyping, long-term design decisions, and exploring novel architectures Enhancement of the existing tools and knowledgebase Collaborating with architects in the development of next generation devices Collaborating with customer facing teams to identify scope of optimization for future market scenarios Breaking down system level designs into simpler dataflow models and identify bottlenecks, capture memory and communication overheads Knowledge sharing with teammates through thorough documentation PREFERRED EXPERIENCE: Preferred experience in SOC architecture OR Performance analysis. Strong background in Computer architecture, Hardware performance metrics and bottlenecks. Experienced in modelling and simulation of hardware. Experience in performance profiling, creating experiments to address various use-cases and doing design space exploration. Good to have experience of creation of designs for ACAP devices or HLS. Good communication skills ACADEMIC CREDENTIALS: bachelors or Masters degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent

We are looking for a technical leader to join and lead the SOC Power Modeling team in the AMD Client Computing and Graphics group. This role involves collaboration with many engineering teams including SoC architecture definition, IP design, integration/physical design, verification, platform architecture, software, and firmware. Contributions have a direct impact on the power & performance of AMD s Client products. The Person: The candidate should have strong SOC design process experience from front end to tapeout. The candidate will lead a team working closely with the SOC design teams on RTL and emulation-based power estimation, simulation and design flow extraction. The candidate must be organized, self-motivated and able to work effectively on teams large and small across multiple sites. He or she must be able to prioritize assignments and drive them to completion. Strong verbal and written communication skills are essential for driving technical discussions to successful and actionable outcomes. Key Responsibilities: Team leader for Hyderabad based power modeling group, work with management to define department objectives and growth plans. Make recommendations to improve processes or procedures as appropriate. Implement changes to engineering processes based on new technologies or industry standards. Work with department management on recruiting, hiring, training, and team e valuations . Work with frontend RTL, DFT, Synthesis, and Physical design teams in the development of power intent (UPF) design at SoC level. Lead team with power estimates during the pre-silicon design process using Power Artist/PTPX emulation environments and ensure power objectives and goals are met. Work with RTL and physical design teams to scientifically assess and manage tradeoffs with impacts of power management options such as, but not limited to clock and power gating, device type mix and physical implementation options. Track IP power development through the design cycle ensuring it meets power budgets - leakage/dynamic at every milestone. Improve power design flows in areas of power modeling, clock power analysis, structural power validation, IP power intent. Work with design verification in validating low power design features at SoC and IP level. Preferred Experience Extensive experience with Synopsys EDA tools, particularly PtPx/Power Artist. Detailed understanding of hardware emulation process, stimulus and EDA flow data extraction. Ability to define data reporting and requirements needs using EDA flows, Tcl and Python based scripting. Ability to work independently and lead a world-wide team. Excellent communication skills, written and verbal skills Academic Credentials PhD or Master of Science degree in Electrical Engineering, Computer architecture, or Computer Science. 10+ years of experience.

We are looking for an adaptive, self-motivative Synthesis/PD/STA engineer to join our growing team. As a key contributor, you will be part of a team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The Physical Design Engineering team furthers and encourages continuous technical innovation to showcase successes as we'll as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and physical design in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects for the new features to be implemented in layout End-to-end RTL to GDS implementation of complex IPs and supporting the SOC customers Working with RTL team to resolve timing and congestion issues Build and develop methodology to converge multiple PNR blocks from RTL to GDS Analyze design metrics and make implementation choices to optimize PPA PREFERRED EXPERIENCE: ASIC design flow and direct experience with ASIC design in sub-7nm technology nodes Circuit timing/STA, and practical experience with Prime Time or equivalent tools Low power digital design and analysis Expertise in synthesis and physical design flows Modern SOC tools including Synopsys Fusion compiler, Primetime and Redhawk TCL, Perl, Python scripting Strong verbal and written communication skills Ability to organize and present complex technical information Fluent in working with Linux environment Mimimum 6 years of industry experience ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Embedded Microcontrollers Development Microcontroller Device Driver Software development and validation for various peripherals of Infineon s microcontrollers based on ARM cortex M0, M4 (eg Ethernet, USB, UART,CAN, SPI, I2C, LIN, Flash, Timers, PWM, Lighting systems, Human Machine Interface, SDMMC etc) Application/UI development in Eclipse environment Author architecture, design, test specifications and customer documents Participate in software requirements analysis and ambiguity resolution Provide technical solutions to customer change requests Conceive and develop validation infrastructure for topics in own responsibility Liaise with Application engineers on a need basis Education: Bachelors / Master Degree in Computer Science, Electrical/Electronic Engineering Experience: 1-2 years industry experience Proficiency in OOPS, C++, STL, data structures, algorithms and programming concepts Experience in developing C++ based models for the virtual platform of a SoC Experience in developing and debugging skills using popular IDEs/debuggers (eg Keil) Experience in SDLC Good in any unit test tools Knowledge about code generation tools from specification using scripts or any tools is desirable Experience in scripts (Python/mako/Perl/Windows) Good at understanding the features from specification and drawing various test scenarios for product specification Excellent analytical Areas of Responsibility: Good understanding of ARM / 80x51 controllers Develop/enhance behavioral/functional models in C++ for 80x51 or ARM based Develop regression test suites using C Debug and fix the change requests/bugs Follow Agile Scrum methodology for the development Automated code generation from the specification Acquire knowledge on new topics and share the knowledge with the team Work with the team members on innovation related activities

Microcontroller Device Driver Software development and validation for various peripherals of Infineon s microcontrollers based on ARM cortex M0, M4 (eg Ethernet, USB, UART,CAN, SPI, I2C, LIN, Flash, Timers, PWM, Lighting systems, Human Machine Interface, SDMMC etc) Application/UI development in Eclipse environment Author architecture, design, test specifications and customer documents Participate in software requirements analysis and ambiguity resolution Provide technical solutions to customer change requests Conceive and develop validation infrastructure for topics in own responsibility Liaise with Application engineers on a need basis Education: Bachelors / Master Degree in Computer Science, Electrical/Electronic Engineering Experience: 1-2 years industry experience Proficiency in OOPS, C++, STL, data structures, algorithms and programming concepts Experience in developing C++ based models for the virtual platform of a SoC Experience in developing and debugging skills using popular IDEs/debuggers (eg Keil) Experience in SDLC Good in any unit test tools Knowledge about code generation tools from specification using scripts or any tools is desirable Experience in scripts (Python/mako/Perl/Windows) Good at understanding the features from specification and drawing various test scenarios for product specification Excellent analytical Areas of Responsibility: Good understanding of ARM / 80x51 controllers Develop/enhance behavioral/functional models in C++ for 80x51 or ARM based Develop regression test suites using C Debug and fix the change requests/bugs Follow Agile Scrum methodology for the development Automated code generation from the specification Acquire knowledge on new topics and share the knowledge with the team Work with the team members on innovation related activities