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5.0 - 7.0 years
0 Lacs
bengaluru, karnataka, india
On-site
Responsibilities Develop emulation build workflows and infrastructure in collaboration with RTL, verification, validation and SW teams Build and Deliver emulation and prototyping models from RTL on targeted to industry standard emulation and prototyping platforms like Palladium, Protium or ZeBu Proficiency in setting up a Bare Metal compile flow with Processor tool chains Compiler, Assembler, Linker and ROM / Memory images generation Bring up and debug PCIe, USB, Ethernet, DDR and generic SOC interfaces using standard debug tools like JTAG, and Waveform dump Build and execute emulation bring-up test plans to ensure quality of the released models Use strong analytical & problem-solving skills...
Posted 1 day ago
4.0 - 12.0 years
3 - 15 Lacs
ahmedabad, gujarat, india
On-site
IP verification Using SV/UVM SOC Verification using C/SV Third Party VIP Integration Interconnect Protocols: AHB, AXI, APB SOC Interfaces: GPIO, SPI, I2C, UART (4+) High Speed Serial Interfaces: PCIe Gen 3/4 or USB or MIPI (7+) Memory Interfaces: DDR or HBM I/O (10+) Coverage Closure: Code, Functional and Toggle Tools: Synopsys VCS or Cadence Incsive Technical Documentation: Testbench Specification, Test Plan Specification Foundry Porting Experience: Technology Library Conversion Related Changes Verification
Posted 2 months ago
4.0 - 12.0 years
3 - 15 Lacs
ahmedabad, gujarat, india
On-site
IP verification Using SV/UVM SOC Verification using C/SV Third Party VIP Integration Interconnect Protocols: AHB, AXI, APB SOC Interfaces: GPIO, SPI, I2C, UART (4+) High Speed Serial Interfaces: PCIe Gen 3/4 or USB or MIPI (7+) Memory Interfaces: DDR or HBM I/O (10+) Coverage Closure: Code, Functional and Toggle Tools: Synopsys VCS or Cadence Incsive Technical Documentation: Testbench Specification, Test Plan Specification Foundry Porting Experience: Technology Library Conversion Related Changes Verification
Posted 2 months ago
4.0 - 12.0 years
3 - 15 Lacs
ahmedabad, gujarat, india
On-site
IP verification Using SV/UVM SOC Verification using C/SV Third Party VIP Integration Interconnect Protocols: AHB, AXI, APB SOC Interfaces: GPIO, SPI, I2C, UART (4+) High Speed Serial Interfaces: PCIe Gen 3/4 or USB or MIPI (7+) Memory Interfaces: DDR or HBM I/O (10+) Coverage Closure: Code, Functional and Toggle Tools: Synopsys VCS or Cadence Incsive Technical Documentation: Testbench Specification, Test Plan Specification Foundry Porting Experience: Technology Library Conversion Related Changes Verification
Posted 2 months ago
2.0 - 7.0 years
3 - 8 Lacs
noida, hyderabad, bengaluru
Work from Office
About Us: Silcosys Solutions Private Limited is a pioneer in semiconductor innovation, committed to delivering cutting-edge analog design solutions that power the future of technology. If you are eager to work on impactful projects and advance your expertise, we invite you to join our dynamic team. Job Description: As an RTL Design Engineer, you will be responsible for designing and implementing high-quality RTL code for complex digital blocks and subsystems. You will collaborate with architects, verification, and physical design teams to create designs that meet functional, performance, and power requirements. Responsibilities: 1. Develop RTL designs for digital IPs, subsystems, and SoCs ba...
Posted 3 months ago
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