18.0 - 28.0 years

80 - 90 Lacs

Hyderabad, Pune, Bengaluru

Work from Office

Define and drive SoC Architecture with strong PPA (Power, Performance, Area) trade-off analysis. Lead IP selection and integration strategies for performance-driven designs. Architect and review Mixed Signal Designs and Multi-core Processor Subsystems. Collaborate across RTL to Physical Design teams ensuring sign-off quality deliverables. Coordinate with Physical Design (PD) teams for successful Tapeout activities. Ensure architectural alignment with foundry node requirements (across 28nm, 16nm, 7nm, etc.). Minimum 18+ years of experience post Engineering degree in EE or EC. Proven expertise in SoC design methodologies and architecture definition. Deep understanding of RTL development, integration, and backend handoff. Strong cross-functional collaboration experience with analog, PD, DFT, and software teams. Exposure to foundry-specific constraints and best practices across technology nodes.

Posted 2 months ago

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