Principal DFT Engineer NXP Semiconductors

5.0 - 10.0 years

0 Lacs

karnataka

On-site

As a Senior DFT engineer with over 10 years of experience in SoC DfT implementation and verification of scan architectures, JTAG, memory BIST, ATPG, and LBIST, you will play a crucial role in ensuring the design quality and functionality of complex semiconductor devices. Your educational background should include a BE/ME/B.Tech/M.Tech degree from reputed institutes with a 1st class degree and a minimum of 5 years of relevant industry experience. Your expertise in Verilog/VHDL RTL coding and proficiency in using Mentor DfT tools and Cadence tools will be essential for success in this role. You will be responsible for tasks such as scan insertion, JTAG, LBIST, ATPG, DRC, and coverage analysis, as well as simulation debug with timing/SDF. It is expected that you have hands-on experience working on at least one SoC project from start to end. In addition to technical skills, you should possess qualities such as proactiveness, collaboration, and attention to detail. The ability to exercise independent judgment, debug issues, and identify root causes of simulation failures is crucial for this position. Strong interpersonal skills, effective communication (both oral and written), and self-motivation are also key attributes that will contribute to your success. At NXP in India, we value individuals who exhibit curiosity, a desire to understand the underlying mechanisms of their work, and a continuous drive for learning and improvement. If you are someone who thrives in a dynamic and challenging environment, where your contributions can make a significant impact, we encourage you to apply and join our team.,

Posted 1 day ago

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DFT Engineer Shashwath Solution

6.0 - 8.0 years

25 - 40 Lacs

Bengaluru

Work from Office

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills.

Posted 2 months ago

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