STA (SI30FT RM 3520) Sourceright Technologies

3.0 - 8.0 years

6 - 8 Lacs

hyderabad, telangana, india

On-site

Doing STD cells characterization work (max up to 40% of time) , Static timing analysis (60%) Able to characterize basic STD Cells Writing ARC for STD cell char (using primeLib , Silicon smart) lib QA check Circuit understanding block wise , Full chip level Static timing Analysis of DRAM block wise , top level analysis , cell level analysis Writing constraints , analysing the STA reports Reporting violations to Design team , ownership for closure Parasitic modelling and assisting in design validation, reticle experiments and required tape-out revisions Performing verification processes with modelling and simulation using industry standard simulators Contributing to cross group communication t...

Posted 2 weeks ago

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Analog Modeling,Verification and characterization Senior Lead Engineer Qualcomm

3.0 - 8.0 years

3 - 8 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

General Summary: Join Qualcomm's Hardware Engineering team where innovation meets silicon. In this role, you will contribute to the design and characterization of advanced mixed-signal IPs such as DDRIOs, SERDES, ADCs, DACs, and PLLs. This position focuses on developing Verilog behavioral models and performing accurate timing and power characterization using industry-standard tools. You'll be collaborating with cross-functional teams to ensure high-quality deliverables for Qualcomm's world-class chipsets. Key Responsibilities: Develop behavioral models (Verilog, Verilog-MS/real, SystemVerilog) for mixed-signal analog IPs such as DDR-MSIP, DDRIOs, SERDES, ADC/DACs, and PLLs. Perform timing an...

Posted 3 months ago

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