636 Silicon Jobs - Page 26

We are seeking a highly motivated Product Engineer who is passionate about advancing technology and solving complex design challenges. You are innovative, dependable, and have a strong technical background in transistor-level analysis. With a minimum of 5 years of hands-on experience, you possess exceptional expertise in debugging circuit-level issues for SRAM, RF, ROM memories, and Standard Cells. You have a deep understanding of static timing concepts and CMOS engineering fundamentals, coupled with proficiency in TCL or other scripting languages. Your excellent communication and social skills enable you to collaborate effectively with cross-functional teams, including R&D, Field AEs, Sales, and Marketing. You thrive in a dynamic environment, driving new products and features that exceed customer expectations and contribute to the success of Synopsys. What You ll Be Doing: Drive new products and new product features that exceed customer needs. Work with R&D to enable timely implementation of new products and features, and important bug fixes. Provide consultation to prospective users and/or product capability assessment and validation. Provide tool trainings to customers and Field AEs. Provide technical expertise to sales staff through sales presentations and product demonstrations. Assist the sales staff in assessing potential application of company products to meet customer needs and preparing detailed product specifications for the development and implementation of customer applications/solutions. The Impact You Will Have: Influence technology and solution roadmaps through collaboration with R&D. Ensure overall consistency of end-to-end design and analysis flow to meet customer needs. Drive new tool evaluations and help customers with the adoption and continuous usage of our tools. Enable Chip Design customers to achieve optimal Timing, Power, and Characterization goals. Enhance predictability and productivity for designers through advanced tool features. Identify and resolve design issues early-on, minimizing costly late-stage silicon problems. What You ll Need: BS degree in Electrical Engineering or related field. Minimum of 5 years of recent hands-on experience in transistor-level analysis. Expertise in debugging circuit-level issues for SRAM, RF, ROM memories, and Standard Cells. Proficiency in static timing concepts and CMOS engineering fundamentals. Knowledge of TCL and/or other scripting languages. Who You Are: Innovative and motivated. Dependable and detail-oriented. Excellent communicator and collaborator. Proactive problem solver. Adaptable and eager to learn

Designing and developing high-performance flip flops, latches, multibit flip flops, voltage level shifters, power optimization cells, clock cells, and other complex circuits. Creating and refining environments for post-layout netlist extraction. Applying your expertise in CMOS device characteristics, design rules, latch-up, and electromigration to ensure robust designs. Optimizing digital circuits for better performance, power, and area (PPA). Performing statistical and variation analysis to enhance the reliability of designs. Collaborating with cross-functional teams to integrate designs into larger systems. The Impact You Will Have: Contributing to the creation of cutting-edge semiconductor technologies that power a wide range of applications. Enhancing the performance and efficiency of standard cell circuits, impacting the overall quality of our products. Driving innovation in power optimization and clock cell design, leading to more energy-efficient solutions. Improving the reliability and robustness of our designs through meticulous analysis and optimization. Collaborating on projects that shape the future of technology and influence industry standards. Leveraging your skills to solve complex engineering challenges, contributing to the success of Synopsys. What You ll Need: Experience in Standard Cell Circuit design of high-performance flip flops, latches, multibit flip flops, voltage level shifters, power optimization cells, and clock cells. Strong knowledge and hands-on experience in developing environments and extracting post-layout netlists. Good understanding of CMOS device characteristics, design rules, latch-up, and electromigration. Proficiency in digital circuit design and optimization for better PPA. Hands-on experience in statistical/variation analysis

Designing, implementing, and optimizing CI/CD pipelines for cloud and hybrid environments. Integrating AI-driven pipeline automation for self-healing deployments and predictive troubleshooting. Leveraging GitOps (ArgoCD, Flux, Tekton) for declarative infrastructure management. Implementing progressive delivery strategies (Canary, Blue-Green, Feature Flags). Containerizing applications using Docker & Kubernetes (EKS, AKS, GKE, OpenShift, or on-prem clusters). Optimizing service orchestration and networking with service meshes (Istio, Linkerd, Consul). Implementing AI-enhanced observability for containerized services using AIOps-based monitoring. Automating provisioning with Terraform, CloudFormation, Pulumi, or CDK. Supporting and optimizing distributed computing workloads, including Apache Spark, Flink, or Ray. Using GenAI-driven copilots for DevOps automation, including scripting, deployment verification, and infra recommendations. The Impact You Will Have: Enhancing the efficiency and reliability of CI/CD pipelines and deployments. Driving the adoption of AI-driven automation to reduce downtime and improve system resilience. Enabling seamless application portability across on-prem and cloud environments. Implementing advanced observability solutions to proactively detect and resolve issues. Optimizing resource allocation and job scheduling for distributed processing workloads. Contributing to the development of intelligent DevOps solutions that support both traditional and AI-driven workloads. What You ll Need: 5+ years of experience in DevOps, Cloud Engineering, or SRE. Hands-on expertise with CI/CD pipelines (Jenkins, GitHub Actions, GitLab CI, ArgoCD, Tekton, etc.). Strong experience with Kubernetes, container orchestration, and service meshes. Proficiency in Terraform, CloudFormation, Pulumi, or Infrastructure as Code (IaC) tools. Experience working in hybrid cloud environments (AWS, Azure, GCP, on-prem). Strong scripting skills in Python, Bash, or Go. Knowledge of distributed data processing frameworks (Spark, Flink, Ray, or similar)

* Responsible for functional verification involving coherent and non-coherent IP designs. * Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. * Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. * Developing verification plans and driving functional coverage-driven verification closure of real designs. * Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: * Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. * Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. * Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. * Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. * Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. * Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You ll Need: * B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 5-8 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 4-8 years of relevant experience. * Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. * You will be responsible for functional verification involving coherent and non-coherent IP designs. * Proficiency in writing scripts using Perl, Python, and Shell scripting. Who You Are: * Excellent problem-solving, debugging, and analytical skills. * Strong programming skills and familiarity with object-oriented programming concepts. * Creative and innovative mindset. * Excellent verbal and written communication skills. * A collaborative team player with a passion for functional verification. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Responsible for PCIe/CXL next-gen Controller IP features Customer pre/post sales PCIe/CXL protocol related communication Utilizing advanced design methodologies and tools to achieve high-quality results Mentoring and guiding other engineers, promoting best practices, and fostering a culture of continuous improvement Communicating with internal and external stakeholders to align on project goals and deliverables. What You ll Need: Extensive experience in digital ASIC design and physical aware synthesis. In-depth knowledge of PCIe, CXL , AXI, CHI and similar IO protocols. Proficiency in advanced digital design tools and methodologies. Strong problem-solving skills and the ability to work independently. Excellent communication skills for effective collaboration with diverse teams. Experience of 20+ years in relevant domain. Who You Are: A mentor who fosters talent and encourages innovation. A proactive problem solver who thrives in complex environments. An effective communicator with the ability to convey technical concepts to a broad audience. A team player who values collaboration and diversity.

"> Search Jobs Find Jobs For Where Search Jobs Technical Writer Hyderabad, Telangana, India Apply Now Save Category: Engineering Hire Type: Employee Job ID 10602 Date posted 04/17/2025 Share this job Email LinkedIn X Facebook Alternate Job Titles: Senior Technical Writer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performan ce silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: Energetic, experienced, and organized, you are a writer who thrives in a vibrant environment and is passionate about cutting-edge technology. You have a knack for turning complex technical information into clear, concise, and user-friendly documentation. With a strong background in technical writing within the software or hardware industry, you bring a blend of creativity and precision to your work. You are a team player who can also work independently, and you take pride in delivering high-quality content on time. Your excellent communication and interpersonal skills enable you to collaborate effectively with engineers and other stakeholders. You are always eager to learn and adapt to new technologies, ensuring that your documentation remains relevant and up-to-date. If you care about doing a good job, about details, and about contributing to a dynamic team, Synopsys is the place for you. What You ll Be Doing: Planning, organizing, writing, and editing a variety of customer documentation. Collaborating with engineers to understand product functionalitie s and features. Creating user manuals, reference guides, and online help content in various formats. Ensuring documentation is accurate, clear, and comprehensive. Maintaining and updating existing documentation to reflect product updates. Utilizing authoring tools such as FrameMaker and Oxygen to produce high-quality content. The Impact You Will Have: Empower customers to effectively use and optimize Synopsys products. Enhance user experience through clear and accessible documentation. Support product adoption and customer satisfaction. Contribute to the success of product releases with timely and accurate documentation. Facilitate better communication and understanding between customers and the engineering team. Help maintain Synopsys reputation as a leader in semiconductor IP solutions. What You ll Need: Degree or masters in electronics, science, hardware, computing, software, physics, mathematics, or engineering disciplines. Other technical disciplines considered. 3-5 years of technical writing experience in the software or hardware industry. Excellent problem-solvin g skills with strong logical reasoning. Proficiency with authoring tools such as FrameMaker and Oxygen. Excellent English writing and speaking skills. Who You Are: Excellent communication and interpersonal skills. Energetic and capable of learning new technologies as necessary. Team player with the ability to work independently. Detail-oriente d and committed to delivering high-quality work. Proactive and able to take ownership of projects with minimal supervision. The Team You ll Be A Part Of: You will be part of a dynamic and experienced Technical Publications team that works closely with world-class engineers to create essential customer documentation. Our team is committed to empowering customers worldwide with comprehensive and user-friendly content that enhances their experience with Synopsys products. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Now Save Relevant Jobs Senior Staff Product Engineer, R&D-7683 Aschheim, Germany Engineering Principal Analog Design Engineer Mississauga, Canada Engineering Verdi Internship Hsinchu, Taiwan Interns/Temp

We are seeking a Senior FPGA Verification Engineer to join the Ericsson Silicon organization. In this key role, you will provide strategic leadership to a team of dedicated engineers focused on developing world-class Radio and RAN Compute products. You will lead the FPGA verification team in defining, implementing, and optimizing verification strategies and environments for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, you'll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity, teamwork, and strategic thinking What you will do Lead the definition of advanced verification requirements and strategies for FPGA and/or ASIC designs based on functional specifications and Ericsson development processes. Architect and implement comprehensive verification environments and test cases to execute verification plans, ensuring high-quality deliverables. Analyze and optimize functional and code coverage metrics, driving towards completion targets and continuous improvement. Debug RTL in collaboration with designers, Collaborate with hardware, software, systems, and integration teams to understand overall product requirements and drive strategic and efficient solutions. Champion the continuous improvement of products, tools, and processes, contributing thought leadership and innovative ideas. Produce and oversee the generation of comprehensive verification documentation, ensuring clarity and precision including test procedures and results documentation. Devise test plans that cover functional verification and on target lab verification. Provide mentoring and guidance to team members You will bring 10+ years of experience in FPGA/ASIC verification, including leadership roles. Exceptional knowledge of UVM and SystemVerilog Proven ability to architect and create RTL testbenches from scratch, demonstrating advanced technical skills. Strong knowledge of object-oriented programming and embedded software design and testing. Expertise with modern FPGA device families and tools Experience with scripting languages such as Python, Tcl, shell scripting, etc An analytical and strategic approach with a results-oriented mindset and the ability to deliver under pressure. Excellent English verbal and written communication skills, with the ability to convey complex ideas clearly and persuasively. High self-motivation and the ability to work independently while leading and inspiring teams. A track record of successful cross-team and cross-site cooperation, including leadership roles. A masters degree in Electrical or Computer Engineering or equivalent

We are seeking a seasoned SoC Architect with expertise or significant interest in System Architecture. You have had significant success driving architecture, product roadmaps and product requirements. You are meticulous about Power, Performance and Area while driving schedule and managing cost. This senior role will stretch you as you lead architecture teams in new directions, network with our world-class, patent-holding think-tank, and negotiate amongst design teams, marketing, and business unit executives. THE PERSON: You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: Define product features and capabilities, close architecture, and micro-architecture requirements, drive technical specifications for SoC and IP blocks to meet those requirements, and provide technical direction to execution teams Comprehend the SOC as a complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features, optimizing for performance and power Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements Knowledge sharing and other contributions to Platform & System Architecture As an overall product owner, responsible for architecture analysis and technical solutions for marketing/feature change requests Work closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets, Emulation plans, Pre-Si bug resolution and Performance/Power Verification sign offs Support Post-Si teams for Product Performance, Power and functional issues debug/resolution PREFERRED EXPERIENCE: Outstanding foundation in Systems & SoC architecture, with expertise in one or more of the following: CPU or GPU, Memory sub-system, Fabrics, CPU/GPU coherency, Multimedia, I/O subsystems, Clocks, Resets, Virtualization and Security Experience analyzing CPU, GPU or System-level Micro-Architectural features to identify performance bottlenecks within different workloads Demonstrated expertise in power management microarchitecture, low power design and power optimization, along with power impact at architecture, logic design, and circuit levels Excellent communication, management, and presentation skills. Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies ACADEMIC CREDENTIALS: bachelors or masters degree in related discipline preferred

We are looking for an adaptive, self-motivative EMIR engineer to join our growing team. As a key contributor , you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The EMIR team furthers and encourages continuous technical innovation to showcase successes as we'll as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ time zone s . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Good understanding of IR/Power-Domain-Network signoff at SOC & block level Experience in RHSC tool Good at scripting python/perl/tcl Must have knowledge of Physical Implementation (Synthesis and Place&Route) Effective communication ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering with 5+Yrs of exp.

The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc You are meticulous about Power, Performance and Area while driving schedule and managing cost. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 16+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

About You: You are a talented and dedicated Senior Layout Design Engineer specializing in analog and mixed-signal (A&MS) integrated circuits. You excel in collaborative environments, working seamlessly with cross-functional teams to drive technological innovation. Your meticulous attention to detail and unwavering commitment to quality are hallmarks of your work. You are constantly striving to enhance layout design methodologies and best practices, utilizing your profound knowledge of semiconductor process technologies and industry-standard EDA tools. Your exceptional problem-solving abilities, effective communication, and strong teamwork make you an indispensable asset. What You ll Be Doing: Develop and implement layout designs for A&MS integrated circuits. Optimize layouts using industry-standard EDA tools. Perform physical verification and design rule checks. Participate in Layout reviews and provide feedback. Collaborate with circuit designers on specifications and constraints. Enhance layout design methodologies and best practices. Stay updated with industry trends in A&MS layout design. The Impact You Will Have: Ensure high quality and performance of A&MS integrated circuits. Drive innovation with cutting-edge layout designs. Improve manufacturability and reliability through meticulous design. Contribute valuable feedback during design reviews. Foster continuous improvement in design methodologies. Mentor junior engineers by sharing your expertise.