636 Silicon Jobs - Page 22

Position: Senior QA Engineer Experience: 3+ years Location: Mumbai, Dadar East About Miko: Miko.ai is a Mumbai-based consumer robotics company founded in 2015 by IIT Bombay graduates Sneh Vaswani, Prashant Iyengar, and Chintan Raikar. The company specializes in developing AI-powered educational robots designed to engage, educate, and entertain children aged 4 to 12. Mikos flagship products, such as Miko 3 and Miko Mini, combine conversational AI with interactive learning experiences, aiming to foster cognitive, emotional, and social development in young learners. Miko has a global presence, with offices in Mumbai and Silicon Valley, and its products are available in over 140 countries. The company emphasizes child safety and privacy, ensuring that all interactions are secure and compliant with international standards. Additionally, Miko collaborates with educational content providers to offer a diverse range of learning materials tailored to individual learning paths. For more detailed information about Miko.ai, you can visit their official About the Role: We are looking for Quality Assurance Engineer with 2+ years of experience to join our Quality Assurance team and work with key stakeholders in the organization such as AI and robotics engineers, User Experience designers, product managers and technical program managers to define and implement quality engineering solutions for new features and products ensuring the highest quality of product delivery. Responsibilities: Development of test strategies and creation, execution and verification of test plans via manual testing methodologies for the area of ownership which includes voice and conversation experience, human robot interaction, child focused activities and games. Working alongside the engineering and product teams to maintain and enhance manual and automation test suites to fix bugs and implement new features and modules. Simulate real-world deployments of the products, reproduce customer issues, and perform root cause analysis. Defining and validating quality guidelines and processes for testing and releasing software to production Communicating with multiple teams and coordinating testing efforts and own software quality Requirements: 3+ years of experience working as a Quality Assurance Engineer Expertise in application quality and testing methodologies Experience with some or all testing methodologies: black box, white box, performance, security, integration and UAT. Experience with cross-platform mobile app development tools , technologies and mobile app operating systems - Android, iOS or other mobile platforms Perform functional and linguistic testing to validate grammar, spelling, punctuation, cultural nuances, and translations . Test UI/UX elements for truncation, alignment, and overall readability in the localized language . Evaluate voice AI, speech recognition, and text-to-speech (TTS) outputs for pronunciation accuracy and natural fluency . Collaborate with content, development, and speech engineering teams to resolve localization issues. Execute test cases and exploratory testing for localized features , ensuring cultural relevance in the target market. Identify, document, and report localization defects, providing detailed feedback for improvements . Hands-on experience in UI automation, API testing and should have knowledge in any one programming language preferably Java or Python. Good exposure for testing voice commands and Knowledge of conversational AI . Exposure to smart applications like Alexa or Google will be an added advantage Experience with wireless consumer electronics devices, smart devices, IoT devices is an added plus. Experience with child-focused products, applications and games is added plus

Striim, (pronounced stream with two i s for integration and intelligence), is a unified data integration and streaming platform that connects clouds, data, and applications with unprecedented speed and simplicity to deliver the right data at the right time. Striim is used by enterprise companies to monitor events across any environment, build applications that drive digital transformation, and leverage true real-time analytics to provide a superior experience to their customers. At our company, we believe and expect all of our employees to operate as one with unlimited potential and dignity. Description We are looking for a Software Engineer who is ready to make an impact in realtime data-streaming and large-scale data integration. As a Software Engineer, you will play a pivotal role in designing, implementing, and optimizing the infrastructure that powers our high-performance data streaming platform. This is an exciting opportunity to work with state-of-the-art technologies, collaborate with top-tier engineers, and contribute to the growth of a company that is transforming how businesses harness the power of real-time data. If youre ready to take on complex challenges and drive impactful change, we want to hear from you. Requirements: 2 to 4 years of experience in programming with any one of the object oriented language - Golang / Java / Python / C / C++ . Experience working on Microservices architecture latest distributed systems is a plus Proven professional experience with Cloud platform Knowledge in AWS/GCP/Azure is an advantage Experience with Agile programming methodologies. Ability to thrive in a fast-paced working environment and collaborate with other engineers. Location: Bengaluru Benefits: We offer Competitive salary and pre-IPO stock options Comprehensive health care plans for employees and family members. Gratuity Plan as per the India Gratuity Act Paid Time Off (Annual Leave, Sick Leave, Casual and generous public /bank holidays) Employee Wellness Programs: Access to free online Yoga classes, Gym membership reimbursements, Employee Wellness Assistance Program Sodexo Meal Program Internet reimbursement program Group Term Life Insurance (Go Digit Insurance) Paid Maternity and Paternity leave The chance to contribute to and shape an upbeat, fully engaged culture Our company culture fosters entrepreneurship and nurtures our team members to grow with the company. Come join a Silicon Valley startup focused on delivering a product that s loved by its customers and primed to be a core part of the cloud data stack. We are an equal opportunity employer, and we value diversity at our company.It is in our best interest to continue to foster an environment of diversity, equity, and inclusion to bring the most value to our workforce, customers, and partners. All applicants are considered for employment without attention to race, color, religion, sex, age, marital status, sexual orientation, gender identity, national origin, veteran status, or disability status. For more information on Striims Privacy Policy, click here .

We are looking for a highly skilled Java to join our dynamic development team with 2+ years of experience. This role requires a problem-solving mindset and the ability to work in an agile environment. Responsibilities : Implement APIs and microservices in Java. Deploy serverless solutions using Azure Functions, Logic Apps and API Management. Document integration processes and provide technical support for deployed solutions. Collaborate with cross-functional teams to align technical solutions with business objectives. Monitor and optimize performance using Azure Monitor and Application Insights. Requirements : 2+ years of experience in backend engineering. Proficiency in Java, Spring boot and Azure. Expertise in Azure Functions, Azure Logic Apps or APIM will be a huge plus. Expertise of RESTful APIs, JSON, and XML. Excellent problem-solving and communication skills. Familiarity with cloud integration patterns and practices will be a plus. Knowledge of CI/CD pipelines

We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products including memory compilers, logic cells and custom macros of all types on the bleeding edge of process technology. We have multiple positions at all experience levels. Available Job Responsibilities Design and build memory or circuit blocks at the gate or transistor level Simulate and analyze the circuit design using transistor level simulators Extract the layout and perform post-layout simulations and verification Floorplan physical implementation and layout integration of design components Integrate characterization flow to extract timing and power information Develop scripts to automate characterization flow, simulations, and verification Specify and verify various behavioral and physical memory models Document the design specifications, behavioral description, and timing diagrams Help specify silicon test plan and correlate silicon to simulation data Preferred Skills Good understanding of transistor level circuit behavior and device physics Good understanding of signal integrity analysis, EM/IR analysis, and reliability analysis Proficiency in running simulators, writing automation scripts, and are tools savvy Understanding of memory behavioral and physical models is a plus Expertise in memory circuit design is a plus Understanding of DFT schemes and chip level integration is a plus Good communication, interpersonal, and leadership skills Motivated, self-driven and good at multi-tasking Passion for solving complex problems and willingness to learn

We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products including memory compilers, logic cells and custom macros of all types on the bleeding edge of process technology. We have multiple positions at all experience levels. Available Job Responsibilities Design and build memory or circuit blocks at the gate or transistor level Simulate and analyze the circuit design using transistor level simulators Extract the layout and perform post-layout simulations and verification Floorplan physical implementation and layout integration of design components Integrate characterization flow to extract timing and power information Develop scripts to automate characterization flow, simulations, and verification Specify and verify various behavioral and physical memory models Document the design specifications, behavioral description, and timing diagrams Help specify silicon test plan and correlate silicon to simulation data Preferred Skills Good understanding of transistor level circuit behavior and device physics Good understanding of signal integrity analysis, EM/IR analysis, and reliability analysis Proficiency in running simulators, writing automation scripts, and are tools savvy Understanding of memory behavioral and physical models is a plus Expertise in memory circuit design is a plus Understanding of DFT schemes and chip level integration is a plus Good communication, interpersonal, and leadership skills Motivated, self-driven and good at multi-tasking Passion for solving complex problems and willingness to learn .

Job Description Need to work in collaboration with global design teams across sites. Will be responsible for driving innovation in Analog IP designs. Responsible for design of IPs like Switched capacitor circuits , Voltage regulators, LDO, Current and Voltage reference, High Voltage charge pumps, temperature sensors, oscillators etc using industry standard EDA tools. Should provide technical leadership and mentor junior engineers. Responsible for developing processes and robust design methodology. Help build overall competency in Analog domain. Qualifications Bachelors/ Masters degree in Electrical/ Electronics Engineering with 8+ years of experience in Analog Circuit Design across different technologies. Should have experience in developing analog IPs l

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. 5+ years RTL Design/Hardware Engineering experience or related work experience. Strong Domain Knowledge on RTL design(Verilog/VHDL/System Verilog) , implementation, and integration, micro-architecture & designing cores and ASICs Familiar with the Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc Exposure in scripting (Pearl/Python/TCL) Strong debugging capabilities at simulation, emulation, and Silicon environments Collaborate closely with cross-functional teams to research, design and implement performance and power management strategy for product roadmap Knowledge on Designing low power/power management controller IP blocks including AVS (adaptive voltage scaling), ACD (adaptive clock distribution), on-chip sensor controller Work closely with technology/circuit design team to close IP block specification/requirement. Work closely with verification/physical design team to complete the IP design implementation Support SoC team to integrate low power / power management IP solution into wireless SoC chips and front-end design flows Work closely with system/software/test team to enable the low power feature in SoC products Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. 8+ years RTL Design/Hardware Engineering experience or related work experience. Strong Domain Knowledge on RTL design(Verilog/VHDL/System Verilog) , implementation, and integration, micro-architecture & designing cores and ASICs Familiar with the Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc Exposure in scripting (Pearl/Python/TCL) Strong debugging capabilities at simulation, emulation, and Silicon environments Collaborate closely with cross-functional teams to research, design and implement performance and power management strategy for product roadmap Knowledge on Designing low power/power management controller IP blocks including AVS (adaptive voltage scaling), ACD (adaptive clock distribution), on-chip sensor controller Work closely with technology/circuit design team to close IP block specification/requirement. Work closely with verification/physical design team to complete the IP design implementation Support SoC team to integrate low power / power management IP solution into wireless SoC chips and front-end design flows Work closely with system/software/test team to enable the low power feature in SoC products Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Details: : Intel is a leader in the wireless communication industry, offering products that set the benchmark for performance and innovation. We are seeking a motivated Junior SerDes PHY Integration Engineer to join our team. In this role, you will focus on integrating physical layer components for high-speed SerDes systems, playing a crucial part in ensuring their performance and reliability.Key Responsibilities:SerDes PHY IntegrationsSupport the integration of the physical layer for SerDes systems, including transmitter and receiver architectures, equalization techniques, and signal integrity.Simulation and ValidationAssist in conducting simulations using MATLAB and Python, along with lab testing, to validate the performance and compliance of the SerDes PHY, optimizing it for high-speed data transmission.Calibration TechniquesHelp integrate calibration methods to enhance the performance of the SerDes PHY, ensuring high-quality data transmission.CollaborationWork collaboratively with cross-functional teams, including digital design, hardware, and software, to ensure seamless integration of the PHY layer into the overall SerDes system.DocumentationContribute to maintaining detailed and up-to-date documentation of design specifications, test plans, and results.Problem-SolvingAssist in addressing and resolving technical issues related to the SerDes PHY, ensuring optimal performance.Quality AssuranceSupport the implementation of quality control measures and best practices to ensure the reliability and robustness of the SerDes PHY.Develop SERDES TestsParticipate in the development of comprehensive tests to support integration efforts, including writing scripts for software and firmware in Intel's test environment. Qualifications: Bachelor's degree in Electrical Engineering; a Master's degree in a relevant field is a plus.Passion for lab work, collaboration, and solution development.Familiarity with scripting and programming languages such as C, C#, MATLAB, and Python.Experience in silicon development and SerDes technologies is beneficial.Strong problem-solving abilities and analytical skills.Self-motivated and capable of executing tasks in uncertain environments.Demonstrated ability to contribute effectively in a matrix organization. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Job Details: : 1) Defines, develops, and performs functional validation in SoC power management for GPUs focusing on validation of IP integration, interaction between IPs, and system level features.2) Applies various hardware and software level tools and techniques to ensure validation coverage and that performance, power, and area goals are met. 3) Reviews proposed design changes to assess impact on validation plans, tasks, and timelines. 4) Develops Power Management validation methodologies and Validation plans for SoC power management for GPUs, executes validation plans, and collaborates with engineers for feature verification, troubleshooting and failure analysis. 5) Tests interactions between various GPU features using validation infrastructure. 6) Develops post silicon validation infrastructure (e.g., performance monitors, behavioral checkers, state space coverage) and test environment used in validation testing. 7) Performs silicon debug to identify root causes and resolves all functional and triage failures for SoC Power management in GPUs. 8) Develops content to create or increase specific IP interactions, engages in all phases of the product life cycle and develops and validates content, infrastructure, and bug hunts in multiple environments (emulation, FPGA) to ensure silicon readiness Qualifications: Bachelors or masters degree in computer science, Electrical Engineering, or a related field with 5 to 10 years of experience. Proven experience in SoC validation specifically in Power management areas Test content development with focus on reset/boot/Active Power/Idle Power/ Thermal areas. Strong understanding of server architectures, hardware components, and operating systems (Windows, Linux) Proficiency in programming like C, C++, Python for test automation, debugging, and test content development. Experience with validation, debug tools involving ITP/JTAG, Test content development tools and frameworks (e.g., Jenkins, GDB, WinDbg). Excellent problem-solving skills and attention to detail. Familiarity with version control systems (e.g., Git) and issue tracking tools (e.g., JIRA). Knowledge of industry standards and best practices related to server reset, platform validation, debugging, and test content development. Good team player, Candidate should have excellent interpersonal skills / strong communication and collaboration skills w/ the ability to work effectively in team environment Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Lead the core level pre-silicon functional & performance verification for our next -generation IBM POWER processor core systems offering. Understand the IBM Power ISA and micro-architecture of the processor core, understand and enhance the existing unit and core level verification environment. Develop deep understanding of the processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units of the high performance processor CPU. Hands on debug for core level fails, propose and implement stimulus enhancements and drive improving the debug capabilities for core testbench environments. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of complete processor pipeline stages. Good understanding of computer architecture, including Processor core design specifications,processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units Experience with high frequency, instruction pipeline designs. At least 1 generation of Processor Core silicon bring up experience. In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Knowledge of verification principles and coverage. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

Lead the unit level pre-silicon functional & performance verification of the front end of the pipeline for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for Instruction fetch, Branch Prediction and Instruction Decode units of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 6 years or more experience in functional verification of processors, demonstrating a deep understanding of core units (eg.I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying frontend pipeline units of any CPU architecture. Hands on experience of Branch Prediction techniques. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages.

NVIDIA is seeking a passionate, creative, and highly motivated engineer to work on architectural power estimation for the world s leading GPUs and SOCs. In this position, the responsibility includes development of advanced power models to estimate chip and board power under product driven use cases. You are expected to understand the high-level chip architecture, application use-cases, low power design techniques, process technology aspects which impact dynamic and leakage power, develop the estimation infrastructure, estimate power consumption under various scenarios. You will be working with architecture, design, synthesis, timing, circuit, and post silicon teams to accomplish your tasks. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. Were united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as the AI computing company. What you ll be doing: Architecture, development and correlation of power estimation models/tools for NVIDIAs chips Help architect and develop power models for use-cases, Idle power and IO power. Chip in to design the tools based on these models and their testing methodology/infrastructures Correlate and Calibrate the power models using measured silicon data Analyze and help decide the chip configuration and process technology options to optimize power/performance for Nvidias upcoming chips Help study and contribute to Performance/Watt improvement ideas for Nvidias GPUs and SOCs What we need to see: B. Tech. /M. Tech and 1+ years of experience related to Power / Performance estimation and optimization techniques Strong fundamentals in power including transistor-level leakage/dynamic characteristics of VLSI circuits Familiarity with low power design techniques such as multi VT, Clock gating, Power gating, and Dynamic Voltage-Frequency Scaling (DVFS) Strong background in power estimation techniques, flows and algorithms Good programming skills - Python preferred. Good skills with object-oriented programming and design. Ways to stand out from the crowd: Exposure to lab setup including power measurement equipment such as scope/DAQ with ability to analyze board level power issues is a plus Exposure to power analysis EDA tools such as PTPX/EPS Good communication skills desire to work as a great teammate With competitive salaries and a generous benefits package, Nvidia is widely considered to be one of the most desirable employers in the world. #LI-Hybrid

Technical Skills and Competencies Must Have: At least 4 years of hands-on experience in mobile automation script development. Good understanding of various methods for identifying UI elements in both Android and iOS platforms. Automation Framework: Appium with Java Test Runner: TestNG CI/CD Integration: Jenkins Good to Have: Automation experience with Selenium/Java Knowledge of Perfecto Candidate Profile and Competencies Responsibilities: Write robust scripts to ensure the reliability of underlying code functionality. Execute scripts on multiple environments and share reports. Understand existing code and make necessary changes. Work directly with project teams and infra teams. Share analysis and reports of recommendations based on execution results. Be proactive when working on assigned tasks. Learn and apply new performance testing techniques on projects. Work independently and make progress by being resourceful. Own the implementation of scripts and deliver within designated timelines. Provide timely status updates and raise flags as needed. Possess good communication skills to collaborate with internal and external teams.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. As CPU Physical Design CAD engineer, you will build and support the world"™s best implementation tools and flows. Your tools and flows will ensure our custom CPUs have industry-leading power, performance and area. Roles and Responsibilities Develop, integrate and release new features in our high-performance place-and-route CAD flow Architect and recommend methodology improvements to ensure our silicon has the best power, performance and area Maintain, support and debug implementation flows, and resolve project-specific issues Work closely with worldwide CPU physical design teams, and provide methodology guidance, tools/flows support and help achieve class-leading PPA. Work with EDA vendors to define roadmap and to resolve tool issues Preferred Qualifications: Bachelors/Masters degree in Electrical/Electronics Engineering or Computer Science Ten+ years of hands-on experience in place-and-route of high-performance chips - either in a design or CAD role High level of proficiency in Tcl as well as Python Experience with automation Experience with a wide variety of Physical Design tasks - ranging all the way from place-and-route, analysis, timing sign-off and PDV Experience with advanced technology nodes (5nm or lower) Solid understanding of digital design, timing analysis and physical verification Strong user of industry-standard place-and-route tools such as Cadence Innovus Proven track record of managing and regressing place-and-route flows

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. As CPU Physical Design CAD engineer, you will build and support the world"™s best implementation tools and flows. Your tools and flows will ensure our custom CPUs have industry-leading power, performance and area. Roles and Responsibilities Develop, integrate and release new features in our high-performance place-and-route CAD flow Architect and recommend methodology improvements to ensure our silicon has the best power, performance and area Maintain, support and debug implementation flows, and resolve project-specific issues Work closely with worldwide CPU physical design teams, and provide methodology guidance, tools/flows support and help achieve class-leading PPA. Work with EDA vendors to define roadmap and to resolve tool issues Preferred Qualifications: Bachelors/Masters degree in Electrical/Electronics Engineering or Computer Science Ten+ years of hands-on experience in place-and-route of high-performance chips - either in a design or CAD role High level of proficiency in Tcl as well as Python Experience with automation Experience with a wide variety of Physical Design tasks - ranging all the way from place-and-route, analysis, timing sign-off and PDV Experience with advanced technology nodes (5nm or lower) Solid understanding of digital design, timing analysis and physical verification Strong user of industry-standard place-and-route tools such as Cadence Innovus Proven track record of managing and regressing place-and-route flows

{"company":" About Eridu AI Eridu AI India Private Limited, a wholly owned subsidiary of Eridu Corporation, Saratoga, California, USA, is looking to hire highly motivated and talented professionals for its RD center in Bengaluru to join our world-class team. Eridu AI is a Silicon Valley hardware startup focused on accelerating training and inference performance for large AI models. Today s AI model performance is often gated by infrastructure bottlenecks. Eridu AI introduces multiple industry-first innovations across semiconductors, software and systems to deliver solutions that improves AI data center performance to increase GPU utilization while simultaneously reducing capex and power. Eridu AI s solution and value proposition have been widely validated with several hyperscalers. The company is led by a veteran team of Silicon Valley executives and engineers with decades of experience in state-of-the-art semiconductors, optics, software, and systems, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (World s leading micro-LED display company and developer of the first augmented reality contact lens) . Visit our website to learn more about our impressive list of investors, advisors and leadership team. ","role":" Position Overview We are seeking an RTL Design Director to lead our Networking IC team in Bengaluru. If youre a highly motivated self-starter eager to solve real-world problems, this is a unique opportunity to shape the future of AI Networking. As part of the Design Group, you will be responsible for defining, specifying, architecting, executing, and productizing cutting-edge Networking devices. Responsibilities Provide technical leadership and direction for the offshore RTL team. Collaborate with Chip and System Architects to translate architecture requirements into microarchitecture and design implementation. Perform RTL coding, code reviews, and debugging. Document microarchitecture and RTL subsystems. Support the definition of development flows that improve efficiency and quality of execution. Work closely with Physical Design, Firmware, and Design Verification teams to ensure successful end-to-end RTL implementation. Leverage domain experience with Ethernet, PCIe, protocols to make informed design decisions. Qualifications ME/BE with at least 15+ years of experience. Proven record of successful tape-outs and productization, preferably in networking devices. Ability to translate architecture-level feature descriptions into implementable designs, including clear documentation for execution and verification. Thorough understanding of multiple clock/reset/power domain design challenges and safe/robust design practices. Experience in refactoring/restructuring designs to solve timing/area challenges, including algorithmic and structural design changes. Expertise in optimizing hardware versus firmware implementation for overall product performance/efficiency. Excellent knowledge of industry-standard tools and best-in-class practices for high-quality RTL development. Knowledge of networking protocols is essential. Experience with micro-architectural specification of ASIC s. Good understanding of the ASIC design flow, including DFT and physical implementation requirements. Why Join Us At Eridu AI, you ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities. The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles . "},"

Performance modelling and evaluation of ACAP workloads to eliminate bottlenecks as early as possible and guide the architecture of future generation devices. This is a challenging role in the FPGA Silicon Architecture Group in AECG business unit of AMD in Hyderabad. ABOUT THE TEAM: AECG group in AMD designs cutting edge FPGAs and Adaptable SOCs consisting of processor subsystems and associated peripherals, programmable fabric, memory controllers, I/O interfaces and interconnect. KEY RESPONSIBILITIES: Modelling and simulation of workload dataflow networks and clock accurate SOC components. Performance analysis and identification of bottlenecks Quick prototyping, long-term design decisions, and exploring novel architectures Enhancement of the existing tools and knowledgebase Collaborating with architects in the development of next generation devices Collaborating with customer facing teams to identify scope of optimization for future market scenarios Breaking down system level designs into simpler dataflow models and identify bottlenecks, capture memory and communication overheads Knowledge sharing with teammates through thorough documentation PREFERRED EXPERIENCE: Preferred experience in SOC architecture OR Performance analysis. Strong background in Computer architecture, Hardware performance metrics and bottlenecks. Experienced in modelling and simulation of hardware. Experience in performance profiling, creating experiments to address various use-cases and doing design space exploration. Good to have experience of creation of designs for ACAP devices or HLS. Good communication skills ACADEMIC CREDENTIALS: bachelors or Masters degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent

We are seeking a Talent Partner to directly support our operations, finance, accounting and legal business units. You will apply your creativity and superlative people skills to attract the best of class team members who will resonate with MX mission, mindset and disposition. Job Duties Collaborate with Sr. Talent Partners in establishing strategies for attracting the talent required for MX to execute on its ambitious mission . Implement key initiatives in recruiting key sales-centric disciplines throughout the organization. Collaborate with Talent and Hiring managers in streamlining the full recruiting cycle. Engage in community and industry networking events within the FinTech and startup world. Leverage key metrics in analyzing and refining staffing projections and results. Partner with People Experience and hiring managers to drive the recruiting process through on-boarding. Ensure an amazing candidate experience through high-touch, personalized outreach and engagement. Basic Job Requirements 3+ years of related recruiting experience preferred. Strong understanding of direct sourcing and effective interviewing techniques. Embrace and articulate the MX story, vision, and culture. Proven track record for successfully identifying and qualifying exceptional exception candidates with staying power. Blend of aptitude, communication skills, organizational skills and follow through. Comprehensive expertise in the full spectrum of talent acquisition and retention. Ability and desire to adapt quickly and thrive in a fast paced, often ambiguous, high-stakes environment. Ability to multitask, organize, prioritize, and manage time effectively. Ability to follow-up and follow-through with an engaging touch. Advanced Requirements 2+ years of related recruiting experience at a tech company in the Silicon Slopes region. Strong understanding of various positions, compensation structures, accelerators, local market, and methodologies preferably in the enterprise SaaS space.

The Unified Memory Controller team is looking for a passionate and self-motivatived design engineer to join our growing team. As a key contributor , you will be part of a leading team that develops industry-leading memory controllers used across a wide variety of AMD products. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ time zone s . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Microarchitectural design and RTL implementation of IP features Analyze RTL design for power optimization and timing optimization Collaborate with Design verification team to execute on design features/timing/synthesis Participate in design specification and RTL code reviews PREFERRED EXPERIENCE: Digital design engineering experience with 4+ Years. Excellent knowledge of verilog, system verilog, C and a scripting language; experience with python, perl and tcl Proficient in debugging RTL code using simulation tools Knowledge of clockign architectures, synchronization, and CDC methodology DDR, memory controller design experience is preferred Strong understanding of computer architecture ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Be responsible for supply chain planning through all business cycles,with focus on revenue contribution, ensuring forecast accuracy, managing inventory, and accurate demand planning. Job Description Be responsible for supply chain planning through all business cycles,with focus on revenue contribution, ensuring forecast accuracy, managing inventory, and accurate demand planning. Support allocation planning (supply stabilization, product planning &execution) and generate supply/ recovery plans to close demand gaps in consideration of contract fulfilments Consolidate capacity requiremen t for dedicated front end and silicon foundries in a structured manner for the entire business line on a regular basis: planning process, alignment with peers and communication to central functions Support and execute ramp up and product change projects , coordinate customer escalations and involve higher management levels where necessary. Interface with production logistics and planning; businessmanagement, business line marketing, ramp-up managers, corporate supplychain and quality management. Central role to manage and update planning models and supply/demandrules of our planning systems and act as support to the team whenrequired. You are best equipped for this task if you have: A university degree in industrial management, supply chain management or equivalent. 3-5 years of working experience in the semiconductor industries. Working knowledge of supply chain and material management concepts preferable. Affinity to Data and Advanced excel skills as we'll as experience in SAP. Knowledge in data analytics tools (eg Tableau, Power BI) andplanning models (eg Blue Yonder/JDA tool) is a plus. Fluency in English due to working in multi-cultural team

As a member of the NBIO IP Physical aware group, you will help bring to life cutting-edge designs. As a member of the Physical aware person, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve best quality and PPA for complex IPs THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: STA, timing analysis. Interface timing analysis, generate ECO. Primetime expert. Synthesis of Complex IPs, constraint developement. Develop feedback to RTL team for physically driven microarchirtecture changes, Manage data for shared design across multiple projects. corrdintation with multiple SOC for complex IPs PREFERRED EXPERIENCE: Understanding of STA and synthesis design cycle. 5+ experience in physical design and syntheis domain ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Power Management Engineer in Pune, MH, India Description Invent the future with us. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. About the role: Ampere Computing is looking for a qualified design engineer on power analysis, optimization, and validation, to contribute in designing our high-performance power-efficient microprocessor chipset. This person will be a part of the Silicon Engineering team and work across multiple groups to drive the power requirements, and power optimization from micro-architecture to final silicon. In this role, you will be at the forefront of AI innovation, building AmpereOne Aurora, our groundbreaking AI compute solution. Aurora combines high-performance general-purpose CPUs with integrated AI capabilities, offering a compelling combination of efficiency and market reach. This revolutionary product is poised to deliver superior performance while consuming significantly less power. Power analysis engineer is expected have strong CMOS design fundamentals and deep knowledge of power reduction techniques at various levels of abstraction. Expertise in analyzing the results given by various power estimation tools and create actionable items for power reduction. Experience in developing flows and post processing scripts to help in analysis and rollup. Setup power analysis environment for at the RTL-level, and gate-level for power analysis of all design blocks at the pre-silicon stage. Determine tests and benchmarks to run on all blocks for pre-silicon power analysis Develop tests in DV test environment to certain use cases interesting for power analysis and reduction Run and review power analysis reports at the RTL-level and gate-level on all design blocks. Identify areas of improvements at the architecture-level, RTL-level, and synthesis. Analyze power from activities from workloads run on emulation environment Determine power optimization budgets for all blocks, and setup runs to validate them as the design progresses. Understand the different CPU use cases, Memory and Pcie workloads. Work with industry standard power analysis tools like Spyglass/Power Artist/Joules/PrimePower etc. Maintain and improve existing power modeling and analysis flows. Experience with power analysis using gate-level and RTL-power analysis tools Good understanding of power analysis and optimization on CMOS designs Good understanding of clock-gating, power-gating, DVFS, etc. used for power optimization Good understanding of processor designs, processor work-loads. Solid programming and scripting skills using Perl/Python/Tcl Experience running power analysis on activity from emulation environment Owned CPU or SOC design blocks and familiar with design flows (synthesis, place & route, power, timing, EM/IR) Owned power analysis methodology and/or automation in previous role Hands-on working experience with Power analysis tools and flows (one or more of the following industry-standard tools: Primepower, PTPX, Power Artist, Joules, Voltus) Advanced knowledge of Python, TCL and shell scripting M.Tech in Electronics Engineering or Computer Engineering with 1+ years of semiconductor experience or B.Tech in Electronics Engineering or Computer Engineering with 3+ years of semiconductor experience What we ll offer: At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process.

The role will be a key player in organization responsible for Characterizing and validating Analog and Digital IP based Silicon Solutions at Cadence. Candidate should possess strong leadership skills with ability to manage multiple priorities and guide team members on day-to-day lab tests and silicon characterization activities. Ownership of tasks, ability to collaborate with remote teams located worldwide and clear communication skills, are must have attributes in this role. Coordination with R&D, Marketing teams in defining the scope and delivering the results in time are critical. Minimum Qualifications & Professional Experience: 10-15 years (with BTech) or 10 years (with MTech) experience in Post-Silicon PHY, Systems Interop and Compliance testing. 2-3 years of management experience leading/mentoring a small team of engineers Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on Ethernet/PCIe/CXL/UCIe/ Debug skills and Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, Analyzers. Proficient with Ethernet, PCIe, UCIe standards and Protocols. Proven experience to interpret the standard s specification to develop Electrical and Protocol, Interoperability and Compliance test suites to validate the silicon. Ability to isolate the PHY and controller (MAC/PCS) features to test, develop calibration / compliance lab suites and characterize. Architect and design Printed circuit boards in Schematic and layout level. Familiarity with peripheral chips, high speed interface design techniques, Signal and Power integrity checks / analysis and fixes needed to meet the performance requirements. Experience in PCIe/UCIe LTSSM states / UCIe Interfaces / Ethernet standards is a plus. Proven experience in developing lab automation scripts and test result analysis to debug and root cause silicon failures. Expertise in developing ESD/Latchup/ HTOL tests to meet industry standards reliability qualification & specification Expert level knowledge in Verilog RTL coding for FPGA, python,C/C++

We are seeking a Senior Manager to lead our Bengaluru IC Verification team. This role offers a unique opportunity to shape the future of AI Networking. If youre a highly motivated self-starter eager to solve real-world problems, this is a unique opportunity to shape the future of AI networking. Responsibilities Manage and lead Bengaluru team of ASIC verification engineers, fostering an inclusive and collaborative work environment. Ensure effective communication and coordination across different geographical locations. Technical Leadership in ASIC Verification: Provide technical expertise in the verification of complex ASIC designs, ensuring compliance with industry standards and project specifications. Gate Timing Simulations: Manage comprehensive gate-level simulations, including timing and power analysis, to validate the ASIC design before tape-out. RTL Coverage Analysis: Oversee the delivery of detailed coverage metrics to assess the thoroughness of the test suite. Offer actionable feedback to test writers and design engineers, focusing on identifying gaps and suggesting enhancements to broaden coverage scope. Firmware Collaboration: Work closely with Firmware teams to conduct co-simulations, ensuring seamless integration and functionality between hardware and firmware components. Team Development: Mentor and develop team members, identifying training needs and opportunities for growth. Manage third-party team augmentation in varied geographical locations. Qualification s ME/BE in Electrical Engineering, Computer Engineering, or a related field. A minimum of 12 years in ASIC verification, particularly in networking ASIC design. Technical Skills: Expertise in Hardware Verification and Hardware Verification Methodology (e.g., System Verilog, UVM) with a strong understanding of ASIC design and verification flow. Experience with coverage, gate/timing/power simulations, and test-plan documentation is required. Protocol Experience: Prior experience with Ethernet, UCIe, and PCIe protocols and both serial and parallel VIP verification modes, with strong expertise in high-speed SerDes. Leadership and Management Skills: Proven track record in managing and leading global teams with excellent people management skills, including experience in cross-cultural team dynamics. Communication Skills: Exceptional communication abilities, capable of effectively coordinating and leading a global team, and articulating complex technical issues clearly.