465 Silicon Jobs - Page 19

About The Role : Conducts verification of IP and/or SoC microarchitecture using formal verification tools, methodologies, and technologies based on model checking and equivalence checking algorithms. Creates comprehensive formal verification test and coverage plans including definition of formal verification scope, strategy, and techniques. Creates abstraction models for convergence on the design, carves out the right boundaries for the design, and tracks, verifies, and applies abstraction techniques. Develops formal proofs to implement the verification plan, reviews the completed proofs, and develops new formal verification methodologies. Performs convergence on design by creating formal verification methodology, abstraction, and simulation techniques. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Understands the binary decision diagram (BDD) and data flow graph (DFG) for data paths and resolves the BDD complexity on arithmetic. Applies understanding of modeling architecture to simplify and model the problem and uses tools to formally prove protocols and architectures. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications: 5+ years of experience in the verification of IPs Hands on experience in applying formal property verification for Ips signoff at least for 3 years Hands on experience in resolving convergence issues using FV on multiplies Managing and Guiding juniors in their verification task, Stakeholder management. Preferred Qualifications: Expertise in FV verification planning and strategies Good understanding of FV tools and capabilities Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

What you'll be doing: PVT qualification & debug of systems (small and large sample size) intended for testing HW-SW co-working stability of GPUs and SoCs Collect data from large number of systems, identify failures, classify failures based on symptoms and first level of debug. Prepare and file test reports and bugs. Develop test cases and come out with innovative ideas for problem-solving. Develop scripts to improve reporting and automating repetitive tasks. Report issues or software/hardware bugs which occur during execution to project team and management. Perform troubleshooting and root cause analysis to reach quick resolution. Requirements: Familiarity with PC architecture, present day interfaces and & interactions of Software (BIOS, Driver & OS) with hardware Strong understanding Linux and Windows OS environments. Knowledge on setting up windows debugger and working with the Dev team for triaging the issue. Basic scripting skills Familiarity with scripting languages like Perl/Python Proficiency in windows & Linux operating systems and Microsoft office tools Good analytical and reasoning skills Organized, self-directed, efficient, and able to manage multiple and complex projects in a timely manner. Desirable skills: Silicon characterization experience. Board bring-up and testing experience.

This position requires interfacing with various departments outside of Legal including Sales, Order Management and Finance. Candidates should have excellent interpersonal skills and the ability to adapt and the willingness to learn new tasks. You will join a team of contract professionals in a centralized legal operation that facilitates the execution and administration of contract agreements with Juniper customers and suppliers. You will also collaborate with other members of the Legal Operations team on process and technology improvements to positively impact efficiency and effectiveness. This role will require professionalism and discretion in handling confidential information, the ability to work in an organized and efficient manner, with high attention to detail, and the ability to handle multiple priorities at one time. Responsibilities include: Review, evaluate, and provide specific guidance concerning contracting policies and procedures. Meticulously support the global contract signature processing for a variety of documents. Duties include verifying request details, coordination with requestors to modify incorrect information, coordination with Juniper signatories, and signature process administration. Monitor changes to Juniper s authorized signature matrix and accurately apply the matrix while processing documents for signatures. Meticulously support Contract Lifecycle Management System (CLMS) repository and contents. Learn about Juniper s Contracts Taxonomy and Contract Metadata Dictionary to the extent required to perform duties efficiently. Update and maintain Excel spreadsheets and trackers; submit reports on a monthly and quarterly basis to the Senior Contract Specialist. Assist with adhoc projects as required. Support APAC business hours. Education and Experience: Bachelors degree and 5+ years of related experience and/or training. Excellent organizational, interpersonal, written and verbal communication skills. Proficiency with Microsoft Suite (e.g. Excel, Word and PowerPoint). Experience with content management/repository tools such as SharePoint and CLMS is highly desirable. Experience in electronic signature tools (e.g. DocuSign). Manage multiple concurrent tasks in a fast-paced environment and to learn, interpret, and communicate SOPs and guidelines. High attention to detail and superior reading comprehension skills are a must. Impeccable recordkeeping and record retention skills.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Responsibilities : B. Tech/BE/ME/Mtech Job Description Design and lead high speed IP (USB3, PCIE, DPHY etc) development. Need to be a strong individual contributor in analog domain. Will be required to participate in all aspects of development - analog design, layout, digital design, documentation and silicon validation. Would be required to participate in customer facing discussions. Requirements B. Tech/BE/ME/Mtech Exp - 6 +yrs Hands on design experience in various analog IP like PLLs, data converters, serial interfaces etc. Must have participated in full cycles of analog IP creation - right from spec to silicon debug and char Must have good communication skills and should be team player. Working experience in PHY (PCIE, USB2, USB3) development is desired We re doing work that matters. Help us solve what others can t.

AMD seeks a passionate, collaborative leader with strong technical skills and the initiative to motivate an expert team. You will manage a Silicon Engineering group and innovate with internal teams and external partners to create the next generation of computing technologies. THE PERSON: The ideal candidate has experience leading others in technical and managerial settings. You also have excellent communication, writing, and presentation skills. KEY RESPONSIBILITIES: ASIC design verification experience 12+ years Verification of high performance x86-core ISA features Architecting and development of testbench, test-bench components for high performance Cache, x86 ISA features, clock/reset/power features of processor. Development of detailed test plans and driving the execution of test plan, including functional coverage. Understanding the existing test bench setup and look for opportunities to improve the existing test bench. Adhering to coding guideline practices, develop and implement code review process. Collaborate with global design verification teams and drive effectively the execution of the verification plans. Your commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion. PREFERRED EXPERIENCE: Strong understanding the design and verification life cycle. Hands on verification experience with C/C++/SystemVerilog testbench development. Hands on experience with coverage planning, coding and coverage closure. Experience with x86, ARM or any other industry standard microprocessor ISA. Experience with Cache, Coherency and Data-Consistency verification. Experience in clocking, reset, power-up sequences and power management verification. Understanding of low power design verification techniques is a plus. Lead verification team from all aspects of the deliverables. Mentor the junior members of the verification team to meet the team goals Represents AMD to the outside technical community, partners and vendors Collaborate with SOC team, multi-geographical design teams for alignment of features / scoping / problem-solving. Highly motivated to seek out solutions and willing to learn new skills to fulfill job requirements; Proven interpersonal skills, leadership and teamwork; Excellent writing skills in the English language, and good organizational skills required; Skilled at prioritization and multi-tasking; Good understanding of engineering terminology used within the semiconductor industry; Good understanding of digital design concepts; Knowledge of, or experience in, functional design/RTL and physical design flow is highly desired. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor , you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The V erification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ time zone s . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Physical Design Closure of critical partitions in complex IPs PREFERRED EXPERIENCE: 4-6 years of expereince in Physical Design Should have done partition closure in at least 3-4 tapeouts Should have exposure to one of signoff verification flows ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering / Electronics Engineering

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 5+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Imagination is dedicated to designing graphics processors for a growing automotive market and its commitment to critical safety and security standards. We have a strong history supplying technology to tier one customers in the automotive market, where it is utilised in everything from digital dashboards to 360 cameras. You will be a part of the team developing the Safety Critical GPU device driver for the delivery of the new Safety Critical DDK to our customers. You will: Work within the team of engineers developing the Safety Critical DDK stack Get involved in all aspects of the development cycle, from managing requirements, through design, implementation, and testing Write technical documents describing developed technologies Support safety analysis activities Work on feature development and software upgrade About you Committed to making your customers, stakeholders and colleagues successful, you re an excellent communicator, listener and collaborator who builds trusted partnerships by delivering what you say, when you say. You re curious, solutions orientated and a world-class problem solver who constantly seeks opportunities to innovate and achieve the best possible outcome to the highest imaginable standard. You\u0027ll have: Excellent C programming skills Understanding of operating system fundamental and concepts Familiarity with device drivers Understanding of MISRA standards, and verification methods/tools You might also have: Experience in Software Quality and process Familiarity with Configuration, Requirements, and Documentation Management tools Writing technical documents for design, test spec Experience in ISO 26262 Part 6 software development

Job Title: Senior Data Engineer - Power BI Tiger Analytics is a global AI and analytics consulting firm. With data and technology at the core of our solutions, our 4000+ tribe is solving problems that eventually impact the lives of millions globally. Our culture is modeled around expertise and respect with a team-first mindset. Headquartered in Silicon Valley, you ll find our delivery centers across the globe and offices in multiple cities across India, the US, the UK, Canada, and Singapore, including a substantial remote global workforce. We re Great Place to Work-Certified . Working at Tiger Analytics, you ll be at the heart of an AI revolution. You ll work with teams that push the boundaries of what is possible and build solutions that energize and inspire. Curious about the role? What your typical day would look like? As a Senior Data Engineer, you will work to enhance our business intelligence system to help us make better decisions; Seamlessly switch between roles of an Individual Contributor, team member, and data science engineer as demanded by each project to create and manage BI and analytics solutions that turn data into knowledge. On a typical day, you might Engage with clients to understand their business context Translate business needs to technical specifications. Discuss the design of the BI solutions that can be built & deployed to solve the complex problem. Leverage Power BI to maintain & support data analytics platforms. Involve yourself in unit testing and troubleshooting. Develop and execute database queries and conduct analyses. Create visualizations and build reports that exceed the expectations of the clients. Work on enhancing the BI systems that exist. Develop or ensure that the tech documentation developed is updated. Involve in BI performance tuning & consumption patterns as you better understand BI SLAs. Ideate with your peers to design ground-breaking BI solutions. Interact and collaborate with multiple teams (Data Science, Consulting & Engineering) and various stakeholders to meet deadlines, to bring Analytical Solutions to life. What do we expect? 7+ years of experience in the BI space with high-level comfort in Power BI. Real-time experience working in Power BI that includes Model Creation, DAX (including Advanced), RLS Implementation, Performance Tuning, and Security. Comprehensive knowledge of SQL. Enthuse to collaborate with various stakeholders across the organization and take complete ownership of deliverables. Adept understanding of any of the cloud services is preferred (Azure). You are important to us, let s stay connected! Every individual comes with a different set of skills and qualities so even if you don t tick all the boxes for the role today, we urge you to apply as there might be a suitable/unique role for you tomorrow. We are an equal opportunity employer. Our diverse and inclusive culture and values guide us to listen, trust, respect, and encourage people to grow the way they desire. Note: The designation will be commensurate with expertise and experience. Compensation packages are among the best in the industry .

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life s work , to amplify human creativity and intelligence. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! NVIDIA is looking for a best-in-class ASIC STA Engineer to join our outstanding Networking Silicon engineering team, developing the industrys best high-speed communication devices, delivering the highest throughput and lowest latency for todays AI platforms! Come and take a part in designing our groundbreaking large scale and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What you will be doing: Be in charge of full chip and/or chiplet level STA convergence from early stages to signoff. Take part in top level floor plan and clock planning. Optimize, together with CAD signoff flows and methodologies. Digital Partitions and analog IPs timing integration, giving feedback to PD/RTL and driving convergence. Work closely with logic design and DFT engineers to define and implement constraints for the various work modes, including their optimization for runtime and efficiency. What we need to see: B. SC. / M. SC. in Electrical Engineering/Computer Engineering. 3-8 years of experience in physical design and STA Proven experience in RTL2GDS and STA design and convergence Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc. ) Hands on STA experience from early stages to signoff using Synopsis Primetime. Deep knowledge in timing concepts required. Great teammate. NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry! #LI-Hybrid

Responsibilities Lead the unit level pre-silicon functional & performance verification of the front end of the pipeline for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for Instruction fetch, Branch Prediction and Instruction Decode units of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead, guide, mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress, potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of core units (eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying frontend pipeline units of any CPU architecture. Hands on experience of Branch Prediction techniques. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Knowledge of instruction dispatch and Arithmetic unit. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Knowledge of verification principles and coverage. Understanding of Agile development processes. Experience with DevOps design methodologies and tools

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: In this role, the Engineer will apply and lead Broadcoms proven design methodology and milestone flow to meet Broadcoms rigorous criteria for achieving Right-first time silicon. Candidate should have very good experience in layout activities of block and level. Should be well experienced in floor-planning, partitioning, placement, clock tree synthesis, route and physical verification. Responsibilities include, but not limited to: Understanding of SoC for top-down/bottom-up physical design integration in 5nm and lower technologies Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows, adapt. Implement timing and functional ECO P&R, Extraction, Physical verification, work towards STA closure Build automation flows wherever needed/adapt to existing flows for re-use Must be proficient in any of the Cadence/Synospys/Mentor EDA tools for P&R, PV, STA, ECO Needs to be automation savvy with high expertise in one of the programming languages used in the industry Clearly know requisites for executing his/her job and lead by example Bring tangible improvement in TAT with better quality Minimum Qualifications: MSEE/MSCS 3+ years (BSEE/BSCS 5+ years) A deep understanding of backend digital design flow Proficient in timing constraints, physical constraints Proficient in handling EDA tools across floorplan / partition / placement / cts / route stages for SoC TOP. Proficient with backend EDA tools viz, Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, Redhawk Proficiency in Tcl and Perl Excellent analytical skills Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone

Calling all innovators and creators! We re hiring RTL Design Engineers for Bangalore to work on complex ASIC designs and integrations. Experience Required: 3-25 Years Key Skills: RTL design, low-power methodologies, scripting (Perl, Python, TCL)

Candidate should have very good experience in Physical design activities of block and SoC level. Should be well experienced in floor-planning, partitioning, placement, clock tree synthesis, route , physical verification and all signoff checks closure. Experience with tools such as Innovus/Encounter, ICC, Caliber, LEC, Primetime etc is highly desirable. Full chip tape out experience based on 5nm/7nm/16nm technologies is preferred. Candidate would be required to work on various phases of SOC physical design activities of top level & block level - floor-planning, partitioning, placement, clock tree synthesis, route, physical verification (LVS/DRC/ERC/Antenna etc). Should have excellent problem solving skill to help through congestion resolution and timing closure. Candidate should be able to meet congestion, timing and area metrics of design. Would be required to do equivalence checks, STA, Crosstalk delay analysis ,noise analysis, power optimization. Should be able to implement timing and functional ECOs. In this role, the Engineer will apply Broadcoms proven design methodology and milestone flow to meet Broadcoms rigorous criteria for achieving Right-first time silicon. Candidate should be able to work independently and guide other team members. Should be experienced in working in a global team and dynamic environment. Should possess ability to learn and adapt to new tools and methodologies. Excellent communication skill is a must. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

In this role, the Engineer will apply and lead Broadcoms proven design methodology and milestone flow to meet Broadcoms rigorous criteria for achieving Right-first time silicon. Candidate should have very good experience in layout activities of block and level. Should be well experienced in floor-planning, partitioning, placement, clock tree synthesis, route and physical verification. Responsibilities include, but not limited to: Understanding of SoC for top-down/bottom-up physical design integration in 5nm and lower technologies Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows, adapt. Implement timing and functional ECO P&R, Extraction, Physical verification, work towards STA closure Build automation flows wherever needed/adapt to existing flows for re-use Must be proficient in any of the Cadence/Synospys/Mentor EDA tools for P&R, PV, STA, ECO Needs to be automation savvy with high expertise in one of the programming languages used in the industry Clearly know requisites for executing his/her job and lead by example Bring tangible improvement in TAT with better quality Minimum Qualifications: MSEE/MSCS 3+ years (BSEE/BSCS 5+ years) A deep understanding of backend digital design flow Proficient in timing constraints, physical constraints Proficient in handling EDA tools across floorplan / partition / placement / cts / route stages for SoC TOP. Proficient with backend EDA tools viz, Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, Redhawk Proficiency in Tcl and Perl Excellent analytical skills Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.