Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 3+ years"™ experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG -In depth knowledge of DFT concepts. -In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. -Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors. -Knowledge of equivalence check and RTL lint tool (like spyglass). -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem-solving skills

About The Role : As SoC/System Debug specialist, the candidate will be part of a top-notch debug team for Intel post silicon server validation. Manual debug team will be gate keeper to ensure a healthy product quality release to internal and external customers. Responsibilities include systematic debug of complex failures at system level, designing the experiments to root cause the issues, co-ordinate with different teams for execution of experiments. Once the issue is root caused, work with design teams on work around and fix validation. The position will support various levels of experience with following qualifications. Works with architecture and design teams to implement different DFD methodologies and necessary hooks into SoC designs. This position will also mentor and coach other team members to develop necessary expertise and skills. Qualifications Bachelor's/Master's in Hardware Engineering or Electrical/Electronics Engineering or Computer Engineering or Computer Science with 10+ years of related work experience. Candidate must have high degree of hardware architecture/ microarchitecture experience in CPU/SoC/Chipset and a few of the subsystems/areas given below Strong knowledge and skills of Intel IA (IA32 architecture with uArch debug knowledge of Intel's Core and Uncore or equivalent architecture.) Passionate about working on CPU hardware and enjoys various levels of debugging Good data analysis skills and attention to details, Patient and disciplined problem-solving skills Expertise in CPU bring up, system level debug, root cause isolation, debug methodology and tools Knowledge of SOC level flows and deep understanding of some of the domains - CPU core, IOs, Coherency, reset, Power management, virtualization Understands System HW/FW/SW as a whole Excellent failure boundary minimization skills Must possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment. Optimizes debug process and drives systematic improvements in debug methods, tools and features based on expertise and debug findings. Hands-On experience of complex SoC sightings and exposure to running cross-team/site Task forces Knowledge on Debug Tools for JTAG, on chip trace features and ability to debug via OSC/LAs etc; Usage of any Post-Si debug tools (e.g., logic analyzers, oscilloscopes, things like ChipScope on FPGA's, etc.), usage of different Analysers/exercisers (PCIe etc.) Good working knowledge in C/C++/Python SW programming for content development and scripting Demonstrated collaboration skills working with different partner teams like design, architecture, firmware, tools, manufacturing teams during complex failures debug Excellent written and oral communications and experience working in a cross functional /cross geography team environment are essential Inside this Business Group The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intels offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements. Working Model This role will require an on-site presence. *

About Clear At CLEAR (formerly known as ClearTax), we are on a mission to simplify financial lives for all Indians We make delightful tax-based SaaS and financial service products for businesses and individuals which helps them save money and time Over 5 million individuals, 2,500+ enterprises, 80,000 tax practitioners and 600,000 small businesses trust and use our products We have built rich platforms for GST, e-Waybill, e-Invoicing, ITR and TDS much ahead of the curve in India s business digitization journey We now see a material part of our countrys trade with $200B worth of invoices flowing every year It is still day one for us as our goal is to scale 10x to 6 million businesses For the same, we are going mobile-first for all our customer segments and building credit, payments, insurance, network and business discovery engines on our core platform We were incubated in Y Combinator and are funded by Silicon Valley investors, including PayPal co-founders Peter Theils Founders Fund, Max Levchin and Scott Banister - an early investor in Facebook and Uber We initially raised $15 5M with investors including Sequoia Capital and SAIF Partners In October 2018, we raised $50M in series B funding from Composite Capital We are now significantly ramping up our business teams and are looking for the best people to help plan and run our business Job brief: We are looking for a self-motivated enterprise sales manager to join our Enterprise Sales team to scale the growth of our business with Enterprises across India A field-based sales manager who is responsible to grow B2B business within the Enterprise (>100 cr revenue) market space for India Key responsibilities: 1 Understand ClearTax suite of products and confidently demo to CFOs and Tax Heads of Fortune 500 and High Turnover Indian companies Knowledge of SaaS product sales preferred Be able to map the account (end users, influencers, decision makers) and plan the sales process from initial demo to closure within a defined timeline 4 Should have given demos to B2B customers 5 Get insights on competition and position Cleartax USPs to ensure we come out on top as part of the evaluation 6 Build rapport with potential accounts, explaining existing and new capabilities, preparing detailed customized proposals, and constantly engaging with them Be able to negotiate and close deals in the face of stiff competition 8 Co-ordinate and close all contractual documentation for closure and revenue collection Be able to generate your own leads when required - via cold calling, referrals Constantly read up on tax topics, be up to date on tax advances and product specifics Ensure customer success post go live and hand over to key account management team in a smooth manner 12 Feedback on important features and customer needs into the roadmap 13 Regularly update the sales data in CRM for tracking and analysis purpose Requirements: Experience in selling to corporates/businesses in India and have a proven track record Should have the hunger to constantly learn and innovate Outstanding presentation and communication skills, be able to convince prospects Strong consultative selling ability Ability to manage long, complex sales cycles from beginning to end Knowledge of strategic account sales techniques and processes including understanding customer needs, overcoming objections, developing business cases, negotiating and closing complex deals

Analog Validation/Characterization Engineer/Lead

Description Job Description Summary As a Senior Base STD Characterization Engineer, you will work in a highly innovative, motivated, young, and dynamic design team capable of verifying complete products using state of the art STD Cells , Custom Cells on latest CMOS process technology Job Description Responsibilities * Silicon smart based STD cell characterization experience. * Writing vector/ARC for STD Cells Responsibilities for hspce (hspice/spectre) based characterization. Circuit understanding * Basic building blocks - AND , NAND , NOR , latches , flops design understanding Block level circuit simulation , Analysis capability * STD cell timing checks - linearity , monotonicity , QA experience Analysis of Circuits , Timing concepts schematic analysis Collaborate closely with design and verification team members spread across the globe, many of whom have decades of experience in memory design. Opportunities to work closely with cross functional groups such as Product Engineering and Design Architecture. May also review vendor capability to support product development. 3-5 years of experience

AMD is looking for an experienced Analog Mixed Signal engineer to take on the technical challenges within the I/O and PHY Technology Group. This group delivers critical Mixed Signal IP such as highly configurable high-speed memory I/Os/PHYs and Chiplet Interconnect IP (eg UCIE) to various Business Units/SoCs within AMD. The ideal candidate will get to work with circuit and FE architects to accurately model the analog digital interface boundary of high speed mixed signal IPs to accomplish timing integrity goals. KEY RESPONSIBILITIES: Analyze timing constraints for complicated static timing analysis (STA) paths including multistage generated clocks, ZCPs in a variety of mixed signal circuits. Use the appropriate margining methodology for data, clock and async timing paths to improve timing robustness and reliability. Identify noise sources in timing models and feedback to CKT and LAY for appropriate design fixes. Adopt leading industry STA and Timing Char tools to drive timing convergence in mixed signal IP development. Use scripting skills to meet efficiency and quality goals across all timing workflows. Derive best design guidelines for optimal signaling performance that result in minimal skews and insertion delays for various types of data interfaces and clock propagation. Prepare, analyze and report on data integrity and consistency within the macro timing model using spice correlation and data analytics. PREFERRED EXPERIENCE: 6+yrs experience in high-speed 10+Gbps serial and/or parallel analog PHY/IO designs. Experience in FinFet advanced CMOS process nodes with a solid understanding of transistor device performance and fundamentals. Timing closure and Timing char using PrimeTime and NanoTime STA tools is a must. Proficiency in using spice based extraction and simulation tools. Very good understanding of SOC and Custom flows including physical design and IR drop. Strong communication skills with ability to comprehend and present technical ideas & reports across different teams and geographies. Strong analytical and problem-solving skills including the ability to root cause and debug in a fast-paced environment. Possess sound fundamentals and knowledge of analog mixed signal circuits timing collaterals and constraints. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

1. Must have SoC implementation knowledge with deep level expertise in at least one domain. 2. Have responsibility for processes of significant technical importance and for results in SoC implementation and/OR related areas. 3. Solve complex, novel and non-recurring problems; initiates significant changes to existing processes/methods and leads development and implementation. 4. Influences technical decisions that have a significant impact on final product. 5. Requires limited supervision and is evaluated according to project performance. 6. Coaches and mentors less experienced staff; influences others as a technical leader. 7. very good communication and presentation skills 8. Proficiency in scripting Required Skills: 1. SoC implementation expertise. Multi million gates integration. 2. Low power implementation, Constraints validation, Formal verification 3. Floorplanning, Power planning. 4. Clock Tree Synthesis (CTS). 5. Awareness of Synthesis, SCAN and DFT implementation 6. Static Timing analysis (STA). 7. Analysis: IR, EM, Noise. 8. Physical Verification. ACADEMIC CREDENTIALS: Bachelors or Masters degree in Electronics engineering/Electrical Engineering

Your primary focus will be to lead Test Engineering Characterization teams across sites with focus on development, implementation and execution of Characterization test programs for various Automotive Microcontroller Products. In your new role you will: Lead Test Engineering Teams across sites Work closely with cross-functional teams to ensure stakeholder alignment in Post-Silicon methodology related to chip characterization. Drive cost reduction and quality improvements by optimizing characterization concepts, test programs and test hardware. Make Post-Silicon Characterization cost competitive with respect to project timeline and scope. Provide requirements on ATE capabilities derived from new productroad maps. Ensure timely execution of the Characterization Test Program meeting Project milestones. Build and manage high-performance teams driving innovation and process improvements. Foster a culture of innovation and continuous improvement through out the organization. You are best equipped for this task if you have: 8+ years of hands-on experience in any of the post silicon domains (validation, characterization, test engineering) is preferred. Experience in analog mixed signal domains is preferred. 3years of experience in leading and managing teams of a reasonable size. Preferred experinece in managing cross-site projects

Oversee all verification activities for a GPU component or subsystem, from initial planning to final sign-off. Develop verification plans and build, maintain UVM testbench components. Monitor, track, and report verification metrics to ensure closure. Provide verification-focused feedback during design specification discussions. Implement UVM testbenches, including writing tests, sequences, functional coverage, assertions, and verification plans. Take ownership of task definition, effort estimation, and progress tracking. Contribute to the enhancement and evolution of GPU verification methodologies. Lead, mentor, and support team members in verification activities. Engage in design and verification reviews, suggesting improvements where necessary. About you Committed to making your customers, stakeholders and colleagues successful, you re an excellent communicator, listener and collaborator who builds trusted partnerships by delivering what you say, when you say. You re curious, solutions orientated and a world-class problem solver who constantly seeks opportunities to innovate and achieve the best possible outcome to the highest imaginable standard. You\u0027ll have: Demonstrated experience in developing verification environments for complex RTL designs. Strong understanding of constrained-random verification methodologies and the challenges of achieving verification closure. Ability to define verification requirements, determine implementation approaches, and design testbenches. Expertise in root-cause analysis of complex issues, with the ability to resolve them efficiently. Deep knowledge of SystemVerilog and UVM. Capability to develop and enhance verification flows. Familiarity with ASIC design methodologies, flows, and tools. Proficiency in planning, estimating, and tracking personal tasks. Experience managing multiple projects simultaneously. Strong communication skills for effectively conveying technical issues, both verbally and in writing. You might also have: Experience leading teams. Knowledge of Graphics, GPU, CPU, or SoC architectures. Experience with broader verification technologies, including formal property-based verification (FPV). Proficiency in coding and scripting using Python, TCL, Perl, SystemC, or C++. Understanding of functional safety standards such as ISO26262

About The Role : Performs functional logic verification of a block, subsystem, and SoC related to DCAI flagship AI products to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, micro architects, full chip architects, RTL developers, post silicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from post silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications: Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 10+ years of technical experience. Related technical experience should be in/with:Silicon Design and/or Validation/Verification. Preferred Qualifications: Design/Verification with developing, maintaining, and executing complex IPs and/or SOCs. Design/Verification exposure for PCIe Subsystem involving full protocol stack - Transaction layer, Data Link Layer and PHY Layer Design/verification exposure for Industry standard BUS topologies such as AMBA AXI/AHB/APB, I2C, SPI, JTAG, CoreSight Debug and Trace OVM, UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Inside this Business Group Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

About The Role : We are looking for a candidate with strong software engineering background to drive E2E graphics software debug of Intel Graphics drivers. The role involves understanding feature architecture, driving debug of E2E Graphics use cases across Gaming, Creator, AI and Platform focused across Functionality, Concurrency, Reliability/Stress and Interoperability. Strong capable C/C++ programmer with solid experience driving algorithmic solutions from prototype to implementation including OS/Driver debug skills. Proven experience in handling all aspects of SW debug including OS and device drivers. Ability to learn and adapt quickly in ambiguous environments like customer escalations with a keen focus on problem solving. Need to be able to handle tops down system level triage/debug and work well with developers, SW/HW architects to root cause issues. Looking for a candidate with positive attitude, disciplined and ability to work in competitive environment with good written/verbal communication skills. Qualifications Candidate should possess a Master's degree with 2+ years of experience or Bachelor's degree with 4+ years in Computer Science, Computer Engineering Skills and Experience. Experience with the Windows Driver Model(WDM/WDF), Kernel Mode Driver Framework and kernel debugging, Windows kernel internals. Experience with graphics hardware and software. Experience in triaging issues related to Power and Performance, Stress n Stability. Good understanding in state of the art machine learning and deep learning algorithms, techniques and best practices. Expertise in Deep Learning Frameworks:TensorFlow, Pytorch. Familiarity with various debug tools including emulators/JTAG-debuggers, Windbg, etc. Good understanding of industry standard API's and frameworks such as DirectX, OpenGL, OpenCL, Vulkan. Sound knowledge of software development - C, C++ , Python programming expertise and experience is required. Demonstrated software and silicon debug knowledge Good To Have:Knowledge on Intel GEN architecture Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Defines, develops, and performs functional validation for GPUs, focusing on validation of interaction of GPUs, media, display and system level features. Applies various hardware and software level tools and techniques to ensure validation coverage and that performance, power, and area goals are met. Reviews proposed design changes to assess impact on validation plans, tasks, and timelines. Develops GPU validation methodologies, executes validation plans, and collaborates with other engineers for design optimization, troubleshooting, and failure analysis. Performs silicon debug to identify root causes and resolves all functional and triage failures for GPU issues. Tests interactions between various GPU features using validation infrastructure. Develops post silicon validation infrastructure (e.g., performance monitors, behavioral checkers, state space coverage) and test environment used in validation testing. Publishes GPU validation reports summarizing all validation activities performed, reviews results, and communicates to relevant teams. Works with architecture, design, verification, board, platform, and manufacturing teams to maintain and improve debug, validation test strategy, methodologies, and processes for graphics interfaces and to meet desired product specifications. Qualifications Bachelor's or master's degree in computer science, Electrical Engineering, or a related field with 5 to 10 years of experience. Proven experience in platform validation, low power flow management, memory expertise and ( GDDR/LPDDR ) debugging, and test content development, with a focus on reset/boot/low power functionalities. Strong understanding of server architectures, hardware components, and operating systems. Proficiency in scripting languages (e.g., Python) for test automation, debugging, and test content development. Experience with validation, debugging, and test content development tools and frameworks (e.g., Jenkins, GDB, WinDbg). Excellent problem-solving skills and attention to detail. Strong communication and collaboration skills, with the ability to work effectively in a team environment. Familiarity with version control systems (e.g., Git) and issue tracking tools (e.g., JIRA). Knowledge of industry standards and best practices related to server reset, platform validation, debugging, and test content development.

About The Role : Builds emulation and FPGA models and solutions from RTL design using synthesis, partitioning, and routing tools. Develops, integrates, tests, and debugs hardware and software collateral in simulation, emulation, and FPGA models for testing new features, writes directed tests, develops the test environment and hybrid emulation environment, and supports verification of hardware and software/firmware. Defines and develops new capabilities and tools to achieve better verification through improved emulation and FPGA model usability. Enables acceleration of RTL development and improve emulation/FPGA model usability for presilicon verification, postsilicon validation, and software development. Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform and interfaces with and provides guidance to verification teams for optimizing presilicon verification environments, test suites, and methodologies for emulation efficiency. Develops and utilizes automation aids, flows, and scripts in support of emulation utilization. Applies understanding of emulation and FPGA prototyping tools and methodologies, SoC integration, emulation transactors, emulation performance and optimization techniques, RTL simulation, and hybrid emulation environments (virtual platform and FPGA/emulation model). Collaborates with design, power and performance, silicon validation, and software teams, and participates in SoC and IP bring up, root causes testbench issues, IP and SoC testcases, and emulator/FPGA environment issues. Qualifications Bachelor Degree in Electrical and Electronics Engineering or Master's Degree in Electrical and Electronics Engineering or Computer Engineering with 8+ years experience. Experience in Pre-si/post-Si validation with FPGA based validation, Experience with bring up of functional tests on FPGA/Si. Experience in Hardware validation/emulation platforms like zebu, veloce or functional bring up of PM/Reset/PCIE/DMI/DDR/Mem et.al. Good understanding of SoC architecture / uArchitecture, Networking protocols or Signal processing algorithms/flows in hardware. Excellent understanding of test framework and abstraction, develop test plans, test scripts for functional validation. Very good debugging skills, experience of working with various hardware debugging tools JTAG, Verdi, fsdb analysis. Good knowledge in C/C++, Scripting knowledge (Python/Perl/Tcl), ability to develop parsers. Knowledge in RTL design, VHDL/Verilog is a plus. Strong analytical ability, problem solving and communication skills. Ability to work independently and at various levels of abstraction. Inside this Business Group The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Working Model This role will require an on-site presence. *

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Synthesis of Complex IPs, constraint developement. Physical aware activty Floorplan,Placement,clock tree synthesis routing. Develop feedback to RTL team for physically driven microarchirtecture changes, Manage data for shared design across multiple projects. corrdintation with multiple SOC for complex IPs Lead team for junior team member,guide them and help techincal areas. PREFERRED EXPERIENCE: Understanding of Physical design and synthesis design cycle. 8+ experience in physical design and syntheis domain ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering/Electronics Engineering

Looking for an experienced Sales Director, highly self-discipline, result-oriented, team-player, strong sense of do-able and problem-solving, with proven record in developing enterprise business. Primary focus on large enterprise like Telco, and Data center / Cloud Service Provider / HPC business opportunities to promote Supermicro Edge Computing Solution. Identify and define the customer demands, work with internal team to deliver solutions to meet highest customer satisfaction with quality result. Approach and develop large enterprise direct account, Telco E-Commerce, Data center / Cloud Service Provider, HPC and related business opportunities to promote Supermicro Edge Computing solution. Create the quality pipelines with eco-system partners and promote company s products/solution/services proactively. Build-up and maintain long-term partnership and relationships with existing and new customers. Weekly update the progress and support needed. Essential Duties and Responsibilities: Primary focus on large enterprise like Telco, and Data center / Cloud Service Provider / HPC business opportunities to promote Supermicro Edge Computing Solution. Identify and define the customer demands, work with internal team to deliver solutions to meet highest customer satisfaction with quality result. Approach and develop large enterprise direct account, Telco E-Commerce, Data center / Cloud Service Provider, HPC and related business opportunities to promote Supermicro Edge Computing solution. Create the quality pipelines with eco-system partners and promote company s products/solution/services proactively. Build-up and maintain long-term partnership and relationships with existing and new customers. Weekly update the progress and support needed. Qualifications: Bachelor s degree and MBA preferred. Minimum 7+ years of sales and business development experience is desirable. Highly self-discipline, result-oriented, team-player, strong sense of do-able and problem-solving, with proven record in developing enterprise business.

About The Role : This role is within Intel's Client Computing Group. We are seeking an experienced Memory Validation and Debug Lead to join our post silicon validation team. In this role, you will lead memory subsystem ( DDR5 / LPDDR5) validation and debug efforts and ensure high-quality, reliable memory systems within our advanced silicon products. You will work closely with cross-functional teams, including design, MRC , EV (analog) verification, and validation teams, to enable higher memory speeds , validate new feature and identify , analyze and resolve memory issues. Your expertise will be essential in enhancing product quality, optimizing memory performance, and driving innovation. Applies various hardware and software level tools and techniques to ensure validation coverage and that performance, power, and area goals are met. Reviews proposed design changes to assess impact on validation plans, tasks, and timelines. Develops SoC validation methodologies, validation test plans, executes validation plans, and collaborates with other engineers for design optimization, troubleshooting, and failure analysis. Performs silicon debug to identify root causes and resolves all functional and triage failures for SoC issues. Develops content to create or increase specific IP interactions using a variety of tools and techniques (including patching techniques using microcode, firmware, or custom OS builds). Engages in all phases of the product life cycle and develops and validates content, infrastructure, and bug hunts in multiple environments (e.g., simulation, emulation, FPGAs) to ensure silicon readiness. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: M.tech/ME with 7+ years of relevant industry experience hands on with pre or post silicon SOC validation. Key Skills:Memory sub-system validation, DDR5/LPDDR5, IP, debugging, architecture. Preferred Qualifications: Understanding of Intel system architecture and hands-on experience validating and debugging SoC issues.Requirements listed would be obtained through a industry relevant job experience Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

About The Role : The world is transforming - and so is Intel. Here at Intel, we believe the world needs technology that can enrich the lives of every person on earth. We work every single day to design and manufacture silicon products that empower peoples digital lives. Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver solutions for products that impact customers lives? If so, Come join us to do something wonderful.Your responsibilities will include but not limited to:Oversees definition, design, verification, and documentation for SoC (System on a Chip) development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from highlevel design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development. Qualifications You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications Candidate will have a Bachelors degree in Computer Engineering/ Computer Science or Electrical Engineering with 6+ years of experience -OR- a Masters degree in Computer Engineering Computer Science or Electrical Engineering with 4+ years of experience with C and Object Oriented Software design including algorithms and data structures Knowledge of Software development practices and quality standards Experience with Unix Windows based SW development tools . Experience developing bus functional models for unit level verification or Verification IP development Preferred Qualifications Proficiency in System C SystemVerilog UVM and ESL modeling methodologies Proficiency in HW design and verification methodologies Working knowledge of highspeed HW protocols eg PCIe UPI DDR Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world.

About The Role : Lead low power validation strategy and drive validation roadmap across multiple projects Lead a very high performing team of talented engineers working on GPU IP post-Si low power validation Excellent understanding latest GPU architecture/micro-architecture low power features, design changes and develop Post-Si Low Power validation test plan for 3D/Compute pipeline Very good understanding of low power concepts and flows (dynamic, leakage power, clock gating, power gating, Resets, stand-by entry/exit flow, DVFS, clock squashing, TDP, PM flexing) Good understanding of power switching, isolation, level shifter, clock domain crossing, PLL, power delivery logic Understanding of low power FSM blocks, states and interfaces with microcontrollers, SW Driver, FW, SoC and platform Define low power validation scenarios and implement basic/stress/concurrency/cross-feature/PM cycling/random test cases Work closely with pre-Si architect/design/verification and SW/FW teams to review test plans and scenarios and finalise synthetic/BareMetal/driver/real use cases to validate on simulation/emulation to sanitize tests before Si arrival Analyse feature coverage gaps and enhance test plans Define power-on bring up and volume validation regression plan to enable PRQ. Come up with receivables/dependencies, Risks/mitigation and follow-up closely with relevant stakeholders for closure Debug:Understand Si failure signatures in-depth, work closely with design and architecture, SW/FW teams to root cause issues. Guide juniors on debug Tools : Advance usage of Si debug tools. Work with tool development teams to Develop tools/scripts. Effective reproduction of issue on Emulation/simulation to decrease debug TAT Innovation - Drive development of new low power validation methodologies, shift-left validation, PM test framework, automation tools (test content generation, debug, feature coverage) and adoption of AI/ML methods to improve efficiency Regular Rolling up of the Post Si low power validation status to the upper management for decisions at various product cycle milestones Qualifications Master of Engineering degree in Computer or Electronics or Embedded Systems Engineering with 7+ years' experience in graphics post silicon power management PhD degree in Computer or Electronics or Embedded Systems Engineering with 5+ years' experience in graphics post silicon power management Should have good understanding of Computer architecture, Graphics architecture/design, low power Validation and Si Debug Flow Hands-on experience in C/ C++, and Perl/Python, Linux Shell Scripting Familiarity with Verilog/System Verilog/VHDL Familiarity with Windows, Linux OS, commands and environment Familiarity with OpenCL, OpenGL, Vulkan and DirectX API programming is desirable. Good analytical ability, problem solving, and written and verbal communication skills Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high quality integration of the GPU block.Additional Details:: You will be responsible for designing and/or integrating IP for a discrete graphics SoC. You will be working or assisting in architecture, design, implementation, formal verification, emulation and validation of discrete graphics SoC products, including: Creating a design to produce key assets that help improve product KPIs for discrete graphics products. Working with SoC Architecture and platform architecture teams to establish silicon requirements. Making appropriate design trade off balancing risk, area, power, performance, validation complexity and schedule. Creating micro architectural specification document for the design. Working with external vendors on tools or IPs required for the development of micro-architecture, design and design qualification of custom silicon designs. Driving vendor's methodology to meet world class silicon design standards. Architecting area and power efficient low latency designs with scalabilities and flexibilities. Power and Area efficient RTL logic design and DV support. Running tools to ensure lint-free and CDC/RDC clean design, VCLP. Synthesis and timing constraints. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: BS+8 Years of relevant industry experience. Having achieved multiple tape-outs reaching production with first pass silicon. Ability to drive and improve digital design methodology to achieve high quality first silicon. Hands on experience with FPGA emulation, silicon bring-up, characterization and debug. Able to work with multi-functional teams within Intel and external vendors across geographical boundaries to resolve architectural and implementation challenges with a focus on schedule. Strong verbal and written communication skills. Good understanding of verilog and system verilog, synthesizable RTL. Knowledgeable in modern design techniques and energy-efficient/low power logic design and power analysis. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior ATE Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and re-imagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge. Work hard. Have fun. Make history. Key job responsibilities As a Senior Test Engineer at Amazon, you will play a critical role in new product introduction, leading first silicon bring-up, production ramp-up, and yield optimization. You will work closely with OSAT (Outsourced Semiconductor Assembly & Test) vendors to develop ATE test methodologies, board design, and debug strategies, ensuring product performance, manufacturability, and cost efficiency. This role also involves hands-on debugging on ATE testers for rigorous characterization and correlation with Bench (SLT). Key job responsibilities: First Silicon Debug & Characterization - Collaborate with Design and OSAT Test Engineering to debug first silicon, execute rigorous characterization, and perform SLT correlation. ATE Debug & Correlation - Perform hands-on debugging and code bring up on ATE, conduct bench correlation and root cause analysis for yield loss mechanisms. Test Development & Optimization - Define test program flows and methodologies to achieve comprehensive test coverage, efficient test time, and cost optimization. Yield Analysis & Improvement - Analyze engineering sample data, characterize NPI product performance, and optimize manufacturing yield windows through statistical data analysis and failure analysis techniques. Production Readiness & OSAT Management - Finalize wafer-sort and final test programs, oversee early production stages, and drive product to meet yield and test cost targets. Knowledge Transfer & Sustaining Support - Work closely with OSAT sustaining engineers, ensuring seamless product knowledge transfer and ongoing test optimization. Board Design & Debug - Contribute to test hardware development, including load board, probe card design and HW qualification for Mass production. Bachelors or Master s degree in Electrical Engineering, Electronic Engineering, or a related field. Minimum 7years of experience in semiconductor test engineering, ATE test development, yield analysis, yield improvement and production ramp up. Hands-on experience with ATE test coding, first silicon debug (ex. SCAN, MBIST, DDR), PVT characterization and test time optimization. Proficiency in ATE test methodologies, including wafer-sort and final test program development. Proficiency in board design, including load boards, probe cards, and interface hardware. Expertise in statistical ATE data analysis, failure analysis techniques and root cause identification. Excellent communication skills with the ability to collaborate across design, product, and manufacturing teams. Willing to travel for short-term onsite support at OSAT locations during silicon bring-up and mass production.

About Moloco: Moloco is a machine learning company empowering organizations of all sizes to grow and unlock the full value of their unique first-party data, elevating the traditional path to performance advertising. While the largest technology companies have proven the speed and scale of ad-targeting utilizing data the same robust performance powered by machine learning has previously been unavailable beyond their platforms. Thats where Moloco steps in. With Molocos powerful combination of cutting-edge machine learning technologies, we play a unique and visible role in shaping the digital economy, all while allowing companies to stay independent and scale. An industry leader at the nexus of machine learning, performance marketing, and visionary product infrastructure, Moloco is advancing the advertising technology industry. We ranked in the top 10% of the Inc. 5000 fastest-growing private companies for 2023. Recognized as one of 46 leading Cloud Computing companies, receiving the Stratus Award for 2023 . In 2023, we received Google s Cloud DevOps Dreamers Award , a recognition given to companies that are implementing DevOps practices to drive organizational success and high performance. Lastly, Moloco is a 2024-certified Great Place to Work ! Check us out on Glassdoor and be sure to get an inside look at working at Moloco on Instagram , Twitter , and YouTube . Moloco is headquartered in Silicon Valley, with offices in San Francisco, New York, Los Angeles, Seattle, London, Berlin, Seoul, Singapore, Beijing, Gurgaon, Bangalore, Tel Aviv and Tokyo. Creating a diverse workforce and a culture of inclusion and belonging is core to our existence. To reach our goals, diversity of talent and thought is a critical component of how we operate as an organization. Our workforce is our superpower, and we know that fostering a culture of inclusion, authenticity, and belonging will allow us the greatest opportunity to carry out our mission -- to empower businesses of all sizes to grow through operational machine learning. Moloco is a truly rewarding place to work and in an exciting period of growth, which you could be a part of. Join us today and apply now! The Impact Youll Be Contributing to Moloco: Join Moloco as a Growth Manager and take command of our client strategies and grow their mobile businesses. Moloco is a top mobile DSP driving performance results for metrics driven clients. You will get the full experience and learnings from a dynamic startup based in Silicon Valley made up of industry leaders who are experienced, data-driven, motivated, and humble. This is a Gurgaon-based role with a hybrid working model. Here s what you ll be working on: Fully comprehend advertisers marketing needs and translate how Moloco s programmatic solution will drive KPIs and goals. Work with Clients, Sales, other Account Managers, Data Science and cross-functional teams to identify and to drive account growth results. Help build and iterate on new products and client solutions and work with Product, Data-Science, and Engineering teams. Understand the mobile ecosystem, stay current on industry trends, and most importantly offer actionable insights to clients. Lead multiple partnerships, client meetings and business reviews. Understanding clients needs inside out in order to bring success and growth. Analyze campaign data and provide actionable and valuable insights. Translate complex data analysis into simple language and use it to influence decision making. Create a clear data-driven strategy for each client and work closely with them to achieve this. Exceptional data story-telling and client presentation skills. Identify and pitch incremental opportunities that are aligned to client s growth objectives and scale accordingly in partnership. Track record with servicing and growing major advertiser accounts. Here is what you need to succeed 3+ years Mobile Advertising experience in Account Management in programmatic marketing. Strong ownership mentality and a curious approach to problem solving. Familiarity with big data, MMPs, mobile app ecosystem and ad tech. Growth-minded to thrive in a startup environment. Travel depending on business needs. Experience in day to day campaign management. Strong interpersonal skills necessary to interact with clients, management, and peers. Strong skills in excel, powerpoint/slides, g-suite preferred. Positive outlook, enthusiasm, and strong internal drive. Detail oriented. Data-focused approach. Fluency in English. Moloco Thrive: Benefits and Well-Being: We take care of you and create the conditions for you to do the best work of your career. Through a lens of inclusion, we offer innovative benefits that empower our employees to take care of themselves and their families so they can do the best work of their lives. For an overview of our global benefits, click here . Moloco Values Lead with Humility: Everyone s voice is respected, valued, and heard. With humility, we become more open and accessible to each other. We win, lose, and learn together. Accountability and feedback are essential to our success. Uncapped Growth Mindset: We see all situations as opportunities to learn, grow, and improve as individuals and as an organization. We seek diverse perspectives, encourage curiosity, and promote experimentation to push the boundaries of what s possible. Create Real Value: We pursue the most impactful opportunities with rigor and integrity. We take intelligent risks and make disciplined trade-offs to maintain deep focus. We help our customers win by delivering durable value. Go Further Together: We re one team working towards one mission and vision. We collaborate proactively and inclusively, involving the right people at the right time and in the right way. We strive to create a more equitable workplace. We won t let each other fail. Additional Resources: Moloco Company Blog Moloco Leadership Moloco Newsroom Equal Opportunity: Moloco is an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, color, creed, religion, national origin, age, sex and gender, gender expression, and gender identity, sexual orientation, marital status, ancestry, physical or mental disability, military and veteran status, or any other characteristic protected by law. Candidate Privacy Notice: Your privacy matters to us. By applying, you acknowledge that you ve reviewed our Candidate Privacy Notice .

About The Role : Conducts verification of IP and/or SoC microarchitecture using formal verification tools, methodologies, and technologies based on model checking and equivalence checking algorithms. Creates comprehensive formal verification test and coverage plans including definition of formal verification scope, strategy, and techniques. Creates abstraction models for convergence on the design, carves out the right boundaries for the design, and tracks, verifies, and applies abstraction techniques. Develops formal proofs to implement the verification plan, reviews the completed proofs, and develops new formal verification methodologies. Performs convergence on design by creating formal verification methodology, abstraction, and simulation techniques. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Understands the binary decision diagram (BDD) and data flow graph (DFG) for data paths and resolves the BDD complexity on arithmetic. Applies understanding of modeling architecture to simplify and model the problem and uses tools to formally prove protocols and architectures. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: 9+ years of experience in the verification of IPs - This is a leadership role in which a good understanding of common microarchitectures designs is needed Hands on experience in applying formal property verification for Ips signoff at least for 3 years Hands on experience in resolving convergence issues using FV on multiplies- Good handle on FV verification strategy and design partitioning for better convergence. Managing and Guiding juniors in their verification task Stakeholder management - Multiproject tracking and execution Preferred Qualifications: Expertise in FV verification planning and strategies. Good understanding of FV tools and capabilities. Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

About The Role : About The Role ::In this position, you will be working in a team of enthusiastic engineers on High Speed Designs in P and R from RTL to GDSII.You will be part of ACE Group, in the P-Core design team driving Intel's latest CPU's in the latest process technology.Your responsibilities will include but not limited to: Meet the design targets of high performance and low-power digital design. Static timing analysis. Power Optimization. Design Convergence Experience at IP, SoC level. Ability to work in a highly dynamic environment across geographies. Back end design and implementation of new features. Post silicon performance push activities. PPA improvement and Methodology improvements Qualifications You must possess a Masters Degree in Electrical or Computer Engineering with atleast 10 or more years of experience in related field or a Bachelors Degree with at least 12 years of experience. Technical Expertise in Synthesis, Placement, CTS, Post-Route Optimization and P and R tools (CDNS and SNPS) Preferred Qualifications:- Familiarity with Verilog/ VHDL - Tcl, Perl, Python scripting Strong verbal and written communication skills Inside this Business Group The Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core „¢, and critical IPs that power Intel's leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. -Provide technical leadership in conceptualizing and architecting the frontend digital design of our products, defining micro-architecture and driving successful implementation. -Mentor and guide the team, drive processes and design principles aimed at achieving high quality designs and PPA. Should stay abreast with the standard specifications, develop insights into customer requirements and PPA trends and help define product feature roadmap. -Must have experience of being involved in product development from concept to silicon and must be able to contribute technically across the cross-functions. Should be able to provide technical support for pre-sales and customer enablement. We re doing work that matters. Help us solve what others can t.

About The Role : ou will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology. In this position, you will be responsible for leading the design analysis and methodologies of the different types of memory blocks. Your responsibilities will include but not limited to: 1. Responsible for methodology enablement for memory blocks to meet over 5GHz Freq and low-power digital designs with optimal area.2. In depth understanding of different memory design concepts ((SRAM/RF/ROM).3. Expertise in Static timing analysis concepts.4. Close work with Layout and Floor planning teams.5. Back end design implementation of new features.6. Expertise in Memory post silicon analysis. 7. Good understanding of statistical variation. 8. Planning, implementing and analyzing clock distribution from Full Chip level to leaf level for CPU cores. Qualifications You must possess a Masters Degree in Electrical or Computer Engineering with atleast 8 or more years of experience in related field or a Bachelors Degree with atleast 10 years of experience. Technical Expertise in synthesis, P and R tools preferred. Preferred Qualifications: 1. Digital Design Experience, with High Speed, Low Power.2. Familiarity with Verilog/VHDL.3. Tcl, Perl, Python scripting. 4. Good understanding of spice simulations and analysis 5.Custom circuit design, IO design, full chip clocking6. Strong verbal and written communication skills. Inside this Business Group The Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core „¢, and critical IPs that power Intel's leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies.