5.0 - 9.0 years

0 Lacs

hyderabad, telangana

On-site

You will work in the AMS Verification domain, requiring relevant experience in mixed signal SOCs or subsystems/IPs. Leading a project for AMS requirements is considered a value add. Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools is essential. You should have knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles. Analog circuit basics understanding is necessary, and previous analog design experience would be a plus. You should be familiar with the concepts of behavioral modeling, including digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from a mixed signal perspective is advantageous. Functional knowledge of analog and mixed signal building blocks such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected. Previous experience working on AMS Verification on multiple SOCs or sub-systems is required. Working knowledge of Perl/Skill/Python/Tcl or other scripting relevant languages would be beneficial. You must possess the ability to lead a project team and work collaboratively in a multi-site development environment. Being delivery-oriented, passionate to learn and explore, transparent in communication, and flexible related to project situations is important. A good knowledge of analog and mixed signal electronics, test-plan development, tools, and flows is necessary. You will be responsible for developing and executing top-level test cases, self-checking test benches, and regression suites. Additionally, you will develop and validate high-performance behavior models and verify block-level and chip-level functionality and performance. Being a team player with good communication skills and having previous experience in delivering solutions for a multi-national client is valuable. You should be fluent with Cadence-based flow, creating schematics, Simulator/Netlist options, etc. Ability to extract simulation results, capture them in a document, and present them to the team for peer review is required. Supporting silicon evaluation and comparing measurement results with simulations is part of the role. Having UVM and assertion knowledge would be an advantage.,

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