Senior STA Engineer Nextgensilicon Technologies

5.0 - 10.0 years

15 - 30 Lacs

bengaluru

Work from Office

Role & responsibilities Develop, validate, and maintain STA constraints (SDC) for multiple design modes and corners (functional, test, scan, BIST, low power, etc.). Own DFT timing constraints (scan shift, capture, at-speed test, boundary scan, MBIST, LBIST, JTAG). Collaborate with DFT and Physical Design teams to ensure test structures meet timing closure requirements. Work with synthesis, P&R, and STA teams to merge functional and test-mode constraints consistently. Debug timing violations across functional and DFT modes, and propose fixes (false paths, multicycle paths, case analysis, test clocks). Ensure SDC quality by writing scripts/checkers for constraint consistency, redundancy, and c...

Posted 2 weeks ago

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Associate III - VLSI-Physical Design-SV UST

5.0 - 9.0 years

0 Lacs

karnataka

On-site

The role requires a Physical Design Engineer with a strong foundation in the basic fundamentals of C-MOS technology. You are expected to possess a deep understanding of the PD Flow for both flat and hierarchal designs. Your responsibilities will include independently handling RTL/Netlist to GDSII at block level/SS/SoC and having experience in multiple tape outs with a focus on low power implementation. Experience in floor planning, Partitioning, integration at Subsystem/Chip will be considered an advantage. You should have practical experience with Lower technology nodes such as 3nm, 5nm, 7nm, 10nm, 14nm, 16nm, and 28nm. Proficiency in floor planning, placement optimizations, CTS, and routin...

Posted 2 months ago

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