Associate III - VLSI-Physical Design-SV UST

5.0 - 9.0 years

0 Lacs

karnataka

On-site

The role requires a Physical Design Engineer with a strong foundation in the basic fundamentals of C-MOS technology. You are expected to possess a deep understanding of the PD Flow for both flat and hierarchal designs. Your responsibilities will include independently handling RTL/Netlist to GDSII at block level/SS/SoC and having experience in multiple tape outs with a focus on low power implementation. Experience in floor planning, Partitioning, integration at Subsystem/Chip will be considered an advantage. You should have practical experience with Lower technology nodes such as 3nm, 5nm, 7nm, 10nm, 14nm, 16nm, and 28nm. Proficiency in floor planning, placement optimizations, CTS, and routing is essential. You must have hands-on experience in block/top level signoff STA, physical verification checks (DRC/LVS/ERC/antenna), and other reliability checks (IR/EM/Xtalk). Familiarity with industry standard EDA tools from Synopsys, Cadence, and Mentor such as ICC2, Fusion-Compiler, Design Compiler, Primetime, PTSI, IC Validator, Innovus, Genus, Tempus, Encounter, Nanoroute, Calibre, StarRC, Redhawk, and voltage storm is required. Exposure to DMSA flow for ECO generation and implementation is beneficial. A good understanding of VLSI process and proficiency in scripting using TCL, Perl are necessary. Key Skills: Physical design, Innovus, Floor Planning, Signoff STA,

Posted 3 weeks ago

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