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Physical Design Engineer, Sr/Lead/Staff Qualcomm

4.0 - 10.0 years

0 Lacs

hyderabad, telangana

On-site

As a Hardware Engineer at Qualcomm India Private Limited, you will be responsible for the physical design aspects of ASICs, including Place and Route (PnR) flow and methodology. Your key responsibilities will include: - Executing complete PD ownership from netlist to GDS2, encompassing HM level PV, LEC, low-power checks, PDN, and STA closure - Implementing Voltage Islands and low power methodologies, flows, and implementation - Debugging Congestion and Clock Tree Synthesis (CTS) issues - Utilizing PnR tools such as Innovus/Fusion compiler and flow - Familiarity with Sign-off methodologies and tools (PV/PDN/STA/FV/CLP/Scan-DRC(tk)) - Enhancing existing methodologies and flows - Proficiency in...

Posted 3 months ago

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