Senior Management / Leadership - Physical Design AMD

20.0 - 24.0 years

0 Lacs

hyderabad, telangana

On-site

At AMD, we are dedicated to transforming lives with our cutting-edge technology to make a positive impact on our industry, communities, and the world. Our goal is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. Central to our mission is the AMD culture, where we continuously strive for innovation to address the world's most pressing challenges. We are committed to achieving excellence in execution while upholding values of directness, humility, collaboration, and inclusivity of diverse perspectives. As a SOC Physical Design Director at AMD, you will play a ...

Posted 1 month ago

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Mobile Banking- UPI Payments krazy mantra hr solutions

2.0 - 6.0 years

0 Lacs

maharashtra

On-site

The job involves verifying, recording, and reporting on transactions related to money transfers between parties. Additionally, the role requires UAT testing and sign off for production movement. The ideal candidate should have a notice period of immediate to 90 days. The educational qualifications required for this position are BE/BTech, ME/MTech, or MCA. The location of the job is in Mumbai. For further inquiries or to apply for the position, please send your resume to career@krazymantra.com.,

Posted 1 month ago

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STA Full Chip Lead ACL Digital

8.0 - 13.0 years

35 - 65 Lacs

Hyderabad, Pune, Bengaluru

Work from Office

Job Title: STA Full-Chip Lead Location: Bangalore / Hyderabad / Noida / Chennai (Hybrid or On-site) Experience: 8 18 Years Job Type: Full-Time | Permanent Industry: Semiconductor / VLSI / ASIC Design Functional Area: Physical Design / STA / Timing Signoff Job Description We are seeking an experienced and detail-oriented Full-Chip STA Lead to join our high-performance ASIC/SOC design team. You will be responsible for leading full-chip static timing analysis (STA) efforts, driving timing convergence, and managing STA signoff activities across multiple blocks and subsystems. This is a lead-level role requiring deep technical expertise in STA flows and tools, as well as the ability to collaborat...

Posted 4 months ago

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STA lead Xanika Infotech

8.0 - 11.0 years

25 - 30 Lacs

bengaluru

Work from Office

Role & responsibilities We are seeking an experienced Full-Chip STA Engineer to drive timing closure and sign-off across the entire SoC/ASIC design. The role requires expertise in multi-block integration, multi-mode/multi-corner analysis, and sign-off methodology for advanced technology nodes. Key Responsibilities: Perform full-chip static timing analysis for all functional and test modes across multiple PVT corners. Own SDC constraint generation, validation, and refinement at top-level. Collaborate with block-level STA, physical design, synthesis, and clock teams to achieve timing closure . Debug and resolve full-chip setup/hold violations through ECOs, floorplan changes, and clock optimiza...

Posted Date not available

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