ASIC Design Engineer : RTL Design / Verilog / System Verilog Cisco

7.0 - 12.0 years

9 - 14 Lacs

Bengaluru

Work from Office

Cisco's silicon team provides an outstanding, unique experience for ASIC engineers by combining the resources offered by a sizable multi-geography silicon organization and a large campus (with an on-site gym, healthcare, caf, social interest groups, and philanthropy) with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact Write micro-architecture specifications and participate in reviews. Implement Verilog RTL to meet timing, performance, and power requirements. Contribute to full chip integration and timing methodology/analysis. Develop and analyze functional coverage. Help define, evolve, and support our design methodology. ...

Posted 3 months ago

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