38 Serdes Jobs - Page 2

Grounds up verification environment development using SV/ UVM is a must5+ yrs Bangalore/ Pune One of the Serdes of high speed protocols like PCIe or USB 3 or MIPI Testplanning, AMS Setup, Experience in wreal, RNM, Verilog A VCS Primesim AMS and Primesim XA tool lExperience in wreal, RNM, Verilog A, exp in System Verilog and UVM

About The Role : Experience in Mixed-Signal layout design, holding bachelors degree To work independently on block levels analog layout design from schematic, estimating the Area, Optimizing Floorplan, Routing and Verifications. Firsthand experience in Critical Analog Layout design of blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence VLE/VXL, PVS, Assura and Calibre DRC/ LVS is a must. Understanding layout effects on the circuit such as speed, capacitance, power and area etc., Ability to understand design constraints and implement high-quality layouts. Multiple Tape out support experience will be an added advantage. Good people skills and critical thinking abilities to resolve the issue technically, and professionally. Excellent communication. Responsible for timely execution with high quality of layout design. Primary Skills Analog Layout Process or technology experience:TSMC 7nm, 5nm, 10nm,28nm, 45nm,40nm EDA Tools: Layout Editor:Cadence Virtuoso L, XL Physical verification:DRC,LVS,Calibre Secondary Skills IO layout

We are looking for an experienced Rust Developer to contribute to a cutting-edge project focused on evaluating AI-assisted Rust development. This role involves working on real-world Rust codebases, implementing features, debugging, refactoring, and writing comprehensive tests to ensure memory safety and correctness. Responsibilities: Navigate and modify complex Rust codebases using CLI tools like grep and ripgrep. Implement new features with a focus on memory safety, ownership rules, and type correctness . Write and execute tests using cargo test, including property-based testing (proptest or quickcheck). Refactor existing Rust code while maintaining functionality and performance. Debug and fix memory safety, ownership, and concurrency-related issues . Set up and manage Rust development environments using cargo, including handling dependencies and feature flags. Ensure best practices in Rust development, including proper error handling, concurrency safety, and efficient memory usage. Requirements: Strong experience with Rust programming language concepts , including ownership, borrowing, and lifetimes. Familiarity with Rust frameworks like Tokio, Actix, Rocket and libraries such as Serde and Rayon . Experience with Rusts testing ecosystem , including unit, integration, and property-based testing. Knowledge of multi-threading and asynchronous programming in Rust. Ability to work with complex architectural patterns and refactor code without introducing regressions. Strong debugging skills, including fixing memory and concurrency issues. Experience with performance profiling and benchmarking in Rust (cargo bench). 4+ years of work experience This role provides an opportunity to work on challenging Rust engineering problems while improving AI-assisted programming workflows. If youre passionate about Rust and eager to push the boundaries of AI-driven software development, wed love to hear from you! Nice to Have: Experience contributing to open-source Rust projects. Familiarity with writing Rust documentation and designing APIs with doc-tests . Application Link : https://developers.turing.com/invite/eyJhbGciOiJIUzI1NiIsInR5cCI6IkpXVCJ9.eyJqb2JJZCI6MjI2MzQsInVzZXJJZCI6MTE3NCwidXNlclJvbGUiOiJUQV9TT1VSQ0VEIiwiaWF0IjoxNzQxNjMxMzEyfQ.QET0bMcgUFfRkRWigVlcmZ6v1OjCsyQ1mBSY-hGAykI

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. About The Role : Experience:8 to 12 years The candidate should have good understanding of analog and mixed signal circuits with experience in high-speed links such as DDR PHY and/or Serdes Experience with high-speed digital circuits, memories and lab. testing is desirable Experience with Tx/Rx equalization techniques and circuits like de-emphasis, CTLE, DFE is desirable Knowledge of DDR protocols is desirable Ability to work in a dynamic environment and interact well with cross-functional teams such as design, boards, ATE etc. Applicants :Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies :Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Serdes PHY Analog Design Job Function BDC SerDes Mixed-Signal design team is actively looking for experienced (4-12+ years) analog circuit designers to work on high speed SerDes PHYs . You will be directly involved in delivering next-generation custom PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading-nodes - finfets & beyond. Design goals include low-power analog designs to address Qualcomm's low-power wireless products. Responsibilities Hands-on experience - Analog circuit design Experience in designing multiple analog building blocks - LDO, high speed TX and RX (Equalizer, Sampler, PI, Deserializer etc) , Bias, Reference etc. Analog and or Digital PLLs for frequency synthesis and/or SerDes applications" Charge pump, loop filter, VCO/DCO, PFD/TDC, high speed dividers. PLL Loop Dynamics, Jitter sources and modeling (RJ & DJ) Ability to take a design, perform schematic to post layout verification, integration sign-off to post silicon bring up. Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY.

About The Role : Experience in Mixed-Signal layout design, holding bachelors degree To work independently on block levels analog layout design from schematic, estimating the Area, Optimizing Floorplan, Routing and Verifications. Firsthand experience in Critical Analog Layout design of blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence VLE/VXL, PVS, Assura and Calibre DRC/ LVS is a must. Understanding layout effects on the circuit such as speed, capacitance, power and area etc., Ability to understand design constraints and implement high-quality layouts. Multiple Tape out support experience will be an added advantage. Good people skills and critical thinking abilities to resolve the issue technically, and professionally. Excellent communication. Responsible for timely execution with high quality of layout design. Primary Skills Analog Layout Process or technology experience:TSMC 7nm, 5nm, 10nm,28nm, 45nm,40nm EDA Tools: Layout Editor:Cadence Virtuoso L, XL Physical verification:DRC,LVS,Calibre Secondary Skills IO layout

Analog Circuit Design Circuit Design implementation of SERDES blocks like Transmitter, FFE, Receiver, CTLE, DFE, Summer, SAL/Design of basic analog IPs like ADC/DACs, PLLs, Oscillators, General Purpose IOs, Temperature sensor etc/Design of blocks like LDOs, Band Gap reference, Current Generators, POR. Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do Conduct verification of the module/ IP functionality and provide customer support Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology Create test bench development and test case coding of the one or multiple module Write the codes or check the code as required Execute the test cases and debug the test cases if required Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed Test the entire IP functionality under regression testing and complete the documentation to publish to client Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency Write scripts for the IP Comply with project plans and industry standards Ensure reporting & documentation for the client Ensure weekly, monthly status reports for the clients as per requirements Maintain documents and create a repository of all design changes, recommendations etc Maintain time-sheets for the clients Providing written knowledge transfer/ history of the project Stakeholder Interaction Stakeholder Type Stakeholder Identification Purpose of Interaction Internal Tech Lead/ Architect/ Product Owner Regular reporting & updates, testing and debugging etc. External Client technical team (Product Owner, Engineering Manager, Scrum Master) Scripts of test cases, escalations etc Display Lists the competencies required to perform this role effectively: Functional Competencies/ Skill Leveraging Technology - Knowledge of current and upcoming technology along with expertise in programming (automation, tools and systems) to build efficiencies and effectiveness in own function/ Client organization - Competent Process Excellence - Ability to follow the standards and norms to produce consistent results, provide effective control and reduction of risk - Expert Domain knowledge - Industry knowledge as per the project requirement and industry standards of various processes - Competent Technical Knowledge - Knowledge of System Verilog (UVM/OVM), RTL verification, languages (HDL/ HVL) - Competent to Expert Competency Levels Foundation Knowledgeable about the competency requirements. Demonstrates (in parts) frequently with minimal support and guidance. Competent Consistently demonstrates the full range of the competency without guidance. Extends the competency to difficult and unknown situations as well. Expert Applies the competency in all situations and is serves as a guide to others as well. Master Coaches others and builds organizational capability in the competency area. Serves as a key resource for that competency and is recognised within the entire organization. Behavioral Competencies Process Orientation Innovation Managing Complexity Client centricity Execution Excellence Passion for Results Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 3. Self-development Skill test for next level clearance on Trend Nxt

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Develop the verification environment and test bench and creating testcases. Debug fails using waveform, trace tools and debug RTL code Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3 + years of experience in Functional Verification of Processors or ASICs. Minimum 2+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Multi-processor cache coherency, Memory subsystem, IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc Madhu to update ASICs specific skills Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Good object-oriented programming skills in C/C++, and any of scripting languages like Python/Perl Development experience on Linux/Unix environments and in GIT repositories and basic understanding of Continues Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in verification coverage closure Preferred technical and professional experience Verify the different functions/components in a PCI Express Controller & high speed SERDES (PHY). Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Responsibilities As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Develop the verification environment and test bench and creating testcases. Debug fails using waveform, trace tools and debug RTL code Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Required technical and professional expertise 5 + years of experience in Functional Verification of Processors or ASICs. Minimum 3+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Multi-processor cache coherency, Memory subsystem, IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Good object-oriented programming skills in C/C++, and any of scripting languages like Python/Perl Development experience on Linux/Unix environments and in GIT repositories and basic understanding of Continues Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in verification coverage closure Preferred technical and professional experience Verify the different functions/components in a PCI Express Controller & high speed SERDES (PHY). Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug Formal verification experience

• Hands –On EXP. on atleast 2/ 3 of Analog Blocks • Good Understanding of Analog blocks like Op-amps, BGR’s, LDO’s, PLL’s , Clocking circuits, TX / RX. • EXP. on High Speed SERDES/ Memory Circuits is a Plus Required Candidate profile • Exposure to cutting edge technology nodes like FinFets is a Plus • Strong Analog Design Fundamentals

Job Title: Analog Circuit Design Engineers Design of LDOs, Bandgaps, Temp Sensors, PLLs, GPIOs and other analog blocks Design of SERDES blocks like Transmitters, Receivers, Equalizers, Calibration and compensation blocks.

Design of LDOs, Bandgaps, Temp Sensors, PLLs, GPIOs and other analog blocks Design of SERDES blocks like Transmitters, Receivers, Equalizers, Calibration and compensation blocks.

Responsibilities 1. Hands on work on custom layout for analog blocks like High Speed SerDes and General purpose IO designs with Cadence Virtuoso on latest technologies like 5nm and below and also take leadership roles in delivery of IPs 2. Work on Floor planning, power design, signal routing strategy, EMIR awareness andparasitic optimisations 3. Understand and apply analog Layout techniques to ensure the design meets performance with minimum possible area and good yield. 4. Participate in building and enhancing layout flow for faster, higher quality design process. 5. Checking physical verifications like DRC/LVS/ERC/ANT/DFM and other IBM internal checks 6. Collaborate with Circuit Designers to solve challenging problems 7. Writing SKILL/PYTHON scripts to automate repetitive tasks 8. Work with Place and Route engineer to integrate custom macros into top level. 9. Able to perform design reviews across global team 10. Work closely with required global teams to ensure the success of the whole product. 11. Leadership in delivery of macros we plan to own from India Job requirements: 1. Experience in doing layouts for analog blocks like SerDes, ADCs, DACs, LDOs, PLLs, BGAP & amplifiers etc. 2. Experience in designing layouts for high-speed circuits is a plus. 3. Layout experience in the following technology nodes:3nm, 5nm and 7nm FinFET. 4. Good team worker with multi-discipline, multi-cultural and multi-site environments 5. Strong fundamental knowledge in semiconductor device physics, layout principles, IC reliability and failure mechanisms 6. Good problem-solving skills are essential where problems are analysed upfront, identifying gaps, and providing optimum solutions7. Knowledge in Skill/perl/tcl/Python scripting is a plus. Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise The Analog layout design engineer with experience in next generation Ultra high speed serial IO link (HSS) interface for Cognitive, ML,DL, and data center applications. The engineer needs to have knowledge in the design and development full custom analog layouts for ultra high speed 32G/50G/112G IO link interfaces. Preferred technical and professional experience Experience in 7 and 14 nm analog layout design. Working on Cutting edge technology and HSS domain . Quick learner, deep layout design knowledge, problem solving skills and good communication skills with cross teams across the Geos.