Analog Design, Principal Engineer Synopsys

15.0 - 19.0 years

0 Lacs

noida, uttar pradesh

On-site

Role Overview: You are an experienced Analog and Mixed-Signal (A&MS) Senior Circuit Design Expert with a specialization in PLL and SERDES design. Your expertise lies in mixed-signal techniques for power reduction, performance enhancement, and area reduction. You excel in developing Analog Full custom circuit macros for High Speed PHY IP in advanced technology nodes. Collaboration and nurturing key analog design talent are key aspects of your role. Key Responsibilities: - Leading Serdes analog design and development. - Analyzing mixed signal techniques for power reduction, performance enhancement, and area reduction. - Developing Analog Full custom circuit macros for High Speed PHY IP. - Coll...

Posted 1 week ago

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Senior Staff Analog Design Samsung Electronics

5.0 - 12.0 years

0 Lacs

karnataka

On-site

As a Senior Analog Designer with 5-12 years of relevant experience in Analog and Mixed Signal Design, you will be responsible for the following: - Designing Low Jitter and high frequency PLLs, including experience with both LC and Ring based PLLs - Handling General Purpose ADC and thermal Sensors IP design - Working on High-speed Serdes Design - Designing LDO, BGR, and other power management blocks The ideal candidate for this role should be prepared for challenging design experiences and exposure to silicon validation. You will have the opportunity to gain full exposure to the IP design cycle in advanced Samsung foundry processes at 4nm and below. Qualifications required for this position i...

Posted 1 month ago

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RTL - Architect Ambit Semiconductors Private Limited

8.0 - 12.0 years

0 Lacs

karnataka

On-site

As an RTL Architect SERDES at Ambit Semiconductors Private Limited, you will play a crucial role in defining and owning the RTL architecture for high-speed and many lanes SERDES IPs. Your responsibilities will include leading RTL design, coding, and integration of SERDES blocks, collaborating with various teams for seamless integration, driving micro-architecture development, and supporting post-silicon validation efforts. Additionally, you will mentor junior engineers and provide technical leadership in design reviews. Key Responsibilities: - Define and own the RTL architecture for high-speed and many lanes SERDES IPs. - Lead RTL design, coding, and integration of SERDES blocks. - Collabora...

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Analog Design, Staff Engineer Synopsys Inc

4.0 - 6.0 years

0 Lacs

hyderabad, telangana, india

On-site

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned Analog Design Engineer with a passion for pushing the boundaries of high-speed analog and mixed-signal design. You have a deep understanding of CMOS design fundamentals and a proven track record in implementing circuits for analog and mixed-signal building block...

Posted 3 months ago

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Senior Staff Analog Design Samsung Electronics

5.0 - 12.0 years

0 Lacs

karnataka

On-site

As a Senior Analog designer with 5-12 years of relevant experience in Analog and Mixed Signal Design, you will be responsible for Full IP design in one of the following domains: - Low Jitter and high-frequency PLL Design, including experience in both LC and Ring-based PLL design. - General Purpose ADC and thermal Sensors IP design. - High-speed Serdes Design. - Design of LDO, BGR, and other Power management blocks. The ideal candidate should be prepared for challenging design experiences and exposure to silicon validation. You will have the opportunity to work on the full IP design cycle in the advanced Samsung foundry process, specifically focusing on 4nm and below technologies. To be consi...

Posted 4 months ago

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