Senior RTL Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiencesfrom AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challengesstriving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

Together, we advance your career.

MTS SILICON DESIGN ENGINEER

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The Role

The focus of this role is to plan, build, and execute the design and validation of new and existing features for AMD's DDR IPs.???

THE PERSON:

?Collaborate with cross-functional teams to design and integrate DDR memory controller calibration solutionsincluding RTL logic, firmware routines, and algorithmic flowsinto AMD's system-level validation and bring-up environments. Ensure seamless interaction between hardware and firmware components, delivering reliable calibration performance aligned with silicon and platform requirements

KEY RESPONSIBILITIES:

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• Design and implement robust firmware solutions for DDR memory controller calibration across various DDR standards
• Develop and refine calibration algorithms to ensure reliable memory initialization and operation under varying process, voltage, and temperature (PVT) conditions. Focus on improving accuracy, convergence speed, and adaptability of calibration routines
• Create and execute validation plans to verify the correctness and performance of calibration firmware and algorithms. Perform system-level bring-up and debug activities to identify and resolve issues related to memory training and stability
• Work closely with silicon design, verification, and system engineering teams to align calibration firmware with hardware capabilities and system requirements. Ensure seamless integration and interoperability across the full memory subsystem
• Develop clear and comprehensive documentation for calibration flows, firmware APIs, and algorithm behavior. Ensure alignment with JEDEC specifications and internal design guidelines
• Stay updated with emerging DDR technologies and calibration techniques. Propose and implement innovative solutions to improve calibration robustness, reduce boot time, and support next-generation memory interfaces
  

PREFERRED EXPERIENCE:

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• B.E/M.E/M.Tech or B.S/M.S in EE/CE with 9+ years of relevant experience
• Digital design and experience with RTL design in Verilog/SystemVerilog, Knowledge of system-level architecture including buses like AXI/AHB, bridges
• Circuit timing/STA, and practical experience with tools
• Working knowledge of C; embedded experience a plus
• Understanding of memory technologies such as DDR4, DDR5, LPDDR, and JEDEC standards
• Been exposed to memory controller and PHYs from different IP vendors
• Experienced with implementing DRAM/memory controller initialization code, memory subsystem/DDR PHYs training/calibration software
• Version control systems such as Perforce, ICManage or Git
• Familiar with industry standard lab tools (such as: high speed scope, compliance packages, logic analyzers) is a plus
• Strong verbal and written communication skills
• Should have experience working in geographically dispersed team and should be a strong team player
  
  
  

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ACADEMIC CREDENTIALS:

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