Senior CAD Engineer

As part of the Engineering Enablement organization at ADI, this senior-level CAD engineer will work on developing and testing of the QA framework used in the validation of Process design kits (PDK) for internal and external semiconductor process technologies used in the design and manufacturing of analog, mixed signal, power management and DSP products in ADI. As an individual contributor, you will be expected to possess the necessary programming skills and circuit design knowledge to develop, support, enhance and test the PDK QA flow used at ADI. The PDK QA functions involve checking of the PDK deliverables such as schematic symbols, layout p-cells, CDFs, DRC/LVS decks, technology files used in Parasitic extraction, ESD verification and other reliability-based flows for quality issues prior to the release of a PDK. You will also develop process design kits (PDKs) for internal and external process technologies in support of Analog, RF, Mixed-Signal, and Digital design flows using Cadence, Mentor, Keysight and internally developed CAD software.

Primary responsibilities:

• Develop device level layout generators (PCELLs)
• Develop physical verification (DRC/LVS) rules and parasitic extraction flows
• Closely work with developers of front-end and back-end components of PDK to create/enhance test cases to actively improve QA coverage.
• Ability to interpret process as well as assembly/packaging design rule specifications to ensure test cases are representative of design rule checks implemented in DRC decks.
• Understand Layout Vs. Schematic (LVS) flow intent and create representative test cases for validating LVS decks.
• Automatic Test case generation and unit testing to ensure there is adequate test coverage for validating the different PDK components.
• Test case debugging investigate if PASS/FAIL test cases are being generated and functioning as per requirements.
• Provide technical CAD support for ADI design community
• Work closely with the design teams to understand their requirements and colloborate with device modeling, process development and foundry groups to enable the efficient use of CAD tools and methodologies
• Create test cases for validating netlists generated for internal/external analog circuit simulation tools.
• Test case generation for testing the accuracy of Parasitic Resistance/Capacitance extraction technology files.
• Perform validation of techfiles used in ESD verification, such as topology checks, ESD resistance and current density checks.
• Work closely with the EDA software vendors to resolve tool bugs and drive new feature additions.

Qualifications:

• Minimum 6+ years of experience in developing PDKs and writing programs for automation
• BS/MS in Electrical or Computer Engineering with an emphasis on IC design and semiconductor processes
• Knowledge of Python Programming Language and Cadence Skill Language is essential.
• Proven skills in other programming languages (Perl, Tcl, Bash)
• Must have undertaken automation projects.
• Understanding of analog/mixed signal simulation tools
• Familiarity with physical verification (DRC/LVS) tools
• Knowledge of parasitic extraction tools.
• Familiarity with revision control systems and collaboration tools is a plus.
• Must possess excellent verbal and written communication skills
• Must be detail oriented, well organized and a versatile team player.