Develop verification environments for our ICs using Universal Verification Methodology (UVM); Job Description In your new role you will: create and define verification plans; develop verification environments for our ICs using Universal Verification Methodology (UVM); draw on test scenarios using SystemVerilog; verify functionality using the Constrained Random approach; develop assertions in SystemVerilog for formal verification; Interact with other disciplines, such as Concept and ApplicationEngineering, to define verification plans and strategies; provide proactive support to users of our verification flowenvironment; be responsible for our verification methods; Your Profile You are best equipped for this task if you have: You have successfully completed a university degree in Electrical Engineering, Computer Science or a similar academic discipline; You have at least 3 years of experience in Constrained-Random Metric-Driven Verification You have capabilities and experience in working withmicrocontroller-based ICs, as well as security and safety requirements; You have good know-how with UVM especially using SystemVerilog; Have knowledge of firmware and RTL design (VHDL); Ideally have knowledge of working with Verification IPs (VIPs) Contact: swati.gupta@infineon.com We are on a journey to create the best Infineon for everyone.

Software Validation of device drivers used for Communication or signal generation/measurements (Eg: SPI, UART, PWM, ADC, DMA etc.) and safety software in an independent/RTOS environment on Infineon s Automotive Microcontrollers based on Job Description In your new role you will: Software Validation of device drivers used for Communication or signal generation/measurements (Eg: SPI, UART, PWM, ADC, DMA etc.) and safety software in an independent/RTOS environment on Infineon s Automotive Microcontrollers based on TriCore architecture (AURIX ) or equivalent Support Leads with WBS definition and Estimations. Envisage, implement, institutionalize and maintain the verification and validation methods and infrastructure (e.g. automation to improve quality and efficiency in terms of cost and time) Drive innovation in the form of new advancements (test methods/tools, test automation, test infrastructure). Institutionalize software test processes compliant with Automotive standards (e.g.ISO26262, ASPICE). Ownership of reviews - Test Specifications & Scripts Your Profile You are best equipped for this task if you have: A minimum of 4-8 years of experience in Device Driver software testing which includes a good know how of standard software development Life Cycle Experience in AUTOSAR MCAL and exposure to ISO26262 Embedded system software development or Validation using C , assembly languages Experience in the usage of NI, FPGA, oscilloscopes, logic analysers, power benches etc Experience in Embedded System Development tools such as compilers, debuggers (PLS,Lauterbach), static analysers etc Working experience in scripting languages such as Perl, python etc Experience in the development/maintenance of the test automation and continuous integration frameworks We are on a journey to create the best Infineon for everyone.

Platform enabler software development for Infineon s Automotive chipsets. Job Description In your new role you will: AUTOSAR and ISO26262 based microcontroller Complex Device Driver Development and Validation usingvarious peripherals [IO drivers like ADC, SPI, UART, Timers, PORT] of Infineon s Automotive Microcontrollers based on TriCore architecture (AURIX ) or equivalent. Participate and contribute to requirements elicitation and definition phase of the project Develop Architecture, Design, Code for microcontroller complex device drivers Conceptualize and institutionalize develop strategies and engineering practices Perform Static checks (Cyclomatic complexity, MISRA evaluation, Poly space warnings analysis) andUnit Tests Help CoC Head with work breakdown structure and estimates.Support the Senior Engineers by working in PoCs. Your Profile You are best equipped for this task if you have: A minimum of 4-8 years of experience in Device Driver software development which includes a good know how of standard software development Life Cycle. Embedded system Software Development/validation in C, assembly languages & SDLC. Good knowledge on Software Unit Test. Good knowledge of Microcontroller Architecture (16/32bit), real-time systems. Experience in standards such as AUTOSAR, IEC61508, ISO26262 is desirable. Acquaintance with development tool-chains like compiler, static checkers and Unit Test tool. Knowledge about debuggers such as PLS, Lauterbach etc. Good team player in a multi-site work environment. Contact: Gowri Shenoy, LinkedIn We are on a journey to create the best Infineon for everyone.

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures todays innovators stay Ahead of Whats Possible . Learn more at www.analog.com and on LinkedIn and Twitter (X) . Senior/Lead PD Engineer ADI is looking for Senior/Lead PD Engineer for the development of complex mixed Signal SoCs. These chips are manufactured in most leading edge process nodes and high speed clock rates. These SoCs involve multiple processor cores and speed signal processing hardware running at high speed. Position Requirements BTech/MTech degree in Electrical/Electronic from a reputed institute with 4-8 years of experience in the field of Digital place and route Hands on experience with the implementation (PnR Signoff) of complex high speed SoC designs in cutting edge process technologies (22 nm, 16 nm, 7 nm, etc). Hands on experience in handling the tapeout of complex high speed SoC designs in cutting edge process technologies Floor Planning, Power Plan, Place and Route, Clock Planning and Clock Tree Synthesis, Parasitic Extraction Strong expertise in Static Timing analysis , constraint development and sign off. Innovate on the flows to meet the QoR targets and ensure predictability Good understanding on device/interconnect and circuit aspect of the complex UDSM technologies is an added advantage. Being proficient in TCL, Perl etc.

Who are we? Orbit & Skyline India Pvt. Ltd. is a leading semiconductor service provider with a robust and experienced... No of Jobs Mechanical Engineer II Job Opening | Orbit & Skyline India Pvt. Ltd. Who are we? Orbit & Skyline India Pvt. Ltd. is a leading semiconductor service provider with a robust and experienced team of professionals proficient in providing our customers with unique, feature-rich solutions that help them build environmentally friendly semiconductor manufacturing. At Orbit & Skyline, our synergistic cross functional team of Mechanical, Electrical, Electronics, Software, Equipment, and process engineering is delivering end to end solutions to our customers in semiconductor equipment manufacturing space. We are partnering with our customers across the complete semiconductor value chain spectrum that includes Hardware design and development, Supply chain management, Quality management, Product Management, Reliability, Data Science, ML/AI and many more. We are enabling our customers to develop technologies and systems that alter industries by employing one of the most diverse workforces of cutting-edge engineers and technologists in the semiconductor industry. Our clientele includes prestigious IC chip manufacturers and OEMs from the United States, Asia, the Middle East, and Europe with our services being rendered to our global customers out of our head office in Mohali, India. We have offices in the United States, the Middle East, Singapore, Taiwan, Ireland, and several other locations. Who are we looking for? Orbit & Skyline is looking forward to onboarding a "Mechanical Engineer II" to support the full life cycle of mechanical and electro-mechanical systems from concept to productization including conceptualization, designing, CAD modelling, & development. The candidate will be part of a team assisting in the delivery of efficient engineering support and solutions to customers while also contributing to the development of the Indian semiconductor ecosystem. Roles & Responsibilities Support the full life cycle of mechanical and electro-mechanical systems from concept to productization including conceptualization, designing, CAD modelling, & development. Designs components using a variety of metals, ceramics, quartz & plastics Ensure documentation aligns with SEMI standards, and industry best practices for geometric dimensioning and tolerancing (GD&T). Conduct detailed analysis including structural finite element analysis (FEA and manufacturability to properly specify designs. Prepare high technical presentations to communicate design intent, evaluation, and validation to a diverse audience in design reviews. Preparing the part/assembly drawings as per the given standard. Working with cross-functional teams for ECN and ECO activities. Undertake any other duties of a reasonable nature as required by management. Eligibility Criteria Required Qualification: Bachelor s degree in mechanical engineering or a related field with a minimum of 3 years of experience. Master s degree with a minimum of 1 year of experience. Must be comfortable working with US-based timings. Mandatory Skills: Highly proficient in 3D CAD tools, such as SolidWorks and others. Hands-on experimental and design background coupled with solid engineering skills. Practical knowledge of different fabrication methods such as sheet metal forming, CNC machining, injection moulding, and 3D printing. Able to perform basic to moderate levels of structural and thermal analysis using any FEA package. Project management experience, including planning, execution, and finalisation of projects. Risk management skills, including identification, assessment, and mitigation of potential risks in system assembly. Excellent communication, both written and verbal, and technical presentation skills. Good to have Knowledge of design life cycle management tools Experience in the semiconductor industry Ability to multi-task and manage time independently. Why Orbit & Skyline? Orbit & Skyline is an amalgamation of enthusiastic and experienced people working on a remarkable concept, making headway in this industry. Today, the Semiconductor Industry is going through a rapid transformation, and we are proud to be playing a major role in development of the semiconductor ecosystem in India thus providing our employees a platform to grow technically and introducing them to a versatile and sprouting work horizon. We offer a holistic workplace that encourages individuals to attain their full potential. We are a team of thinkers, planners, doers, and risk-takers who work closely together and enjoy the top-notch benefits such as: Safeguarding the health of our employees and their loved ones by providing them Health Insurance . Encouraging healthy, motivated and a happy workforce by providing monthly Wellness Allowances . Supporting effective and efficient communication by providing Communication Allowances . Awarding stability & loyalty of the employees by covering them under the Gratuity act . Providing technical advancements and interpersonal growth through periodic Trainings . Providing Service Award to celebrate employees contributions and show our gratitude for their loyalty and commitment. Rewarding and Recognizing employees efforts and contributions to the companys growth. Encouraging enthusiasm, interaction, and motivation by organising team lunches, team outings, offsite activities, fun Fridays, festival celebrations, and other Engagement events. Job Application Form Please leave this field empty. Mechanical Engineer II Job Opening | Orbit & Skyline India Pvt. Ltd.

OUR STORY At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips forms the hidden part of the world we live in today. When you join ST, you will be part of a global business of more than 115+ nationalities and present in 40 countries, 50,000+, diverse and dedicated creators & makers of technology around the world! Developing technologies takes more than talent: it takes amazing people who understands collaboration and respect. People with passion and desire to disrupt the status quo, push boundaries and drive innovation - whilst unlocking your own potential. YOUR ROLE Looking for a dynamic, committed and a result oriented team member in GBS S2P India (Commission & Incentives team). The desired candidate will play a pivotal role in the management of commission & incentive activities globally for all regions - AME, EMEA, APeC, China, Japan via Salesforce and ServiceNow. JOB PROFILE 1) Audits Business managers submissions of Budgets and validates Results 2) Checks HR Feeds for changes in Plans, Employee details & updates records. 3) Publishes data requested by the Sales teams, HR, Business managers, Finance. 4) Finalises monthly accrual, forecasts, payments of the Sales incentives. 5) Performs and secures approvals for the split searches, adjustments, Rep commission. YOUR QUALIFICATION & EXPERIENCE 1) Graduation degree with specialisation in Finance : BBA / MBA 2) 3-5 years or prior experience in managing sales incentives. SKILLS 1) Expert working knowledge of Excel and Power BI 2) Excellent command over written and spoken English. 3) Skills to perform and flourish in a GBS environment. 4) Ready to work in UK shift timings with few hours of overlap with Americas. Working at ST means innovating for a future that we want to make smarter, greener, in a responsible and sustainable way. Our technology starts with you. Join us and start the future! To discover more, visit st.com/careers

About Analog Devices . Job Title: Software Test Engineer Analog Devices (NASDAQ: ADI) designs and manufactures semiconductor products and solutions. We enable our customers to interpret the world around us by intelligently bridging the physical and digital worlds with unmatched technologies that sense, measure, and connect. Come join Analog Devices (ADI), a place where innovation meets impact. For over 55 years, Analog Devices has been creating groundbreaking technologies that change lives. As a member of the Software Test team, you will play a pivotal role in ensuring the quality, functionality, and reliability of our products. Senior Test Engineer Complexity in consumer systems is growing exponentially. ADI is well positioned to leverage its core sensor and signal processing technology to solve these complex problems. We are looking for an energetic Software Test Engineer who can ensure product quality and functionality using advanced testing methodologies and test strategies. The candidate: Should be able design, develop and execute test cases to validate product features. Should be able to develop test automation frameworks and create regression tests interfacing hardware boards. Should be able to collaborate with software architects and developers to understand product design and provide input on software testing requirements and performance expectations. Should be able to maintain and extend existing build tools and test scripts. Should be able to validate requirements and bug fixes to ensure that they meet the acceptance criteria. Primary Qualifications: BS or MS in Electrical or Computer Engineering or related field 3+ years of Industrial experience in the Test suite design, development Strong Python and C/C++ programming skills Strong experience with integrating, building, and testing of multi-threaded applications. Experience with system level tests on multi-core environments Experience with embedded real-time operating systems Experience with SCM tools (GIT, SVN, Clearcase, Perforce, etc.) Experience with defect tracking tools (Jira, Bugzilla, etc.) Working knowledge of digital signal processing (DSP) and algorithm testing experience Experience with machine learning, deep neural network technologies, PyTorch, TensorFlow platforms Secondary Qualifications: Working knowledge of a software development process (e.g., Agile, Waterfall) Conceptual understanding on Object-Oriented concepts and methodologies Working system-level knowledge in audio, video and TWS domains

Description Enphase Energy is a global energy technology company and a leading provider of solar, battery, and electric vehicle charging products. Founded in 2006, our innovative microinverter technology revolutionized solar power, making it a safer, more reliable, and scalable energy source. Today, the Enphase Energy System enables users to make, use, save, and sell their own power. Enphase is also one of the most successful and innovative clean energy companies in the world, with more than 80 million products shipped across 160 countries. We are building teams that are designing, developing, and manufacturing next-generation energy technologies and our work environment is fast-paced, fun and full of exciting new projects. If you are passionate about advancing a more sustainable future, this is the perfect time to join Enphase! About The Role We are looking for a Product Marketing Manager to bring our industry-leading Small System Solutions (Balcony Solar and upcoming products) to the market, working with a cross-functional and international team. This role works at the intersection of marketing, product, sales, and support to drive launch excellence by building and meeting deadlines, defining milestones and timelines, and driving business processes and initiatives. What you will do B eing an integral part of the GTM team and work with sales, product management and engineering to thoroughly understand the product value proposition and its USPs. Participate in strategic thinking for product market positioning, competitive analysis, messaging hierarchies, and value drivers C reate go to market strategies for individual product and platform launches , resulting in a comprehensive marketing plan that you will drive to execution Work across marketing functions to activate support for product launche s , including PR/comms, website, webstore, social, operations, and creative/design. Who You Are And What You Bring 5+ years of experience in product management, product design, product marketing, or brand roles in global, high-growth B2B and D2C technology companies Bachelors degree or equivalent experience , MBA preferred Strong technical aptitude regarding hardware products and tech suites within sustainable energy and/or semiconductor industry Excellent project and workflow management skills; ability to prioritize and manage multiple projects Comfortable working in a hands-on, fast-paced, growth-focused environment Team player with international experience A climate crusader who is passionate about creating a more sustainable and equitable future

Overview Keysight is on the forefront of technology innovation, delivering breakthroughs and trusted insights in electronic design, simulation, prototyping, test, manufacturing, and optimization. Our ~15,000 employees create world-class solutions in communications, 5G, automotive, energy, quantum, aerospace, defense, and semiconductor markets for customers in over 100 countries. Learn more about what we do. Our award-winning culture embraces a bold vision of where technology can take us and a passion for tackling challenging problems with industry-first solutions. We believe that when people feel a sense of belonging, they can be more creative, innovative, and thrive at all points in their careers. Responsibilities The position lies in Invoice Processing team in Accounts Payable. The person should possess sound knowledge of overall P2P flow with good understanding of Accounts Payable process. The key responsibilities and expectations from this role involve: Working closely with vendors and business requestors for gathering the information as per the local tax and banking requirements before performing the vendor set up in Oracle. Providing active support on various internal & external audits and projects. Trouble shooting employee & vendor queries. Should have the ability to perform root cause analysis and apply permanent fix. Should have good accounting and analytical skills. Exposure to Oracle R-12 or any other ERP. Knowledge of AP module preferred. Should possess effective communication skills - verbal and written. Should be a team player, flexible and responsible. Qualifications MBA with 2-4 years of AP experience of experience from good reputed MNC Careers Privacy StatementKeysight is an Equal Opportunity Employer. The position lies in Invoice Processing team in Accounts Payable. The person should possess sound knowledge of overall P2P flow with good understanding of Accounts Payable process. The key responsibilities and expectations from this role involve: Working closely with vendors and business requestors for gathering the information as per the local tax and banking requirements before performing the vendor set up in Oracle. Providing active support on various internal & external audits and projects. Trouble shooting employee & vendor queries. Should have the ability to perform root cause analysis and apply permanent fix. Should have good accounting and analytical skills. Exposure to Oracle R-12 or any other ERP. Knowledge of AP module preferred. Should possess effective communication skills - verbal and written. Should be a team player, flexible and responsible.

Overview Keysight is on the forefront of technology innovation, delivering breakthroughs and trusted insights in electronic design, simulation, prototyping, test, manufacturing, and optimization. Our ~15,000 employees create world-class solutions in communications, 5G, automotive, energy, quantum, aerospace, defense, and semiconductor markets for customers in over 100 countries. Learn more about what we do. Our award-winning culture embraces a bold vision of where technology can take us and a passion for tackling challenging problems with industry-first solutions. We believe that when people feel a sense of belonging, they can be more creative, innovative, and thrive at all points in their careers. Responsibilities The position in Accounts Payable. The person should possess sound knowledge of Accounts Payable process in addition to meeting following key requirements: > Should have good accounting and analytical skills. > Should have worked on Oracle R-12 or any other ERP. Knowledge of AP module preferred. > Should be able to support various audits and projects. > Should be able to trouble shoot employee & vendor queries. Should have the ability to perform root cause analysis and apply permanent fix. > Must be able to provide strong support to the team. > Should possess effective communication skills - verbal and written. Qualifications MBA with 6-7 years of AP experience of experience from good reputed MNC. Careers Privacy StatementKeysight is an Equal Opportunity Employer. The position in Accounts Payable. The person should possess sound knowledge of Accounts Payable process in addition to meeting following key requirements: > Should have good accounting and analytical skills. > Should have worked on Oracle R-12 or any other ERP. Knowledge of AP module preferred. > Should be able to support various audits and projects. > Should be able to trouble shoot employee & vendor queries. Should have the ability to perform root cause analysis and apply permanent fix. > Must be able to provide strong support to the team. > Should possess effective communication skills - verbal and written.

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures todays innovators stay Ahead of Whats Possible . Learn more at www.analog.com and on LinkedIn and Twitter (X) . Principal Technical Program Manager Analog Devices Software Engineering Solutions group is seeking an experienced senior-level Program Manager to oversee development of cutting-edge software product solutions for next generation SoC products . The successful candidate will be responsible for leading programs through the product lifecycle, taking responsibility for planning, execution, and driving PM processes. Job requirement: BS or MS degree in EE or Comp Sci. Typically requires minimum of 10 years related and progressive experience with program management in the software field. Management of large-scale projects with global teams Strong technical background; you have been a developer earlier in your career. Ability to manage all aspects of programs including technical, financial, legal and customer interactions. Ability to effectively use program management tools to plan, drive and report on projects. Demonstrated leadership, decision-making, teamwork, interpersonal and communication skills are essential coupled with an excellent execution track record working in large multi-discipline development teams spanning multiple time zones. Strong analytical skills. Ability to solve complex problems through design of appropriate experiments and analysis of complex data. Strong embedded software knowledge and an understanding of the hardware development process. Experienced with the tasks related to the New Product Introduction (NPI) process as it relates to combined HW/SW programs. Works with the developers directly to plan, status, track progress, and deduce schedule impacts. Excellent organizational skills and the ability to drive aggressive schedules. A natural leader and facilitator. Proficient with Microsoft Office Software and tools. Proficient with Atlassian products (Confluence, Jira). Positive attitude and proactive / self-motivated / willing to accept responsibility. Certified Scrum Master preferred. PMI PMP preferred. Some travel required. Job responsibilities: Own and drive large-scale software programs to meet ADI business objectives. Manage projects to meet defined scope, schedule, budget and quality requirements. Drive risk management and defect tracking to solve problems before they arise. Lead software requirements and change management to meet customer expectations. Manage resource requirements and allocations. Ensure that program management KPIs are met through project metrics. Lead project core teams and provide clear and concise reports for management. Drive standardized PLC processes throughout the company. Implement continuous improvement and continuous learning mentality with teams. Drive retrospectives and lessons learned activities. The ideal candidate is results-driven and self-motivated with experience in software program management, a track record of execution excellence, and the ability to communicate and work effectively with business and technical teammates at all levels of the organization. You are someone who started off as an engineer/developer and migrated to project/program management over your career. You are typically the most structured and organized individual in your organization. You know how to get the right things done on time in an organization.

Diploma OR Engineering Freshers (Female only) Looking to work in a Japanese MNC to handle office administration at Mahabalipuram, Chennai. Inventory management and coordinate procurement activities. Good communication skill is mandatory Required Candidate profile Any diploma or engineering fresh graduates & certification in office administration is pref. Only Female candidates Willing to work at Mahabalipuram, Chennai Pick up & drop arranged by the company

About Marvell . Your Team, Your Impact Marvells data center engineering group is a leading provider of innovative storage technologies, including ultra fast read channels, high performance processors, leading edge transceivers, highly efficient analog designs, and powerful cryptographic engines. These solutions address all segments of the hard disk drive (HDD) and solid state drive (SSD) electronics markets and accelerator solutions. Many of the same technologies have been utilized in Marvell storage system solutions products, powering PCs, servers, cloud, and enterprise systems. What You Can Expect Design and execute post silicon validation tests for SSD Chipsets, during R&D processes. Develop, port and execute bare metal SW to validate Storage SoCs. Job will involve Pre and Post Si testing of the bare metal functionality of the Storage SoC, including performance, and power. The candidate will also review and prepare test plans and test results documentation. Develop testing and benchmarking applications. Analyze the test results and generate professional validation reports. Provide technical support to Field Application Engineers who support customers. Provide technical support to Test Engineers who design tests for mass production. What Were Looking For We are looking for hardware validation/applications engineer with experience in Solid States Drive. Proficient in C/C++ , Arm Assembly , 64 bit Arm CPU architecture. Experience in Firmware Development under Bare Metal/Linux Environment and Debugging on SoCs for embedded Applications Understanding of SSD controller is preferred Experience in interfaces like NAND/PCIe/NVMe/DDR is a plus Good communication skills in English, written and spoken. Candidate should be flexible, proactive and have the ability to work in a team Should be able to work on a given task independently Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1

About Marvell . Your Team, Your Impact Marvells data center engineering group is a leading provider of innovative storage technologies, including ultra fast read channels, high performance processors, leading edge transceivers, highly efficient analog designs, and powerful cryptographic engines. These solutions address all segments of the hard disk drive (HDD) and solid state drive (SSD) electronics markets. Many of the same technologies have been utilized in Marvell storage system solutions products, powering PCs, servers, cloud, and enterprise systems. What You Can Expect Development, porting, execution, and debug of bare metal SW on multiple SSD blocks to validate proper functionality. Create, maintain and improve code to support new features and standards. Work with Design, FW, and Validation teams to debug any issues found and find root cause on failure cases. Create and review tests plans and prepare test result documents to be shared internally/externally. Create tests to measure performance, throughput, and power of multiple SoC blocks. What Were Looking For Bachelors degree in Software, Computer or Electrical Engineering, and at least 3-5 years professional experience and/or Masters degree in Software, Computer or Electrical Engineering, and at least 2-3 years professional experience, in following domains - Pre-Si Validation, Post-Si Validation, Stress & PVT testing. Excellent C/C++ SW development skills, a good understanding of embedded SW development, Linux and basic knowledge of ARM/RISC micro-processor or SOC architecture. Working knowledge of DDR, SPI, PCIe, NVMe, is a plus. Experience with embedded SW development and proven debug abilities and skills. Familiar with typical lab tools: Emulators, Oscilloscopes, Logic Analyzers. Able to work across disciplines and manage time across several demands. Excellent written and oral communication skills (English). Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1

An experienced and passionate Applications Engineer, ready to join our dynamic team. You thrive in fast-paced environments and are driven by the opportunity to work with high-end customers in the Mobile Industry Processor Interface (MIPI ) domain. With your strong technical background in ASIC design, you are adept at providing top-tier technical support and guidance. Your excellent communication skills enable you to effectively interact with customers and internal teams alike. You are not just looking for a job, but a place where you can make a significant impact and grow your career. What You ll Be Doing: Providing technical support to field engineers and customers utilizing Synopsys MIPI UFS Intellectual Property (IP) Partnering with high-tech customers through the full cycle of ASIC design, from installation and training to RTL design and production testing Conducting reviews on customers major SoC design milestones Authoring application notes and white papers to promote the IPs ease of use and address specific challenges Providing feedback to internal teams for continuous product improvements based on customer feedback Ensuring successful integration of Synopsys MIPI IP solutions into customers SoCs The Impact You Will Have: Enhancing customer satisfaction by providing expert support and ensuring seamless integration of Synopsys IP Driving innovation by collaborating with customers on cutting-edge SoC designs Contributing to the development of industry-leading IP solutions through continuous feedback and improvement processes Expanding Synopsys market presence in the MIPI domain through successful customer engagements Promoting the adoption of Synopsys IP by authoring impactful documentation and white papers Supporting the growth of Synopsys IP portfolio by identifying and addressing customer needs What You ll Need: Bachelors degree with 5+ years or Masters degree with 2+ years of relevant experience in the ASIC design process Proficiency in Verilog HDL, synthesis, simulation, and verification Knowledge of Place and Route, Design Reuse, Physical Design, or Analog Design is a plus Familiarity with MIPI UFS/UniPro protocols, high-speed SERDES, or parallel interfaces is advantageous Experience with Synopsys tool suites is a plus Strong verbal and written communication skills in English

Responsible for Analog design for MSIPs from architecture to production silicon Will set up and manage the team of Analog/Mixed Signal design experts Work out innovative design techniques to overcome challenges Team designs of bandgap, temperature sensors, Signa Delta ADCs , DAC, Voltage monitoring Ips, PLL Ensure right talent is identifies , managed , groomed and enable a stellar team performance Works together with global cross functional team for team s success Qualifications BS or MS degree in Electrical Engineering/Computer Science/Computer Engineering. 10 - 15 years of experience in the fields of Analog/Mixed Signal design for leading edge technologies Innovation mindset with system modelling, architecture and best design practices Ability to lead a large team that will cover different R&D project for AMS IP development . Strong knowledge about custom SOC flow desirable. Understanding of Analog, digital flow and post silicon test/characterization is a desirable skill High in drive and bringing positive energy leading towards a mission Strong personal value system Preferred Skills High drive and people leadership skill Demonstrated experience with Analog/Mixed Signal Design and IP/Product ownership with Analog and Digital subsystems Thorough knowledge of AMS design flow with digital top SOC integration methodology Closely work with Analog Design and layout team by reviewing and guiding for best-in-class performance People management expertise, ability to bring good people and lead them from front

Working on functional verification of high-speed serial link PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards. Studying IP/design blocks/firmware specifications and building/updating verification plans and test cases. Building/updating functional verification environments to execute test plans. Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs) as per verification plan needs. Performing simulation, random and direct stimulus development, and coverage review. Working closely with digital designers for debugging and achieving the desired coverage. The Impact You Will Have: Ensuring the accuracy and functionality of high-speed interface IPs, contributing to the development of cutting-edge technology. Enhancing the reliability and performance of Synopsys products through meticulous verification processes. Driving innovation in the semiconductor industry by verifying complex digital designs. Collaborating with a team of skilled professionals to deliver high-quality IPs that meet industry standards. Improving the efficiency of the verification process through automation and advanced verification methodologies. Contributing to the overall success of Synopsys by ensuring the delivery of robust and reliable IPs to customers.

You are a highly experienced and motivated professional with a solid background in SoC RTL Design . With over 12 years of experience , you have honed your skills in RTL Design, Lint, CDC, RDC, Synthesis, and Constraints Development . You possess a deep understanding of design concepts, ASIC flows, and stakeholder management . Your technical expertise allows you to debug and diagnose violations and errors, set up flows and methodologies for RTL Signoff tools, and develop timing constraints . You are an effective leader, capable of managing and growing a team, providing continuous feedback, and improving the quality of deliverables . Your excellent communication skills help you interact with customers, peers, and management to understand needs, report status, and resolve issues efficiently. What You'll Be Doing: Manage and lead a team of 7-8 SoC/Subsystem RTL Design Engineers for various customer engagements. Work with Synopsys customers to understand their needs and define RTL Signoff and design scope and activities . Lead the team to perform various RTL Design and Signoff activities for SoC Subsystems such as SoC u-Architecture and Integration, RTL Design (Verilog/SystemVerilog), Lint, CDC, RDC, Synthesis, Constraints Development. Assist and mentor the team in day-to-day activities and grow the capabilities of the RTL Design team for future assignments. Review various results and reports to provide continuous feedback to the team and improve the quality of deliverables. Report status to management and provide suggestions to resolve any issues that may impact execution. Understand the complexity and requirements of RTL Quality Signoff and propose resource requirements to complete the activities. Work with peers to improve methodology and improve execution efficiency. Collaborate with other Synopsys teams including BU AEs and Sales to develop, broaden, and deploy Tools. Train the team in design concepts and root-cause analysis. The Impact You Will Have: Drive the successful delivery of SoC Subsystems by leading a skilled team of RTL Design Engineers. Enhance the quality and efficiency of RTL Design and Signoff processes through continuous feedback and methodology improvements. Ensure customer satisfaction by understanding their needs and delivering high-quality solutions. Contribute to the growth and development of the RTL Design team, expanding their capabilities for future projects. Support Synopsys reputation as a leader in chip design and verification through successful project execution. Foster collaboration and innovation within the team and across different Synopsys departments. What You'll Need: B.E/B.Tech/M.E/M.Tech in electronics with a minimum of 12+ years of experience in SoC RTL Design . Technical expertise in various aspects of RTL Design and Signoff: LINT, CDC, RDC. Technical expertise on setting up flows and methodologies for quick deployment of RTL Signoff tools. Technical expertise in debugging and diagnosing violations and errors. Technical expertise in developing timing constraints and running preliminary synthesis for timing constraints check and area estimation. Ability to lead and manage a team to perform RTL Signoff on complex SoC/Subsystem. Experience with planning and managing various activities related to RTL Signoff and Design. Strong understanding of design concepts, ASIC flows, and stakeholders. Good communication skills.

An experienced and visionary ASIC Verification Engineer, Architect who is passionate about driving the future of semiconductor technology. You possess deep functional knowledge and expertise in verification methodologies, and you thrive in an environment where you can influence and implement strategic goals. Your background includes a comprehensive understanding of serial protocols such as PCIe/CXL, UCIe etc. You can define and execute Testbench architecture for protocols such as PCIe/CXL. You are a proactive problem solver, capable of working with minimal oversight, and you excel in communicating complex technical concepts to a diverse audience. Your leadership skills enable you to guide and mentor teams, fostering innovation and excellence in all your projects. What You ll Be Doing: Defining and developing ASIC RTL verification at both chip and block levels. Creating and executing verification plans for complex digital designs, particularly focusing on PCIe/CXL protocols. Collaborating with cross-functional teams to ensure seamless integration and functionality of designs. Utilizing advanced verification methodologies and tools to achieve high-quality results. Mentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement. Communicating with internal and external stakeholders to align on project goals and deliverables. The Impact You Will Have: Enhancing the reliability and performance of Synopsys digital verification processes. Improving time-to-market for robust Synopsys Interface IP controller through efficient verification methodologies. Mentoring and nurturing a highly skilled verification team, elevating overall project quality. Influencing strategic decisions that shape the future of Synopsys capabilities. Ensuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements. What You ll Need: Extensive experience in ASIC RTL verification. In-depth knowledge of PCIe, CXL , UCIe and similar IO protocols. Proficiency in advanced digital design verification tools and methodologies. Strong problem-solving skills and the ability to work independently. Excellent communication skills for effective collaboration with diverse teams. Experience of 15+ years in relevant domain.

You are an experienced and highly motivated professional with a strong background in analog and mixed-signal (A&MS) layout design . You thrive in a collaborative environment and possess a keen eye for detail and design integrity. Your technical expertise in using industry-standard EDA tools , coupled with your problem-solving abilities, makes you a valuable asset to any team. You have a deep understanding of semiconductor process technologies and their impact on layout design, and you are always eager to stay updated with the latest industry trends and advancements. With exceptional communication and interpersonal skills, you work effectively in team-oriented environments and contribute positively to the collective success. What You'll Be Doing: Collaborate with cross-functional teams to develop and implement layout designs for analog and mixed-signal (A&MS) integrated circuits. Create and optimize layout designs using industry-standard EDA tools. Perform physical verification and design rule checks to ensure design integrity and manufacturability. Participate in design reviews and provide feedback to improve design quality. Work closely with circuit designers to understand design specifications and constraints. Contribute to the development and enhancement of layout design methodologies and best practices. Stay updated with the latest industry trends and advancements in A&MS layout design. The Impact You Will Have: Enhance the reliability and performance of our PVT sensor IPs through meticulous layout design. Ensure manufacturability and integrity of designs, avoiding costly errors in production. Contribute to the development of cutting-edge technologies in the semiconductor industry. Support the continuous improvement of design methodologies and best practices. Facilitate the integration of our IPs into SOC subsystems, aiding in the creation of high-performance silicon chips. Drive the technological innovations that keep Synopsys at the forefront of the industry. What You'll Need: Bachelor's or master's degree in electrical engineering or a related field. 3+ years of experience in A&MS layout design for integrated circuits. Proficiency in industry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler. Exceptional knowledge of layout design methods, techniques, and methodologies. Experience with physical verification tools, such as Calibre or Assura.

You are a passionate and meticulous Digital Verification Engineer with a keen interest in functional verification of High Speed interface IPs. With a dynamic personality and a strong eagerness to learn, you are driven to excel in Pre-silicon verification activities. Your understanding of digital design and HDL implementation sets you apart, and you thrive in environments where you can build and update verification plans and test cases . You are well-versed in scripting and automation using TCL, PERL, or Python , and possess excellent debug and diagnostic skills . Collaboration with digital designers is second nature to you, ensuring you achieve the desired coverage and performance in your projects. Your innovative mindset and commitment to excellence make you an invaluable asset to any verification team. What You'll Be Doing: Work on Functional Verification of High speed serial link PHY IPs for USBx, PCIex, Ethernet, Display & HDMI protocol standards. Study IP/design blocks/Firmware Specifications and build/update verification plans as well as the test cases. Build/update functional verification environments to execute the test plans. Implement checkers, assertions, random test generators, high level transactional models, and bus functional models (BFMs) as per the verification plan needs. Perform simulation, random and direct stimulus development, and coverage review. Work closely with digital designers for debug and achieve the desired coverage. The Impact You Will Have: Ensure the reliability and performance of High Speed interface IPs, critical to various advanced technologies. Contribute to the development of cutting-edge verification methodologies. Enhance the quality and efficiency of verification processes. Collaborate effectively with cross-functional teams to achieve project goals. Drive innovation in verification techniques, improving overall product quality. Support the creation of high-performance silicon chips that empower modern technology. What You'll Need: B.Tech/M.Tech with 3+ years of relevant experience. Understanding of functional verification flow with awareness of verification tools and methodologies such as VMM, OVM/UVM, and System Verilog. Proficiency in scripting and automation using TCL, PERL, or Python. Strong debug and diagnostic skills. Experience in building and updating verification environments and test plans.

What You'll Be Doing: Developing emulation solutions for industry-standard protocols such as AXI, AMBA, JTAG, AVB, CAN, and TSN. Engaging in software development using C/C++ and synthesizable RTL development using Verilog. Verifying emulation solutions to ensure they meet the highest standards of quality and performance. Interacting with customers during the deployment and debugging phases to provide technical support and ensure successful implementation. Collaborating with cross-functional teams to integrate emulation solutions with other Synopsys products and technologies. Continuously improving and optimizing emulation solutions to meet evolving industry needs and standards. The Impact You Will Have: Enhancing the efficiency and performance of semiconductor design processes through advanced emulation solutions. Contributing to the development of high-performance silicon chips and software content that drive technological innovation. Supporting semiconductor customers in overcoming design and verification challenges, leading to successful product launches. Improving the reliability and functionality of emulation solutions, thereby increasing customer satisfaction and trust in Synopsys products. Driving continuous improvement and innovation within the emulation solutions domain. Facilitating seamless integration of emulation solutions with other Synopsys technologies, enhancing overall product offerings. What You'll Need: Strong programming skills in C/C++ and understanding of OOPS concepts. Good understanding of digital design concepts. Knowledge of HDL languages such as System Verilog and Verilog. Experience with scripting languages like Perl or TCL is a plus. Understanding of ARM architecture is an added advantage. Knowledge of UVM and functional verification will be a plus.

Develop Multiport SRAM/Register file architectures and circuit implementation techniques. Schematic entry, simulation of major blocks, layout planning, layout supervision and interface with CAD team for full verification and model generation. Designing and implementing optimum low-power and area-efficient embedded memory (SRAM, register files, etc.) circuits and architectures. Learn and apply skills in memory compilers having Transistor level circuit Design. Resolves a wide range of issues in creative ways Inter-team interaction customer focus Frequently networks with senior internal and external personnel in own area of expertise Experience of FinFet Technology for Memory Design Can coordinate, facilitate and monitor the daily activities of a small to large group of support resources within their section or project team While holding a leadership role is able to control to the memory development at a prominent level With minimal supervision, prioritizes workload to successfully manage multiple tasks and responsibilities Proactively addresses and communicates issues impacting productivity In this role, the Staff Engineer will be part of team contributing to Different type of Architectures of embedded SRAM, Register files and ROM. As Staff Engineer, the individual will be involved in challenging projects and drive it to completion in record time. You will quickly ramp on the existing flow, understand the challenges, and produce the work plan. Your expertise in deep submicron technology and Finfet, SRAM design , processor design , Digital design flow and teamwork skills will be highly leveraged to guide activity across the entire cross-discipline, multi-site team. You will work with others to identify the issues, get buy-in on proposed solutions, and implement the solutions in time for the team to execute to schedule. Skills/Experience: BE/B.Tech/ME/M.Tech/MS in Electrical & Electronics Engineering from premium institute/university with minimum of 4 years of experience in VLSI Design Deep understanding of SRAM/Register File architectures and advanced custom circuit implementations. Exposure to full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, timing and model generation. Direct experience with the most advanced technology nodes. Familiarity with variation-aware design in nanometre technology nodes Wmastery in scripting using Perl, python for automation Deep understanding of SRAM single port and multi-port design Fundamentals: Understanding of RC circuit of 1 st and 2 nd order. Basics of Digital design (realizationof Boolean function using Gates, Mux etc) Fundamentals of Transfer function and its analysis for stability etc. Strong CMOS fundamentals Knowledge of CMOS fabrication Good digital design knowledge

Applications Engineer position offers a wonderful opportunity to work on most challenging technical problems in verification domain and innovative technologies under Synopsys Verification Platform. Looking for an experienced and motivated professional who enjoys problem solving, open to continuous learning, passionate to work on cutting edge technologies and has excellent communication skills. It gives exposure to the breadth of HDL/HVL, methodologies, static and formal verification, dynamic simulation aspects including debug and experience in working in a diverse environment where interaction with domain experts across global locations will be involved. Key Requirements Experience: Bachelors degree in Electronics with 7+ Years or Master s degree in Electronics with 5+ Years Experience in verification technologies (Simulation, UVM, SVA, LRM understanding) Strong HDL language support (Verilog, VHDL, System Verilog) Simulation, UVM, Design Verification Digital design fundamental and RTL coding understanding Good Debugging skills. Scripting - Perl, TCL, Make, Shell Scripting. Role - VCS Simulation Technology Product Engineer Solid fundamentals in Digital design, HDLs (Verilog/VHDL) and System Verilog Exposure to Synopsys EDA tools (SpyGlass, VC SpyGlass, Verdi) would be added advantage Excellent written and oral communication skills is a must as the role requires interfacing global teams, proposing solutions Must have working knowledge on UNIX, TCL and/or any other scripting language to be effective Team player, partners with multiple stakeholders, has attention to detail and innovative mindset Motivated, doer and self-organized team worker with good social communication skills Open to travel, ability to multi-task, be detail-oriented Drive VCS/related technology customer deployment working closely with field and R&D Drive competitive engagements, requirements gathering for delivery strong product roadmap Work directly with R&D, Product Validation & Customers to suggest improvements in implementation and validation Use in-depth product understanding to provide technical expertise, diagnose, troubleshoot issues

Designing and implementing SOC solutions for various applications, ensuring high performance and reliability. Collaborating with cross-functional teams to define and develop SOC architecture and specifications. Conducting verification and validation of SOC designs to ensure compliance with industry standards and customer requirements. Optimizing SOC designs for power, performance, and area (PPA) to meet project objectives. Debugging and resolving issues in SOC designs, utilizing advanced tools and methodologies. Providing technical guidance and mentorship to junior engineers, fostering a culture of continuous improvement and innovation. Job Description and Requirements The role is for RTL Design and Signoff of IP/Subsystem/SoC Design in the System Solutions Group (SSG). At SSG, we are a team of experts in various Synopsys technologies to deliver architecture, design, verification, implementation, tools, and methodology to enable our customers to complete their most challenging SoC Design projects. Our work spans from sub-blocks to full turnkey end-to-end SoCs. Our customers range from start-ups to industry leaders, commercial companies, and government agencies. As part of this role, you can expect to develop and deliver your expertise in RTL Signoff and RTL Design Techniques while working on activities such as Lint/CDC/RDC Checks, Timing Constraints Development, Preliminary Synthesis, Formality, and RTL Design. The role will expose you to various innovative technologies deployed for RTL Quality Signoff for Semiconductors. Responsibilities Perform RTL Quality Signoff Checks such as LINT, CDC, RDC. Understand the design/architecture and develop timing constraints for synthesis and timing. Run preliminary synthesis to ensure that the design can be synthesized as intended. Run formality to ensure equivalence of RTL and gates. Integrate IPs in SoCs/Subsystems and create RTL design as per need of the customer.